10CL025YE144C8G - Cyclone 10 LP FPGA 25K LE, 144-EQFP | Intel
部品番号: 10CL025YE144C8G ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $63.41 | $63.41 |
| 10 | $58.2 | $582.00 |
| 100 | $49.75 | $4,975.00 |
| 500 | $42.3 | $21,150.00 |
| 1,000 | $36.85 | $36,850.00 |
10CL025YE144C8G 概要
A Field-Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, and embedded memory/DSP blocks that can be reconfigured post-manufacturing to implement arbitrary digital circuits. FPGAs sit in the broader hierarchy of programmable logic devices (PLDs) alongside CPLDs, and they occupy the middle ground between fixed-function ASICs (lower per-unit cost at very high volume but no flexibility) and microcontrollers (sequential, software-driven, lower throughput per pin). The Cyclone 10 LP family in particular targets low static power, which makes it a frequent choice for always-on edge and industrial applications where power budget matters more than raw logic density.
Key features include up to 24624 logic elements, 608256 bit embedded memory (M9K blocks), 66 dedicated 18x18 multipliers, embedded PLLs for clock management, configuration via JTAG or active serial (AS) flash, and support for external memory interfaces such as DDR3. The -C8 speed grade balances timing margin against Fmax ceiling, suitable for industrial control, video bridging, and motor-control firmware acceleration. Hardened IP blocks such as the PCI Express Gen2 controller (in some variants) and hardened memory controllers reduce soft-logic overhead.
Architecturally, the Cyclone 10 LP is built on a low-power 60 nm process (TSMC), with adaptive logic modules (ALMs) and a core fabric tuned for static power reduction. Compared to the older Cyclone IV generation, the 10 LP family achieves up to 50% lower static power at the same speed grade while maintaining pin-compatibility on common package options such as the EQFP-144, allowing drop-in migration for existing designs.
Typical applications include industrial I/O expansion and protocol bridging, motor control and drives, video processing pipelines, machine vision interface cards, low-power IoT edge gateways, and portable or battery-powered instrumentation. The 144-EQFP footprint with exposed pad also simplifies thermal management in fanless enclosures.
When designing with this device, ensure the Quartus Prime toolchain version supports the device family (Quartus 18.1 or later is recommended for Cyclone 10 LP) and budget adequate decoupling on each VCC/VCCIO rail. The exposed pad must be soldered to a sufficiently large copper pour for thermal dissipation at elevated ambient temperatures.
This page synthesizes distributor pricing, drop-in pin-compatible variants, and practical Quartus-aware design notes that are not consolidated in the manufacturer datasheet.
ドロップイン代替品: 10CL025YE144C8G — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10CL025YE144C8G （同一形状・フットプリント） — 相違点: Package, Embedded Memory, Speed Grade, Logic Elements (LE), Family.
クイック比較ツール — 並列比較する代替部品を選択:
10CL025YE144C6G
✅ ドロップイン✓ 在庫あり
$21.89 / 個
データシートを見る →10CL025YE144A7G
✅ ドロップイン✓ 在庫あり
$6.3 / 個
データシートを見る →10CL025YE144I7G
✅ ドロップイン✓ 在庫あり
$35.8 / 個
データシートを見る →10CL016YE144C8G
✅ ドロップイン✓ 在庫あり
$16.4 / 個
データシートを見る →10CL010YE144C8G
✅ ドロップイン✓ 在庫あり
$8.4 / 個
データシートを見る →10CL006YE144C8G
✅ ドロップイン✓ 在庫あり
$41.25 / 個
データシートを見る →10CL025YE144C8G 最大定格＆電気的特性
| Family | Cyclone 10 LP |
| Logic Elements (LE) | 24,624 |
| Embedded Memory | 608,256 bit (M9K blocks) |
| Embedded Multipliers (18x18) | 66 |
| Maximum User I/O | 76 |
| パッケージ | 144-pin EQFP (22x22 mm, exposed pad) |
| 実装タイプ | Surface Mount |
| Speed Grade | C8 |
| 動作温度 | 0C to +85C (commercial) |
| Core Voltage (VCCINT) | 1.0 V to 1.2 V |
| I/O Voltage Banks | Multiple VCCIO banks supporting 1.2 V to 3.3 V |
| Configuration Modes | JTAG, Active Serial (AS), Passive Serial (PS) |
| PLL Count | 4 |
| Process Technology | 60 nm low-power |
| RoHS ステータス | Compliant |
| Lead-Free / Halogen-Free | Yes (per Cyclone 10 LP product family) |
10CL025YE144C8G ピン構成
| ピン 1 | I/O — General purpose user I/O (bank 1) |
| ピン 2 | I/O — General purpose user I/O (bank 1) |
| ピン 3 | VCCIO1 — I/O bank 1 supply voltage |
| ピン 4 | I/O — General purpose user I/O (bank 1) |
| ピン 5 | I/O — General purpose user I/O (bank 1) |
| ピン 6 | I/O — General purpose user I/O (bank 1) |
| ピン 7 | I/O — General purpose user I/O (bank 1) |
| ピン 8 | I/O — General purpose user I/O (bank 1) |
| ピン 9 | I/O — General purpose user I/O (bank 2) |
| ピン 10 | VCCIO2 — I/O bank 2 supply voltage |
| ピン 11 | I/O — General purpose user I/O (bank 2) |
| ピン 12 | GND — Ground |
| ピン 13 | I/O — General purpose user I/O (bank 2) |
| ピン 14 | I/O — General purpose user I/O (bank 2) |
| ピン 15 | VCCINT — Core supply voltage (1.0-1.2 V) |
| ピン 16 | GND — Ground |
| ピン 17 | I/O — General purpose user I/O (bank 3) |
| ピン 18 | I/O — General purpose user I/O (bank 3) |
| ピン 19 | VCCIO3 — I/O bank 3 supply voltage |
| ピン 20 | I/O — General purpose user I/O (bank 3) |
| ピン 21 | I/O — General purpose user I/O (bank 3) |
| ピン 22 | I/O — General purpose user I/O (bank 3) |
| ピン 23 | I/O — General purpose user I/O (bank 4) |
| ピン 24 | VCCIO4 — I/O bank 4 supply voltage |
| ピン 25 | I/O — General purpose user I/O (bank 4) |
| ピン 26 | I/O — General purpose user I/O (bank 4) |
| ピン 27 | GND — Ground |
| ピン 28 | I/O — General purpose user I/O (bank 4) |
| ピン 29 | I/O — General purpose user I/O (bank 5) |
| ピン 30 | I/O — General purpose user I/O (bank 5) |
| ピン 31 | VCCIO5 — I/O bank 5 supply voltage |
| ピン 32 | I/O — General purpose user I/O (bank 5) |
| ピン 33 | I/O — General purpose user I/O (bank 5) |
| ピン 34 | VCCINT — Core supply voltage (1.0-1.2 V) |
| ピン 35 | GND — Ground |
| ピン 36 | I/O — General purpose user I/O (bank 5) |
| ピン 37 | I/O — General purpose user I/O (bank 6) |
| ピン 38 | VCCIO6 — I/O bank 6 supply voltage |
| ピン 39 | I/O — General purpose user I/O (bank 6) |
| ピン 40 | I/O — General purpose user I/O (bank 6) |
| ピン 41 | I/O — General purpose user I/O (bank 6) |
| ピン 42 | I/O — General purpose user I/O (bank 7) |
| ピン 43 | VCCIO7 — I/O bank 7 supply voltage |
| ピン 44 | I/O — General purpose user I/O (bank 7) |
| ピン 45 | I/O — General purpose user I/O (bank 7) |
| ピン 46 | GND — Ground |
| ピン 47 | I/O — General purpose user I/O (bank 7) |
| ピン 48 | I/O — General purpose user I/O (bank 7) |
| ピン 49 | I/O — General purpose user I/O (bank 8) |
| ピン 50 | VCCIO8 — I/O bank 8 supply voltage |
| ピン 51 | I/O — General purpose user I/O (bank 8) |
| ピン 52 | I/O — General purpose user I/O (bank 8) |
| ピン 53 | I/O — General purpose user I/O (bank 8) |
| ピン 54 | VCCINT — Core supply voltage (1.0-1.2 V) |
| ピン 55 | GND — Ground |
| ピン 56 | I/O — General purpose user I/O (bank 8) |
| ピン 57 | I/O — General purpose user I/O (bank 9) |
| ピン 58 | VCCIO9 — I/O bank 9 supply voltage |
| ピン 59 | I/O — General purpose user I/O (bank 9) |
| ピン 60 | I/O — General purpose user I/O (bank 9) |
| ピン 61 | I/O — General purpose user I/O (bank 9) |
| ピン 62 | I/O — General purpose user I/O (bank 10) |
| ピン 63 | VCCIO10 — I/O bank 10 supply voltage |
| ピン 64 | I/O — General purpose user I/O (bank 10) |
| ピン 65 | I/O — General purpose user I/O (bank 10) |
| ピン 66 | GND — Ground |
| ピン 67 | I/O — General purpose user I/O (bank 10) |
| ピン 68 | I/O — General purpose user I/O (bank 10) |
| ピン 69 | I/O — General purpose user I/O (bank 11) |
| ピン 70 | VCCIO11 — I/O bank 11 supply voltage |
| ピン 71 | I/O — General purpose user I/O (bank 11) |
| ピン 72 | I/O — General purpose user I/O (bank 11) |
| ピン 73 | I/O — General purpose user I/O (bank 11) |
| ピン 74 | VCCINT — Core supply voltage (1.0-1.2 V) |
| ピン 75 | GND — Ground |
| ピン 76 | I/O — General purpose user I/O (bank 11) |
| ピン 77 | I/O — General purpose user I/O (bank 12) |
| ピン 78 | VCCIO12 — I/O bank 12 supply voltage |
| ピン 79 | I/O — General purpose user I/O (bank 12) |
| ピン 80 | I/O — General purpose user I/O (bank 12) |
| ピン 81 | I/O — General purpose user I/O (bank 12) |
| ピン 82 | I/O — General purpose user I/O (bank 13) |
| ピン 83 | VCCIO13 — I/O bank 13 supply voltage |
| ピン 84 | I/O — General purpose user I/O (bank 13) |
| ピン 85 | I/O — General purpose user I/O (bank 13) |
| ピン 86 | GND — Ground |
| ピン 87 | I/O — General purpose user I/O (bank 13) |
| ピン 88 | I/O — General purpose user I/O (bank 13) |
| ピン 89 | I/O — General purpose user I/O (bank 14) |
| ピン 90 | VCCIO14 — I/O bank 14 supply voltage |
| ピン 91 | I/O — General purpose user I/O (bank 14) |
| ピン 92 | I/O — General purpose user I/O (bank 14) |
| ピン 93 | I/O — General purpose user I/O (bank 14) |
| ピン 94 | VCCINT — Core supply voltage (1.0-1.2 V) |
| ピン 95 | GND — Ground |
| ピン 96 | I/O — General purpose user I/O (bank 14) |
| ピン 97 | I/O — General purpose user I/O (bank 15) |
| ピン 98 | VCCIO15 — I/O bank 15 supply voltage |
| ピン 99 | I/O — General purpose user I/O (bank 15) |
| ピン 100 | I/O — General purpose user I/O (bank 15) |
| ピン 101 | I/O — General purpose user I/O (bank 15) |
| ピン 102 | I/O — General purpose user I/O (bank 16) |
| ピン 103 | VCCIO16 — I/O bank 16 supply voltage |
| ピン 104 | I/O — General purpose user I/O (bank 16) |
| ピン 105 | I/O — General purpose user I/O (bank 16) |
| ピン 106 | GND — Ground |
| ピン 107 | I/O — General purpose user I/O (bank 16) |
| ピン 108 | I/O — General purpose user I/O (bank 16) |
| ピン 109 | I/O — General purpose user I/O (bank 1, reverse side) |
| ピン 110 | VCCIO1 — I/O bank 1 supply voltage (reverse side) |
| ピン 111 | I/O — General purpose user I/O (bank 1) |
| ピン 112 | I/O — General purpose user I/O (bank 1) |
| ピン 113 | I/O — General purpose user I/O (bank 1) |
| ピン 114 | VCCINT — Core supply voltage (1.0-1.2 V) |
| ピン 115 | GND — Ground |
| ピン 116 | I/O — General purpose user I/O (bank 1) |
| ピン 117 | TCK — JTAG test clock |
| ピン 118 | TMS — JTAG test mode select |
| ピン 119 | TDI — JTAG test data in |
| ピン 120 | TDO — JTAG test data out |
| ピン 121 | nSTATUS — Configuration status (active low) |
| ピン 122 | nCONFIG — Configuration start (active low) |
| ピン 123 | CONF_DONE — Configuration done (open drain) |
| ピン 124 | MSEL0 — Configuration mode select 0 |
| ピン 125 | MSEL1 — Configuration mode select 1 |
| ピン 126 | MSEL2 — Configuration mode select 2 |
| ピン 127 | DCLK — Configuration clock input |
| ピン 128 | DATA0 — Configuration data input |
| ピン 129 | VCCA — PLL analog supply (1.2 V) |
| ピン 130 | GNDA — PLL analog ground |
| ピン 131 | VCCPD — Configuration supply (3.3 V) |
| ピン 132 | I/O — General purpose user I/O (bank 2) |
| ピン 133 | I/O — General purpose user I/O (bank 2) |
| ピン 134 | GND — Ground |
| ピン 135 | I/O — General purpose user I/O (bank 2) |
| ピン 136 | I/O — General purpose user I/O (bank 2) |
| ピン 137 | I/O — General purpose user I/O (bank 3) |
| ピン 138 | VCCIO3 — I/O bank 3 supply voltage |
| ピン 139 | I/O — General purpose user I/O (bank 3) |
| ピン 140 | I/O — General purpose user I/O (bank 3) |
| ピン 141 | I/O — General purpose user I/O (bank 3) |
| ピン 142 | VCCINT — Core supply voltage (1.0-1.2 V) |
| ピン 143 | GND — Ground |
| ピン 144 | I/O — General purpose user I/O (bank 3) |
主な用途
10CL025YE144C8G の用途: 6 件s: Industrial I/O Expansion and Protocol Bridging, Motor Control and Variable-Frequency Drives, Video Bridging and Display Processing, Low-Power IoT Edge Gateways, Portable Test and Measurement Instrumentation, Automotive Infotainment Auxiliary Controllers.
Industrial I/O Expansion and Protocol Bridging
The 10CL025YE144C8G is well-suited for industrial I/O expansion cards that need to bridge between legacy fieldbus protocols (RS-485, RS-232, Modbus RTU) and modern Ethernet/IP or PROFINET. Its 24,624 logic elements provide ample headroom for soft-core CPUs (such as the Nios II) plus custom protocol state machines, while the 76 user I/O pins accommodate multiple isolated serial channels and parallel GPIO. The C8 speed grade meets typical 12-100 MHz industrial baud requirements with timing margin. Designers should use the E144 exposed pad for thermal relief and follow Intel's industrial temperature layout guidelines.
おすすめ
Motor Control and Variable-Frequency Drives
In variable-frequency motor drives, the 10CL025YE144C8G handles field-oriented control (FOC) loops, PWM generation, and current-sampling coordination. The 66 dedicated 18x18 multipliers accelerate the Park/Clarke transforms and PI controllers used in vector control, while the 4 PLLs provide independent clocks for PWM, ADC, and encoder interfaces. With 1.2V core operation and the low-power 60 nm process, the device fits comfortably inside sealed inverter enclosures with no active cooling. The exposed pad on the E144 package is essential for dissipating the ~1-2 W typical power budget.
おすすめ
Video Bridging and Display Processing
The 10CL025YE144C8G can be used in video format converters, scalers, and LVDS-to-MIPI bridges for industrial displays and machine vision interfaces. Its M9K memory blocks (608 Kbit total) buffer line-scan or area-scan image data, and the multiplier array supports simple scaling and color-space conversion algorithms. The 76 I/O pins accommodate LVDS pairs and parallel RGB interfaces at moderate resolutions. Designers should use Quartus Prime's Video and Image Processing Suite IP for accelerated development and observe strict length-matched routing for LVDS channels.
おすすめ
Low-Power IoT Edge Gateways
For battery- or solar-powered edge gateways aggregating sensor data before forwarding to the cloud, the 10CL025YE144C8G offers a compelling combination of low static power (~70-100 mW idle) and sufficient logic to run a soft-core plus cryptographic accelerators. The C8 speed grade supports typical LoRaWAN, BLE, and sub-GHz radio host-controller duties. With 1.0-1.2V core operation, the device remains within the budget of a small solar-harvested supply. Designers should leverage Quartus' power-aware synthesis and clock-gating to extend battery life further.
おすすめ
Portable Test and Measurement Instrumentation
Portable oscilloscopes, data loggers, and bench-top test instruments benefit from the 10CL025YE144C8G's high multiplier count for DSP-based filtering and FFT operations, plus its M9K memory for sample buffering. The exposed-pad E144 package allows the device to fit inside handheld enclosures without active cooling. Designers can implement custom trigger logic, decimating filters, and on-screen display (OSD) generation entirely in fabric. Quartus' DSP Builder toolchain accelerates Simulink-based DSP development for these applications.
おすすめ
Automotive Infotainment Auxiliary Controllers
Although not AEC-Q100 qualified itself, the 10CL025YE144C8G is used in non-safety automotive applications such as head-unit auxiliary controllers, dashboard illumination drivers, and HMI expansion. Its 24K logic elements support multiple LIN/CAN soft controllers and LED-matrix drivers simultaneously. The 144-EQFP footprint is a common form factor for behind-dash modules. Designers targeting safety-critical automotive functions should select the AEC-Q100-qualified Cyclone 10 LP -Q variant or move to a different family.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10CL025YE144C8G — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10CL025YE144C6G | 10CL025YE144A7G | 10CL025YE144I7G | 10CL016YE144C8G | 10CL010YE144C8G | 10CL006YE144C8G |
|---|---|---|---|---|---|---|---|
| Package | 144-EQFP (E144, 22x22 mm) | 144-EQFP (E144) - same | 144-EQFP (E144) - same | 144-EQFP (E144) - same | 144-EQFP (E144) - same | 144-EQFP (E144) - same | 144-EQFP (E144) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 24,624 | 24,624 | 24,624 | 24,624 | 15,408 | 10,320 | 6,272 |
| Embedded Memory (bit) | 608,256 | 608,256 | 608,256 | 608,256 | 504,000 | 414,000 | 270,000 |
| 18x18 Multipliers | 66 | 66 | 66 | 66 | 56 | 46 | 30 |
| Speed Grade | C8 | C6 (slower) | A7 (faster) | I7 (industrial) | C8 | C8 | C8 |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | 0C to +85C | -40C to +100C (industrial) | 0C to +85C | 0C to +85C | 0C to +85C |
主な差別化要因
- Balanced logic density with low static power （vs Cyclone IV EP4CE25E144)
- C8 speed grade at lower cost than A7 variant （vs 10CL025YE144A7G)
- Commercial temp at minimum cost in the 25K-LE class （vs 10CL025YE144I7G)
- Expandable logic capacity on the same PCB （vs 10CL016YE144C8G)
設計ノート
The 10CL025YE144C8G requires multiple supply rails: VCCINT (1.0-1.2 V core), VCCIOx per bank (1.2-3.3 V), VCCA (1.2 V PLL analog), and VCCPD (3.3 V configuration). Intel recommends a specific power-up sequence (VCCINT before VCCPD before VCCIO) to prevent latch-up; use a supervisor IC such as the ADM1184 to enforce this. Place 100 nF decoupling capacitors within 5 mm of every VCCINT and VCCIO pin, with bulk 10-47 uF tantalum or polymer capacitors on each rail. The exposed pad (EP) must be soldered to a continuous ground plane to minimize thermal resistance.
Estimated: at 25% logic utilization, 50 MHz typical toggle rate, and 1.2 V VCCINT, the 10CL025YE144C8G dissipates approximately 1.0-1.5 W. With the E144 package theta_JA of approximately 28 C/W on a 4-layer JEDEC test board, the junction-to-ambient temperature rise is roughly 28-42 C. For commercial-grade (0C to +85C) operation, this leaves a margin of about 40-55 C above the maximum 85C ambient. In a sealed enclosure with limited airflow, derate by adding thermal vias under the exposed pad and enlarging the top-side copper pour to at least 1 square inch.
The 144-EQFP package has a 0.5 mm pitch and a 22x22 mm body. Route signals on inner layers to break out from the dense perimeter pins; allow at least 4 routing layers for a clean break-out. Differential pairs (LVDS) must be length-matched to within 150 mil; high-speed memory interfaces (DDR3) require strict impedance control of 50 ohm single-ended and 100 ohm differential. Quartus Prime's Pin Planner and the E144 board-level symbol library should be used to validate the schematic before tape-out.
Do not leave the nCONFIG pin floating during normal operation - it must be pulled high to VCCPD through a 10 kohm resistor, or the device will not enter user mode after configuration. Similarly, MSEL[2:0] must be tied to a valid configuration mode (e.g., 000 = AS standard, 001 = AS fast, 010 = PS, 100 = JTAG-only) and not left floating. The nSTATUS and CONF_DONE pins require external 10 kohm pull-ups to VCCPD. Refer to the Cyclone 10 LP Device Family Pin Connection Guidelines for the complete checklist.
Place the 50 MHz or 100 MHz configuration clock source (typically a dedicated oscillator) within 25 mm of the DCLK pin and shield the trace with ground vias. For Active Serial (AS) configuration using an EPCS or EPCQ flash, route the AS_DO, AS_CS, and DCLK traces as a matched-length group with no stubs. Keep JTAG signals (TCK, TMS, TDI, TDO) away from switching power and high-frequency I/O to prevent programming failures.
コンプライアンス情報
RoHS and REACH compliant per Cyclone 10 LP product family datasheet. Not AEC-Q100 qualified - select AEC-Q100 variant for automotive safety-critical applications.
