10M04SCM153I7G - MAX 10 FPGA 4K LE, 153-BGA, Industrial | Intel
部品番号: 10M04SCM153I7G ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $16.5 | $16.50 |
| 10 | $14.85 | $148.50 |
| 100 | $12.3 | $1,230.00 |
| 500 | $10.45 | $5,225.00 |
| 1,000 | $9.2 | $9,200.00 |
10M04SCM153I7G 概要
What is a MAX 10 FPGA? A Field-Programmable Gate Array is a reconfigurable digital logic device consisting of programmable logic elements, embedded memory blocks, DSP slices, and a programmable interconnect fabric. MAX 10 (within Intel's FPGA taxonomy: FPGA -> non-volatile FPGA -> low-power CPLD/FPGA family) uniquely integrates instant-on flash configuration with analog and DSP blocks, bridging the gap between traditional CPLDs and higher-density Cyclone / Stratix families. The 10M04 is the entry-level density tier of the MAX 10 lineup.
Key features include up to 193,536 bits of embedded user flash (added to the user-accessible SRAM budget), a 12-bit 1 Msps ADC with up to 17 analog inputs, hard memory controllers (DDR3/DDR3L/LPDDR2), and up to 45 multipliers (18x18). The 153-ball MBGA package is just 8x8 mm with a 0.5 mm ball pitch, supporting densities above 30,000 logic cells when migrating within the MAX 10 family.
Architecturally, MAX 10 uses logic array blocks (LABs) of 16 logic elements, each LE containing a 4-input LUT, register, and carry chain. The embedded flash reduces BOM cost by eliminating external boot PROM. The industrial -40C to +100C operating range suits factory, automotive aftermarket, and outdoor industrial deployments.
Typical applications include industrial I/O expansion and glue logic, motor control, sensor aggregation in IoT edge nodes, video bridging, and human-machine interface (HMI) controllers. Designers also use 10M04 for protocol bridging (UART/SPI/I2C to Ethernet) and as a low-cost replacement for CPLD-based state machines requiring soft-core processors.
When designing, account for bank-dependent I/O voltage (each bank is independently 1.2/1.5/1.8/2.5/3.0/3.3 V) and use the Quartus Prime Lite toolchain (free) for synthesis, place-and-route, and programming file generation. A JTAG or on-chip flash programmer is required for in-system configuration.
This page synthesizes distributor pricing, drop-in package-compatible MAX 10 variants, and design notes not found in the standalone datasheet, enabling faster component selection for low-density FPGA designs.
ドロップイン代替品: 10M04SCM153I7G — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10M04SCM153I7G （同一形状・フットプリント） — 相違点: Package, Speed Grade, Configuration Memory, Temperature Grade, Family.
クイック比較ツール — 並列比較する代替部品を選択:
10M04SAM153I7G
✅ ドロップイン✓ 在庫あり
$9.2 / 個
データシートを見る →10M04SCM153C8G
✅ ドロップイン✓ 在庫あり
$7.49 / 個
データシートを見る →10M04SAM153C8G
✅ ドロップイン✓ 在庫あり
$4.85 / 個
データシートを見る →10M04SCE144I7G
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$10.26 / 個
データシートを見る →10M04SCM153I7G 最大定格＆電気的特性
| Family | MAX 10 |
| Logic Elements (LE) | 4,000 |
| Embedded Memory (bits) | 193,536 |
| Maximum User I/O | 112 |
| パッケージ | 153-ball MBGA (Micro FineLine BGA), 8x8 mm, 0.5 mm pitch |
| Process Technology | 55 nm |
| Core Voltage | 1.2 V |
| I/O Voltage Standards | LVCMOS 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V |
| Embedded Memory Type | M9K (9 Kbit blocks) |
| User Flash (CFM/UFM) | Available (configurable flash + user flash) |
| DSP Blocks (18x18 Multipliers) | 16 |
| PLLs | 2 |
| On-chip ADC | 12-bit, 1 Msps, up to 17 analog inputs |
| Speed Grade | SC (commercial/industrial slow) |
| Temperature Grade | Industrial (I), -40C to +100C |
| Configuration Method | On-chip flash + JTAG |
| Lead-free / RoHS | Yes (7G suffix) |
| 実装タイプ | Surface Mount (BGA) |
10M04SCM153I7G ピン構成
| ピン A1 | IO — User I/O (bank-specific voltage) |
| ピン A2 | IO — User I/O (bank-specific voltage) |
| ピン A3 | IO — User I/O (bank-specific voltage) |
| ピン A4 | VCCIO — I/O bank supply voltage |
| ピン A5 | VCCIO — I/O bank supply voltage |
| ピン A6 | IO — User I/O (bank-specific voltage) |
| ピン A7 | IO — User I/O (bank-specific voltage) |
| ピン A8 | IO — User I/O (bank-specific voltage) |
| ピン A9 | IO — User I/O (bank-specific voltage) |
| ピン A10 | IO — User I/O (bank-specific voltage) |
| ピン A11 | IO — User I/O (bank-specific voltage) |
| ピン B1 | IO — User I/O (bank-specific voltage) |
| ピン B2 | GND — Ground |
| ピン B3 | GND — Ground |
| ピン B4 | VCC — Core voltage 1.2 V |
| ピン B5 | VCC — Core voltage 1.2 V |
| ピン B6 | GND — Ground |
| ピン B7 | GND — Ground |
| ピン B8 | VCCIO — I/O bank supply voltage |
| ピン B9 | VCCIO — I/O bank supply voltage |
| ピン B10 | GND — Ground |
| ピン B11 | IO — User I/O (bank-specific voltage) |
| ピン C1 | IO — User I/O (bank-specific voltage) |
| ピン C2 | IO — User I/O (bank-specific voltage) |
| ピン C3 | GND — Ground |
| ピン C4 | VCCIO — I/O bank supply voltage |
| ピン C5 | GND — Ground |
| ピン C6 | VCCIO — I/O bank supply voltage |
| ピン C7 | VCC — Core voltage 1.2 V |
| ピン C8 | GND — Ground |
| ピン C9 | VCC — Core voltage 1.2 V |
| ピン C10 | IO — User I/O (bank-specific voltage) |
| ピン C11 | IO — User I/O (bank-specific voltage) |
| ピン D1 | IO — User I/O (bank-specific voltage) |
| ピン D2 | GND — Ground |
| ピン D3 | VCCIO — I/O bank supply voltage |
| ピン D4 | GND — Ground |
| ピン D5 | VCCIO — I/O bank supply voltage |
| ピン D6 | VCC — Core voltage 1.2 V |
| ピン D7 | GND — Ground |
| ピン D8 | VCC — Core voltage 1.2 V |
| ピン D9 | VCCIO — I/O bank supply voltage |
| ピン D10 | GND — Ground |
| ピン D11 | IO — User I/O (bank-specific voltage) |
| ピン E1 | IO — User I/O (bank-specific voltage) |
| ピン E2 | VCCIO — I/O bank supply voltage |
| ピン E3 | GND — Ground |
| ピン E4 | VCC — Core voltage 1.2 V |
| ピン E5 | VCC — Core voltage 1.2 V |
| ピン E6 | GND — Ground |
| ピン E7 | VCC — Core voltage 1.2 V |
| ピン E8 | GND — Ground |
| ピン E9 | VCC — Core voltage 1.2 V |
| ピン E10 | IO — User I/O (bank-specific voltage) |
| ピン E11 | IO — User I/O (bank-specific voltage) |
| ピン F1 | IO — User I/O (bank-specific voltage) |
| ピン F2 | GND — Ground |
| ピン F3 | VCCIO — I/O bank supply voltage |
| ピン F4 | VCC — Core voltage 1.2 V |
| ピン F5 | TCK — JTAG test clock |
| ピン F6 | TMS — JTAG test mode select |
| ピン F7 | TDI — JTAG test data in |
| ピン F8 | TDO — JTAG test data out |
| ピン F9 | VCC — Core voltage 1.2 V |
| ピン F10 | VCCIO — I/O bank supply voltage |
| ピン F11 | GND — Ground |
| ピン G1 | IO — User I/O (bank-specific voltage) |
| ピン G2 | VCCIO — I/O bank supply voltage |
| ピン G3 | GND — Ground |
| ピン G4 | nCONFIG — Configuration start (active low) |
| ピン G5 | nSTATUS — Configuration status (active low) |
| ピン G6 | CONFIG_DONE — Configuration complete |
| ピン G7 | CRC_ERROR — CRC error indicator |
| ピン G8 | DEV_CLRn — Device clear (active low) |
| ピン G9 | DEV_OE — Device output enable |
| ピン G10 | VCCIO — I/O bank supply voltage |
| ピン G11 | IO — User I/O (bank-specific voltage) |
| ピン H1 | IO — User I/O (bank-specific voltage) |
| ピン H2 | GND — Ground |
| ピン H3 | VCCIO — I/O bank supply voltage |
| ピン H4 | VCC — Core voltage 1.2 V |
| ピン H5 | VCCA_ADC — ADC analog supply (2.5 V) |
| ピン H6 | ADCIN1 — Analog input channel 1 |
| ピン H7 | ADCIN2 — Analog input channel 2 |
| ピン H8 | VREF — ADC reference voltage |
| ピン H9 | VCC — Core voltage 1.2 V |
| ピン H10 | VCCIO — I/O bank supply voltage |
| ピン H11 | GND — Ground |
| ピン J1 | IO — User I/O (bank-specific voltage) |
| ピン J2 | VCCIO — I/O bank supply voltage |
| ピン J3 | GND — Ground |
| ピン J4 | VCC — Core voltage 1.2 V |
| ピン J5 | ADCIN3 — Analog input channel 3 |
| ピン J6 | ADCIN4 — Analog input channel 4 |
| ピン J7 | ADCIN5 — Analog input channel 5 |
| ピン J8 | ADCIN6 — Analog input channel 6 |
| ピン J9 | VCC — Core voltage 1.2 V |
| ピン J10 | IO — User I/O (bank-specific voltage) |
| ピン J11 | IO — User I/O (bank-specific voltage) |
| ピン K1 | IO — User I/O (bank-specific voltage) |
| ピン K2 | GND — Ground |
| ピン K3 | VCCIO — I/O bank supply voltage |
| ピン K4 | VCC — Core voltage 1.2 V |
| ピン K5 | GND — Ground |
| ピン K6 | ADCIN7 — Analog input channel 7 |
| ピン K7 | ADCIN8 — Analog input channel 8 |
| ピン K8 | GND — Ground |
| ピン K9 | VCC — Core voltage 1.2 V |
| ピン K10 | VCCIO — I/O bank supply voltage |
| ピン K11 | GND — Ground |
| ピン L1 | IO — User I/O (bank-specific voltage) |
| ピン L2 | VCCIO — I/O bank supply voltage |
| ピン L3 | GND — Ground |
| ピン L4 | VCC — Core voltage 1.2 V |
| ピン L5 | ADCIN9 — Analog input channel 9 |
| ピン L6 | ADCIN10 — Analog input channel 10 |
| ピン L7 | ADCIN11 — Analog input channel 11 |
| ピン L8 | ADCIN12 — Analog input channel 12 |
| ピン L9 | VCC — Core voltage 1.2 V |
| ピン L10 | IO — User I/O (bank-specific voltage) |
| ピン L11 | IO — User I/O (bank-specific voltage) |
| ピン M1 | IO — User I/O (bank-specific voltage) |
| ピン M2 | GND — Ground |
| ピン M3 | VCCIO — I/O bank supply voltage |
| ピン M4 | VCC — Core voltage 1.2 V |
| ピン M5 | GND — Ground |
| ピン M6 | VCCIO — I/O bank supply voltage |
| ピン M7 | VCC — Core voltage 1.2 V |
| ピン M8 | GND — Ground |
| ピン M9 | VCC — Core voltage 1.2 V |
| ピン M10 | VCCIO — I/O bank supply voltage |
| ピン M11 | GND — Ground |
| ピン N1 | IO — User I/O (bank-specific voltage) |
| ピン N2 | IO — User I/O (bank-specific voltage) |
| ピン N3 | GND — Ground |
| ピン N4 | VCCIO — I/O bank supply voltage |
| ピン N5 | VCC — Core voltage 1.2 V |
| ピン N6 | GND — Ground |
| ピン N7 | VCC — Core voltage 1.2 V |
| ピン N8 | VCCIO — I/O bank supply voltage |
| ピン N9 | GND — Ground |
| ピン N10 | IO — User I/O (bank-specific voltage) |
| ピン N11 | IO — User I/O (bank-specific voltage) |
主な用途
10M04SCM153I7G の用途: 6 件s: Industrial I/O Expansion & Glue Logic, Motor Control & PWM Generation, Sensor Aggregation in IoT Edge Nodes, Video Bridging & Display Interface, Human-Machine Interface (HMI) Controllers, Protocol Bridging & Industrial Communication.
Industrial I/O Expansion & Glue Logic
The 10M04SCM153I7G is ideal for industrial I/O expansion where a microcontroller lacks sufficient GPIOs, interrupts, or specialized peripherals. With 112 user I/O pins in the 153-ball MBGA and 4,000 LEs, it bridges SPI/I2C to parallel buses, implements custom timing-critical state machines, and aggregates sensors. The integrated 12-bit 1 Msps ADC also digitizes analog inputs (0-2.5 V) alongside digital I/O. Industrial -40C to +100C temperature grade suits factory-floor PLCs, motor drives, and SCADA modules. Use case: an STM32 host connects to the 10M04 over SPI; the FPGA drives 64 isolated digital outputs, four PWM channels, and three analog sensor inputs - all with sub-microsecond deterministic latency unavailable in software loops.
おすすめ
Motor Control & PWM Generation
The 10M04SCM153I7G's 16 DSP blocks (18x18 multipliers) and 2 PLLs make it suitable for field-oriented control (FOC) and high-resolution PWM generation in BLDC, stepper, and PMSM motor drives. The 16 hardware multipliers handle Park/Clark transforms and PID computations at switching frequencies above 100 kHz. Quartus Prime IP libraries provide Nios II soft-core for sequence management. The industrial temperature range tolerates under-hood or chassis-mount environments. Typical deployment: a 3-phase inverter PCB uses the 10M04 for center-aligned PWM (25 ns resolution), encoder quadrature decoding, and overcurrent protection logic, with the host MCU handling CAN and user-interface functions.
おすすめ
Sensor Aggregation in IoT Edge Nodes
The 10M04SCM153I7G aggregates multiple sensor streams (SPI temperature, I2C pressure, UART GPS, analog load cell) into a single Ethernet or CAN output for IoT gateways. Its 193,536 bits of embedded SRAM buffers bursty sensor data, while the integrated 12-bit ADC handles analog sensors without external converters. Industrial temperature rating fits outdoor enclosures. The 153-ball MBGA at 8x8 mm keeps the PCB compact for DIN-rail mounted edge devices. Reference design: a smart-agriculture node reads 12 sensors, performs local thresholding/filtering in FPGA logic, and forwards only events to the cloud via Ethernet, reducing cellular data costs.
おすすめ
Video Bridging & Display Interface
The 10M04SCM153I7G supports parallel RGB, LVDS, and CMOS image sensor interfaces for video bridging applications. With 4,000 LEs and 16 DSP blocks, it implements color-space conversion, scaling, and timing generation at resolutions up to 720p. The 112 I/O pins accommodate 24-bit parallel RGB plus control signals. Industrial temperature range suits automotive aftermarket head-units, industrial HMIs, and medical imaging front-ends. Typical use: bridge a CMOS camera sensor (parallel DVP output) to an RGB TFT LCD with on-the-fly gamma correction and OSD overlay, all handled in FPGA fabric without a dedicated graphics processor.
おすすめ
Human-Machine Interface (HMI) Controllers
The 10M04SCM153I7G drives HMI touchscreens, button matrices, and LED indicators in industrial control panels. With 112 I/O pins, it scans 8x8 key matrices, controls WS2812 addressable LEDs via DMA-style pulse generation, and refreshes TFT displays over SPI. The on-chip ADC reads potentiometers and analog joysticks. Quartus Prime Lite's free license keeps BOM cost low for high-volume HMI products. Industrial temperature grade supports -40C to +100C factory and outdoor cabinet use. Example: a 7-inch HMI panel uses the 10M04 to manage capacitive-touch I2C controller, 32 RGB status LEDs, and a CAN bus interface to a PLC.
おすすめ
Protocol Bridging & Industrial Communication
The 10M04SCM153I7G excels at industrial protocol bridging between UART, SPI, I2C, CAN, RS-485, RS-232, and Ethernet. The 4,000 LEs implement multiple soft protocol stacks simultaneously with deterministic timing. Hard PLLs generate precise baud rates up to 10 Mbit/s. Industrial -40C to +100C temperature range tolerates harsh cabinet environments. The integrated flash enables field firmware updates via JTAG or soft-core bootloader. Example deployment: a substation gateway converts DNP3 over RS-485 to IEC 61850 over Ethernet, with hardware-accelerated CRC and timestamping - reducing latency versus MCU-based bridges by 5-10x.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10M04SCM153I7G — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10M04SAM153I7G | 10M04SCM153C8G | 10M04SAM153C8G | 10M04SCE144I7G |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 153-ball MBGA (M153), 8x8 mm | 153-ball MBGA (M153), 8x8 mm | 153-ball MBGA (M153), 8x8 mm | 153-ball MBGA (M153), 8x8 mm | 144-ball MBGA (E144) |
| Logic Elements | 4,000 | 4,000 | 4,000 | 4,000 | 4,000 |
| Embedded Memory (bits) | 193,536 | 193,536 | 193,536 | 193,536 | 193,536 |
| Maximum User I/O | 112 | 112 | 112 | 112 | ~96 |
| Speed Grade | SC | SA | SC | SA | SC |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Industrial (-40C to +100C) |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| On-chip ADC | 12-bit, 1 Msps | 12-bit, 1 Msps | 12-bit, 1 Msps | 12-bit, 1 Msps | 12-bit, 1 Msps |
主な差別化要因
- Highest-density I/O option within the 10M04 family at 8x8 mm （vs 10M04SCE144I7G)
- Industrial temperature grade for harsh-environment deployment （vs 10M04SCM153C8G)
- Integrated 12-bit 1 Msps ADC with up to 17 analog inputs （vs Lattice ECP5 (LFE5U-12F-8BG256C))
設計ノート
The 10M04SCM153I7G requires three supply rails: 1.2 V core (VCC), per-bank VCCIO (1.2-3.3 V), and 2.5 V VCCA_ADC for the integrated ADC. Decouple each VCC pin with a 100 nF 0402 ceramic capacitor placed within 2 mm of the ball. Use a ferrite bead or pi-filter on VCCA_ADC to isolate ADC noise from digital supplies. Bulk capacitors of 10 uF on each rail are recommended. Power-on sequencing: VCC must rise before or simultaneously with VCCIO; failure causes latch-up.
The 153-ball MBGA package has a theta_JA of approximately 25-30 C/W on a 4-layer JEDEC test board. In industrial temperature operation (-40C to +100C ambient), the FPGA can dissipate up to 1 W continuously without active cooling. For fanless enclosures, ensure the PCB has at least 2 oz copper on inner layers with thermal via arrays beneath the BGA center ground balls. Avoid placing the FPGA adjacent to high-power regulators.
Route all 153 BGA escape traces on the top layer using 0.1 mm trace/space with microvia-in-pad for BGA breakouts. The 0.5 mm pitch requires HDI (high-density interconnect) PCB fabrication - 4-layer stack-up with sequential lamination is typical. Match JTAG trace lengths to TCK to within 25 mm. Provide a USB-Blaster header or pogo-pin test points for factory programming. Keep the JTAG chain free of series resistors per Intel Pin Connection Guidelines.
Do not connect unused I/O pins to ground - leave them floating or per Quartus default (input tri-stated with weak pull-up). Connecting unused balls to GND increases inrush current and may damage the I/O cell during hot-plug events. Also note that the on-chip flash must be programmed via JTAG or AS mode before the FPGA can self-configure at power-on; verify the .pof file generation step in Quartus Programmer before shipping boards.
コンプライアンス情報
RoHS compliant per 7G suffix in MPN. Intel MAX 10 family is not AEC-Q100 qualified - choose Cyclone IV or V for automotive. Halogen-free status not confirmed in available data.
