5M160ZM100C5N - MAX V CPLD 128 Macro Cells 118.3MHz | Intel/Altera
部品番号: 5M160ZM100C5N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.8 | $6.80 |
| 10 | $6.12 | $61.20 |
| 100 | $5.44 | $544.00 |
| 500 | $4.89 | $2,445.00 |
| 1,000 | $4.35 | $4,350.00 |
5M160ZM100C5N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device positioned in the hierarchy below FPGAs and above simple SPLDs/glue-logic ICs. CPLDs are widely used as I/O expansion, bus-interface bridging, power-up sequencers, and configuration controllers because they retain their configuration in flash, boot in microseconds, and offer deterministic timing. The MAX V family is Altera/Intel's smallest, lowest-cost CPLD line, typically selected for replacing dozens of discrete 74-series logic gates.
Key specifications of the 5M160ZM100C5N include 128 macro cells (equivalent to 160 logic elements), 7.9 ns pin-to-pin propagation delay, 184 MHz internal performance, 1.8 V core VCCINT with multi-voltage VCCIO banks supporting 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and LVCMOS/LVTTL I/O standards, plus an internal flash configuration memory with IEEE 1532 in-system programmability via JTAG. The MBGA-100 package provides 79 user I/Os in a compact 6 x 6 mm area.
Architecturally, the MAX V CPLD combines a flash-based non-volatile configuration store with a classic macro-cell fabric of AND/OR arrays and product-term logic, eliminating the external boot PROM required by SRAM-based FPGAs. This makes 5M160ZM100C5N ideal for deterministic, instant-on glue logic in systems where SRAM-FPGA boot time is unacceptable.
Typical applications include I/O expansion and bus bridging for microcontrollers, power-up/power-down sequencing in multi-rail systems, JTAG-controlled configuration of companion FPGAs, address decoding and chip-select generation, and replacement of multiple discrete 74-series TTL/CMOS gates. The 100-ball MBGA package suits space-constrained portable and embedded designs.
When designing with this device, ensure that the VCCIO bank voltages match the driven/receiving logic; mixing 3.3 V peripherals with a 1.8 V bank will damage the I/O. Use the Altera/Intel Quartus II or Quartus Prime toolchain for synthesis, fitting, and JTAG programming.
This page synthesizes distributor pricing from DigiKey/Mouser/LCSC, drop-in alternatives from the MAX V family, and practical Quartus toolchain notes not found in the bare datasheet.
ドロップイン代替品: 5M160ZM100C5N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 5M160ZM100C5N （同一形状・フットプリント） — 相違点: Package, Programming Interface, Configuration Memory, Operating Temperature, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
5M160ZM100C4N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$1.4 / 個
データシートを見る →5M160ZM100A5N
✅ ドロップイン✓ 在庫あり
$5 / 個
データシートを見る →5M160ZE64I5N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$4.13 / 個
データシートを見る →LCMXO2-256ZE-100MG132I
✅ ドロップイン📋 参考代替品（カタログ未掲載）
XA2C128-7VQG100Q
✅ ドロップイン📋 参考代替品（カタログ未掲載）
5M160ZM100C5N 最大定格＆電気的特性
| Device Family | MAX V |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Logic Elements | 160 |
| Maximum Internal Frequency | 184 MHz |
| Propagation Delay (tPD) | 7.9 ns |
| User I/Os | 79 |
| Core Voltage (VCCINT) | 1.8 V |
| I/O Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Configuration Memory | Internal Flash (non-volatile) |
| Programming Interface | JTAG (IEEE 1532 / IEEE 1149.1) |
| パッケージ | 100-ball Micro FBGA (MBGA-100), 6 x 6 mm, 0.5 mm pitch |
| 動作温度 | 0C to +85C (commercial) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| MSLレベル | 3 (168 hours) |
| Supported I/O Standards | LVCMOS, LVTTL, PCI (Bank 1 only via VCCIO) |
5M160ZM100C5N 100-ball micro fbga (mbga-100), 6 x 6 mm, 0.5 mm pitch ピン配置ガイド
5M160ZM100C5N (100-ball micro fbga (mbga-100), 6 x 6 mm, 0.5 mm pitch パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: 5M160ZM100C5N.
詳細は データシート をご参照ください。
主な用途
5M160ZM100C5N の用途: 7 件s: Microcontroller I/O Expansion and Bus Bridging, Multi-Rail Power-Up/Power-Down Sequencing, JTAG-Based Configuration Controller for Companion FPGAs, Address Decoding and Chip-Select Generation, Discrete 74-Series Glue Logic Replacement, Industrial Control Logic and Interface Bridging, Portable Consumer Device Interface Controllers.
Microcontroller I/O Expansion and Bus Bridging
The 5M160ZM100C5N's 79 user I/Os in a 6 x 6 mm MBGA-100 package, combined with 160 logic elements and 1.2-3.3 V VCCIO bank support, make it a high-density bridge between low-pin-count microcontrollers and parallel peripherals. Placed between an MCU with limited GPIO and a 16-bit LCD, SRAM, or SD card interface, the CPLD decodes addresses and generates chip-select signals with 7.9 ns propagation delay - far faster than software bit-banging. Unlike microcontrollers, the CPLD boots instantly from internal flash with deterministic timing, so peripherals are ready at power-on without firmware intervention.
おすすめ
Multi-Rail Power-Up/Power-Down Sequencing
The 5M160ZM100C5N is widely used as a deterministic power-sequencer in systems with 3-8 voltage rails that must come up in a strict order to prevent latch-up. Its internal flash configuration boots in microseconds - before any MCU firmware runs - allowing the CPLD to assert enable signals to DC-DC converters with 7.9 ns deterministic delay between stages. The 1.8 V core draws minimal quiescent current, and the multi-voltage VCCIO banks drive 3.3 V and 5 V enable inputs directly. Compared to discrete RC delay chains, the CPLD approach is reprogrammable and field-updatable.
おすすめ
JTAG-Based Configuration Controller for Companion FPGAs
In systems pairing a MAX V CPLD with an SRAM-based FPGA (such as Cyclone IV/V or MAX 10), the 5M160ZM100C5N can serve as the configuration master, loading the FPGA's bitstream from SPI flash and driving the FPGA's nCONFIG, nSTATUS, and CONFIG_DONE pins. The CPLD's IEEE 1532 JTAG interface simplifies board-level test access, and the 79 user I/Os provide ample headroom for status LEDs, mode selects, and configuration handshake signals. This configuration-controller role eliminates the need for an external configuration PROM in low-cost FPGA designs.
おすすめ
Address Decoding and Chip-Select Generation
The 5M160ZM100C5N's 160 logic elements and 7.9 ns propagation delay make it ideal for high-speed address decoding in memory subsystems where multiple peripherals share a parallel bus. Place the CPLD between the system bus and memory/peripheral chip-select lines; with 79 user I/Os it can decode up to a 24-bit address space and generate 8-12 independent chip-select outputs. Unlike discrete 74-series decoders, the CPLD allows any address map to be programmed via Quartus without rewiring.
おすすめ
Discrete 74-Series Glue Logic Replacement
A single 5M160ZM100C5N can replace 20-40 discrete 74HC/74AHC logic gates (AND, OR, NAND, flip-flops, multiplexers, latches), shrinking BOM cost and PCB area. With 79 user I/Os in a 6 x 6 mm MBGA-100 package, the CPLD fits where a board would otherwise carry a dozen SOT-23 or SOIC gates. The internal flash allows late-stage design changes via JTAG without board rework, and the 1.8 V core with multi-voltage VCCIO banks allows the CPLD to interface seamlessly with legacy 5 V and modern 1.8 V logic.
おすすめ
Industrial Control Logic and Interface Bridging
In industrial PLCs, motor controllers, and factory-automation I/O modules, the 5M160ZM100C5N bridges RS-485, RS-232, SPI, I2C, and parallel industrial buses while providing debouncing, edge detection, and protocol conversion. Its commercial 0-85C temperature range covers most indoor industrial enclosures, and the 100-ball MBGA package withstands typical factory vibration profiles when properly PCB-mounted. The 79 user I/Os allow direct connection to multiple optically-isolated industrial I/O channels.
おすすめ
Portable Consumer Device Interface Controllers
The compact 6 x 6 mm MBGA-100 footprint and 1.8 V core voltage make the 5M160ZM100C5N suitable for handheld consumer devices where PCB real estate is at a premium. It handles display timing generation for small LCDs, keypad scanning, LED matrix driving, and battery-management handshaking - tasks that would otherwise burden the main application processor. The instant-on flash-based configuration means the CPLD is ready before the application CPU completes its boot sequence, enabling fast user-perceived power-on times.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 5M160ZM100C5N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 5M160ZM100C4N | 5M160ZM100A5N | 5M160ZE64I5N | LCMXO2-256ZE-100MG132I | XA2C128-7VQG100Q |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Lattice Semiconductor | Xilinx |
| Package | MBGA-100 (100-ball Micro FBGA) | MBGA-100 (100-ball Micro FBGA) - same | MBGA-100 (100-ball Micro FBGA) - same | MBGA-100 (100-ball Micro FBGA) - same | 132-ball BGA (near-compatible BGA footprint class) | VQ100 (100-pin VQFP) - different outline |
| Macro Cells | 128 | 128 | 128 | 64 (50% reduction) | 256 LUTs (higher) | 128 |
| Max Internal Frequency | 184 MHz (C5 speed grade) | 152 MHz (C4 speed grade) | 184 MHz (C5 speed grade) | 184 MHz (C5 speed grade) | 200+ MHz (MachXO2) | 200+ MHz (CoolRunner-II) |
| User I/Os | 79 | 79 | 79 | 52 (smaller package density) | 55 (132-ball BGA) | 80 (VQ100) |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.2 V (lower) | 1.8 V |
| Configuration Memory | Internal Flash (non-volatile) | Internal Flash | Internal Flash | Internal Flash | Internal Flash (NVCM) | Internal Flash |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +125C (automotive) | -40C to +100C (industrial) | -40C to +100C (industrial) | -40C to +125C (Q-grade) |
| Approx. 1-piece Price | $6.80 USD | ~$5.95 USD | ~$8.20 USD | ~$5.40 USD | ~$7.50 USD | ~$9.00 USD |
主な差別化要因
- Largest user I/O count in 100-ball MAX V CPLD family （vs 5M160ZE64I5N)
- Highest speed grade (C5) in 160-LE MAX V CPLD family （vs 5M160ZM100C4N)
- Cross-brand drop-in path to higher LUT density （vs LCMXO2-256ZE-100MG132I)
設計ノート
The 5M160ZM100C5N operates from a single 1.8 V VCCINT supply plus one or more VCCIO bank supplies (1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V). All VCCINT and VCCIO pins must be connected; unused VCCIO banks can be tied to 1.8 V to minimize I/O leakage. Estimated core current at 184 MHz is ~25 mA for a fully-utilized design, so a 100 mA LDO is sufficient. Add 100 nF decoupling on each VCC pin placed within 5 mm of the ball.
The MBGA-100 package has 0.5 mm pitch balls on a 6 x 6 mm footprint, requiring 4-layer PCB with microvia-in-pad or via-in-pad construction for reliable assembly. Apply the manufacturer's recommended land pattern with non-solder-mask-defined (NSMD) pads and a solder mask dam between balls. Match the impedance of JTAG and clock traces to 50 ohms if longer than 25 mm, and keep JTAG signals away from switching power rails to avoid programming interference.
Do not mix VCCIO bank voltages above 3.3 V - the 5M160Z family I/Os are not 5 V tolerant unless explicitly documented for that bank. Do not leave VCCIO floating; floating bank supplies can cause unpredictable I/O behavior and inrush during power-up. When migrating from 5M160Z (1.8 V core) to MAX 10 or Cyclone FPGAs, do not assume JTAG pinout compatibility - verify with Quartus pin planner.
For high-speed outputs above 100 MHz, use the Quartus Slow Slew Rate and Current Strength settings to control edge rates and ground bounce. Series-terminate clock outputs with 22-33 ohm resistors if driving long traces (>50 mm) on the same layer. The 79 user I/Os are split across multiple banks; co-locate timing-critical signals within the same bank to minimize bank-to-bank skew.
コンプライアンス情報
RoHS compliant per Altera/Intel MAX V family product page. Commercial 0-85C temperature grade; choose 5M160ZM100A5N for AEC-Q100 automotive temperature range.
