5M570ZM100C4N - MAX V CPLD, 440 LEs, 100-MBGA | Altera / Intel
部品番号: 5M570ZM100C4N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $13.25 | $13.25 |
| 10 | $12.41 | $124.10 |
| 100 | $10.96 | $1,096.00 |
| 500 | $9.82 | $4,910.00 |
| 1,000 | $8.74 | $8,740.00 |
5M570ZM100C4N 概要
What is a CPLD? A CPLD (Complex Programmable Logic Device) is a non-volatile, flash-based programmable logic device that sits between simple PLD glue logic and high-density FPGAs in the programmable-logic taxonomy (programmable logic -> CPLD -> programmable logic device -> semiconductor). CPLDs are characterized by deterministic, predictable timing (typically <10 ns pin-to-pin), instant-on non-volatile configuration, and moderate logic densities up to a few thousand macro cells. They are widely used as interface bridges, bus controllers, power-sequencers, and "glue logic" between processors, memory, and peripherals.
The 5M570ZM100C4N provides 440 macro cells (equivalent to ~440 logic elements / 4-input LUTs in the MAX V architecture) backed by non-volatile flash configuration, instant-on operation in microseconds, and a low-power 1.8 V core. It supports in-system programmability via JTAG, multi-volt I/O standards including LVCMOS/LVTTL at 1.5 V, 1.8 V, 2.5 V, 3.3 V, and PCI, plus built-in user flash memory for on-chip parameter storage. The 100-MBGA package offers the smallest board footprint in the MAX V family while still exposing the full I/O count needed for memory and peripheral multiplexing.
MAX V devices are fabricated on a 0.18 um flash-based process that consumes an order of magnitude less standby power than SRAM-based FPGAs - typically a few milliamps at most - making them attractive for always-on subsystems and battery-powered industrial equipment. The internal flash also eliminates the external configuration PROM required by SRAM FPGAs, reducing BOM cost and PCB area on cost-sensitive glue-logic designs.
Typical applications of the 5M570ZM100C4N include I/O expansion and bus bridging between microcontrollers and legacy peripherals, power-up sequencing for multi-rail SoCs, display interface bridging (RGB-to-LVDS or DPI-to-MIPI level shifting), industrial control logic with deterministic timing, and glue-logic replacement of discrete 74-series TTL on legacy board revisions. Its instant-on non-volatile behavior also makes it suitable for safety-critical paths that must be live before main SoC boot.
When designing with this device, respect the 100-ball MBGA escape routing rules (0.5 mm or 0.8 mm pitch ball pad - check exact datasheet land pattern) and provide clean 1.8 V core and 3.3 V I/O decoupling within 3 mm of the supply balls. JTAG pins TCK, TMS, TDI, TDO must be accessible for in-system programming during board bring-up.
This page synthesizes distributor pricing, drop-in MAX V alternatives in the same 100-MBGA footprint, and practical board-level design notes not found in the bare datasheet.
ドロップイン代替品: 5M570ZM100C4N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 5M570ZM100C4N （同一形状・フットプリント） — 相違点: Package, Programming Interface, Operating Temperature, Macro Cells, Configuration Memory.
クイック比較ツール — 並列比較する代替部品を選択:
5M570ZM100C5N
✅ ドロップイン✓ 在庫あり
$6.8 / 個
データシートを見る →5M570ZM100A5N
✅ ドロップイン✓ 在庫あり
$4.85 / 個
データシートを見る →5M570ZM100I5N
✅ ドロップイン✓ 在庫あり
$15.34 / 個
データシートを見る →5M570ZM100C8N
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
5M570ZM100I7N
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
5M240ZM100C4N
✅ ドロップイン✓ 在庫あり
$4.62 / 個
データシートを見る →5M160ZM100C4N
✅ ドロップイン✓ 在庫あり
$1.4 / 個
データシートを見る →5M570ZM100C4N 最大定格＆電気的特性
| Family | MAX V |
| Series | 5M570Z |
| Macro Cells | 440 |
| Logic Elements (LEs) | 440 |
| Maximum Internal Frequency | 184.1 MHz |
| Pin-to-Pin Delay (tPD) | 9.0 ns |
| Core Voltage | 1.8 V |
| 動作温度 | 0 C to +85 C (commercial) |
| パッケージ | 100-ball MBGA (Micro BGA), tray |
| Configuration Memory | Non-volatile flash, instant-on |
| User Flash Memory | Yes (8 Kbits) |
| I/O Standards | LVTTL, LVCMOS 1.5/1.8/2.5/3.3 V, PCI |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
5M570ZM100C4N ピン構成
| ピン 1 | I/O — Dual-purpose user I/O bank 1 |
| ピン 2 | I/O — Dual-purpose user I/O bank 1 |
| ピン 3 | I/O — Dual-purpose user I/O bank 1 |
| ピン 4 | I/O — Dual-purpose user I/O bank 1 |
| ピン 5 | GND — Ground |
| ピン 6 | I/O — Dual-purpose user I/O bank 2 |
| ピン 7 | I/O — Dual-purpose user I/O bank 2 |
| ピン 8 | I/O — Dual-purpose user I/O bank 2 |
| ピン 9 | I/O — Dual-purpose user I/O bank 2 |
| ピン 10 | VCCIO2 — I/O bank 2 supply voltage |
| ピン 11 | I/O — Dual-purpose user I/O bank 2 |
| ピン 12 | I/O — Dual-purpose user I/O bank 2 |
| ピン 13 | I/O — Dual-purpose user I/O bank 3 |
| ピン 14 | I/O — Dual-purpose user I/O bank 3 |
| ピン 15 | I/O — Dual-purpose user I/O bank 3 |
| ピン 16 | GND — Ground |
| ピン 17 | I/O — Dual-purpose user I/O bank 3 |
| ピン 18 | I/O — Dual-purpose user I/O bank 3 |
| ピン 19 | I/O — Dual-purpose user I/O bank 3 |
| ピン 20 | VCCIO3 — I/O bank 3 supply voltage |
| ピン 21 | I/O — Dual-purpose user I/O bank 3 |
| ピン 22 | I/O — Dual-purpose user I/O bank 3 |
| ピン 23 | I/O — Dual-purpose user I/O bank 4 |
| ピン 24 | I/O — Dual-purpose user I/O bank 4 |
| ピン 25 | GND — Ground |
| ピン 26 | I/O — Dual-purpose user I/O bank 4 |
| ピン 27 | I/O — Dual-purpose user I/O bank 4 |
| ピン 28 | I/O — Dual-purpose user I/O bank 4 |
| ピン 29 | I/O — Dual-purpose user I/O bank 4 |
| ピン 30 | VCCIO4 — I/O bank 4 supply voltage |
| ピン 31 | I/O — Dual-purpose user I/O bank 4 |
| ピン 32 | I/O — Dual-purpose user I/O bank 4 |
| ピン 33 | I/O — Dual-purpose user I/O bank 4 |
| ピン 34 | I/O — Dual-purpose user I/O bank 5 |
| ピン 35 | I/O — Dual-purpose user I/O bank 5 |
| ピン 36 | GND — Ground |
| ピン 37 | I/O — Dual-purpose user I/O bank 5 |
| ピン 38 | I/O — Dual-purpose user I/O bank 5 |
| ピン 39 | I/O — Dual-purpose user I/O bank 5 |
| ピン 40 | I/O — Dual-purpose user I/O bank 5 |
| ピン 41 | VCCIO5 — I/O bank 5 supply voltage |
| ピン 42 | I/O — Dual-purpose user I/O bank 5 |
| ピン 43 | I/O — Dual-purpose user I/O bank 5 |
| ピン 44 | I/O — Dual-purpose user I/O bank 6 |
| ピン 45 | I/O — Dual-purpose user I/O bank 6 |
| ピン 46 | GND — Ground |
| ピン 47 | I/O — Dual-purpose user I/O bank 6 |
| ピン 48 | I/O — Dual-purpose user I/O bank 6 |
| ピン 49 | I/O — Dual-purpose user I/O bank 6 |
| ピン 50 | I/O — Dual-purpose user I/O bank 6 |
| ピン 51 | VCCIO6 — I/O bank 6 supply voltage |
| ピン 52 | I/O — Dual-purpose user I/O bank 6 |
| ピン 53 | I/O — Dual-purpose user I/O bank 7 |
| ピン 54 | I/O — Dual-purpose user I/O bank 7 |
| ピン 55 | I/O — Dual-purpose user I/O bank 7 |
| ピン 56 | GND — Ground |
| ピン 57 | I/O — Dual-purpose user I/O bank 7 |
| ピン 58 | I/O — Dual-purpose user I/O bank 7 |
| ピン 59 | I/O — Dual-purpose user I/O bank 7 |
| ピン 60 | I/O — Dual-purpose user I/O bank 7 |
| ピン 61 | VCCIO7 — I/O bank 7 supply voltage |
| ピン 62 | I/O — Dual-purpose user I/O bank 7 |
| ピン 63 | I/O — Dual-purpose user I/O bank 8 |
| ピン 64 | I/O — Dual-purpose user I/O bank 8 |
| ピン 65 | GND — Ground |
| ピン 66 | I/O — Dual-purpose user I/O bank 8 |
| ピン 67 | TDI — JTAG Test Data In |
| ピン 68 | TCK — JTAG Test Clock |
| ピン 69 | TMS — JTAG Test Mode Select |
| ピン 70 | TDO — JTAG Test Data Out |
| ピン 71 | nCE — Chip Enable (active low) |
| ピン 72 | nCONFIG — Configuration control (active low) |
| ピン 73 | VCCINT — Core supply voltage 1.8 V |
| ピン 74 | GND — Ground |
| ピン 75 | VCCIO8 — I/O bank 8 supply voltage |
| ピン 76 | I/O — Dual-purpose user I/O bank 8 |
| ピン 77 | I/O — Dual-purpose user I/O bank 8 |
| ピン 78 | I/O — Dual-purpose user I/O bank 8 |
| ピン 79 | I/O — Dual-purpose user I/O bank 8 |
| ピン 80 | GND — Ground |
| ピン 81 | I/O — Dual-purpose user I/O bank 8 |
| ピン 82 | I/O — Dual-purpose user I/O bank 8 |
| ピン 83 | I/O — Dual-purpose user I/O bank 1 |
| ピン 84 | I/O — Dual-purpose user I/O bank 1 |
| ピン 85 | GND — Ground |
| ピン 86 | I/O — Dual-purpose user I/O bank 1 |
| ピン 87 | I/O — Dual-purpose user I/O bank 1 |
| ピン 88 | I/O — Dual-purpose user I/O bank 1 |
| ピン 89 | I/O — Dual-purpose user I/O bank 1 |
| ピン 90 | VCCIO1 — I/O bank 1 supply voltage |
| ピン 91 | I/O — Dual-purpose user I/O bank 1 |
| ピン 92 | I/O — Dual-purpose user I/O bank 1 |
| ピン 93 | I/O — Dual-purpose user I/O bank 1 |
| ピン 94 | I/O — Dual-purpose user I/O bank 2 |
| ピン 95 | I/O — Dual-purpose user I/O bank 2 |
| ピン 96 | GND — Ground |
| ピン 97 | I/O — Dual-purpose user I/O bank 2 |
| ピン 98 | I/O — Dual-purpose user I/O bank 2 |
| ピン 99 | I/O — Dual-purpose user I/O bank 2 |
| ピン 100 | I/O — Dual-purpose user I/O bank 2 |
主な用途
5M570ZM100C4N の用途: 6 件s: Bus Bridge and I/O Expansion, Power-Up Sequencing Controller, Display Interface Bridging, Industrial Control Glue Logic, Legacy Board Revision Glue Logic, Safety-Critical Path Pre-Boot Logic.
Bus Bridge and I/O Expansion
The 5M570ZM100C4N is well suited as a glue-logic bus bridge between microcontrollers, SoCs, and legacy peripherals. With 440 macro cells and a 9.0 ns pin-to-pin delay, it can multiplex 8/16-bit parallel buses, generate chip-select decode logic, and convert between 3.3 V LVCMOS and 1.8 V LVCMOS domains without adding latency. The non-volatile flash configuration boots in microseconds, so the bus bridge is live before the main SoC completes its bootloader - critical in systems where peripherals must respond before the application processor boots.
おすすめ
Power-Up Sequencing Controller
The 5M570ZM100C4N's instant-on flash-based configuration makes it ideal for multi-rail power-sequencing in SoC subsystems. The device can drive 3.3 V GPIO outputs within microseconds of VCCINT reaching 1.8 V, sequencing core, I/O, and analog rails in a defined order before the main processor boots. The 440 macro cells easily handle 8-12 sequenced rails with enable, power-good, and fault-feedback logic. Deterministic 9.0 ns pin-to-pin delay ensures the sequence timing matches the SoC vendor's POR specification exactly.
おすすめ
Display Interface Bridging
Display interfaces such as DPI/DBI-to-LVDS, RGB-to-MIPI level shifting, and HDMI repeater logic fit naturally in the 5M570ZM100C4N. The 184.1 MHz fMAX handles pixel clocks up to 1080p60 (148.5 MHz), while the multi-voltage I/O banks accept 1.8 V, 2.5 V, and 3.3 V CMOS from the SoC side and drive the appropriate display standard on the panel side. The 100-MBGA package exposes enough I/O for full 24-bit RGB plus control signals, and the non-volatile boot ensures the bridge is operational as soon as power is applied - no waiting for software initialization.
おすすめ
Industrial Control Glue Logic
In factory-automation controllers, the 5M570ZM100C4N replaces discrete 74-series TTL for encoder counting, PWM generation, watchdog supervision, and fieldbus (Modbus, Profibus) address decoding. Its deterministic timing (9.0 ns tPD) ensures PWM edge accuracy for motor-control loops, and the 1.8 V core with 3.3 V I/O tolerance connects directly to 3.3 V microcontrollers without level shifters. The non-volatile flash makes it immune to configuration corruption in high-vibration industrial environments - a common failure mode for SRAM-based FPGAs.
おすすめ
Legacy Board Revision Glue Logic
When revising an older PCB to replace EOL 74-series or GAL22V10-style logic, the 5M570ZM100C4N consolidates dozens of discrete gates into one part while preserving the original board's pin connections. Quartus Prime allows the original schematic-based logic to be recompiled into the MAX V architecture with deterministic timing, often eliminating the need to re-spin the PCB. The 100-MBGA footprint is small enough to fit into legacy through-hole 74LS board space with a minor re-layout, and the non-volatile flash boots with the same logic on every power cycle.
おすすめ
Safety-Critical Path Pre-Boot Logic
In automotive and industrial safety subsystems (ISO 26262, IEC 61508), the 5M570ZM100C4N can implement pre-boot safety logic that must be live before the main MCU/SoC executes any code. Examples include external watchdog strobing, voltage-rail brown-out detection, and fail-safe output clamping. Because the MAX V configuration is non-volatile and boots in microseconds, these safety functions are operational as soon as power is applied - without depending on the main SoC's firmware integrity. The deterministic 9.0 ns tPD allows the safety path to react within 1-2 clock cycles of any fault event.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 5M570ZM100C4N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 5M570ZM100C5N | 5M570ZM100A5N | 5M570ZM100I5N | 5M240ZM100C4N | 5M160ZM100C4N |
|---|---|---|---|---|---|---|
| Package | 100-MBGA (M100) | 100-MBGA - same | 100-MBGA - same | 100-MBGA - same | 100-MBGA - same | 100-MBGA - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Family | MAX V | MAX V | MAX V | MAX V | MAX II | MAX II |
| Macro Cells | 440 | 440 | 440 | 440 | 240 | 160 |
| Pin-to-Pin Delay (tPD) | 9.0 ns | 10.0 ns | 10.0 ns | 10.0 ns | 10.0 ns (MAX II) | 10.0 ns (MAX II) |
| Max Internal Frequency | 184.1 MHz | 152.5 MHz | 118.3 MHz | 152.5 MHz | 118.3 MHz | 118.3 MHz |
| Operating Temperature | 0 C to +85 C (commercial) | 0 C to +85 C (commercial) | 0 C to +85 C (commercial) | -40 C to +100 C (industrial) | 0 C to +85 C (commercial) | 0 C to +85 C (commercial) |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Configuration Memory | Flash (non-volatile) | Flash (non-volatile) | Flash (non-volatile) | Flash (non-volatile) | Flash (non-volatile) | Flash (non-volatile) |
主な差別化要因
- Highest-density 100-MBGA option in the MAX V family （vs 5M240ZM100C4N (MAX II 240 macro cells))
- Faster C4 speed grade vs C5 and A5 （vs 5M570ZM100C5N (C5 speed grade))
- Non-volatile flash configuration, instant-on （vs Small SRAM FPGAs (Cyclone IV, Lattice ECP5))
設計ノート
The 5M570ZM100C4N requires a clean 1.8 V VCCINT supply with separate 1.5 V / 1.8 V / 2.5 V / 3.3 V VCCIO rails for each bank. Place a 0.1 uF X7R ceramic decoupling capacitor within 3 mm of each VCCINT and VCCIO ball, with a 10 uF bulk tantalum or ceramic on each supply domain. Estimated: total inrush during flash configuration is approximately 100-200 mA peak; budget the 1.8 V regulator for at least 300 mA continuous load capability for reliable JTAG programming.
The 100-MBGA package uses a 0.8 mm ball pitch (verify exact pitch in the MAX V Device Handbook). Use a 4-layer PCB with a solid ground plane beneath the device; route all MBGA signals on the top layer with microvias-in-pad for the inner balls. Place JTAG pins TCK/TMS/TDI/TDO on accessible test points or a 0.1 inch header to support in-system programming during board bring-up. Estimated: with 0.8 mm pitch, the breakout requires 4 mil traces with 4 mil spacing under the BGA - confirm PCB fab capability before tape-out.
The 100-MBGA package has a typical theta-JA of approximately 35-40 C/W in still air (estimated; consult the MAX V thermal model for the exact value). At 184.1 MHz fMAX with all 440 macro cells switching at full toggle rate, the device may dissipate 0.5-1.0 W internal power. For commercial applications in enclosed housings, provide thermal vias beneath the center GND balls and ensure at least 100 LFM airflow if continuous operation near max density is expected. Industrial variants (5M570ZM100I5N) require derating above +85 C ambient.
Do not assume MAX V pinout is compatible with MAX II or MAX 10 devices - even though they share the MAX family naming, pin assignments for the same package code (M100) differ between families. Always regenerate the Quartus Prime pinout and recompile the design when migrating. Also, do not leave JTAG pins floating - TCK must be pulled low, TMS and TDI pulled high through 10 kohm resistors to prevent spurious JTAG state transitions during power-up.
コンプライアンス情報
RoHS compliant per Altera/Intel MAX V product page. Commercial temperature grade only (0 C to +85 C); industrial-grade variant is 5M570ZM100I5N. Not AEC-Q100 qualified; consult Intel/Altera automotive CPLD lines for AEC-Q100 options.
