ADC1012D065HN/C1 - 10-bit 65Msps Dual ADC | NXP | 64-HVQFN
部品番号: ADC1012D065HN/C1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $31.8 | $3,180.00 |
| 500 | $28.4 | $14,200.00 |
| 1,000 | $25.1 | $25,100.00 |
| 3,000 | $22.3 | $66,900.00 |
ADC1012D065HN/C1 概要
An Analog-to-Digital Converter (ADC) is a data acquisition mixed-signal IC that samples continuous analog voltages and converts them into discrete digital codes for downstream processing. Dual ADCs like the ADC1012D065HN/C1 specifically capture two synchronized channels at full sample rate per channel, which is essential when phase or timing relationships between signals must be preserved - for example, in I/Q demodulation, three-phase power monitoring, or diversity radio receivers. In the broader taxonomy, the ADC1012D065HN/C1 sits under Data Acquisition ICs -> ADC -> High-Speed Pipeline ADC -> Mixed-Signal IC -> Semiconductor.
Key performance specifications include 10-bit resolution, 65 Msps per-channel sample rate, low-latency LVDS digital outputs, internal reference option, and a 1.8V analog supply. The device supports both CMOS and LVDS output modes, with SPI for configuration of channel gain, offset calibration, and data format. Multi-device synchronization enables channel-count expansion beyond two for phased-array and MIMO use cases.
The converter employs a pipelined architecture with per-stage error correction to achieve 10-bit linearity (DNL/INL) and high spurious-free dynamic range (SFDR) at high input frequencies. The exposed thermal pad and 9x9 mm body enable operation across industrial temperature ranges while keeping junction rise manageable in densely populated PCB designs.
Typical applications include cellular base-station receive paths, test and measurement digitizers, medical ultrasound front-ends, and multi-axis industrial control loops. The dual-channel configuration halves PCB area versus two discrete single-channel ADCs and preserves the analog front-end matching required for accurate differential or I/Q acquisition.
When designing in this part, pay close attention to analog input common-mode biasing and decoupling of the AVDD rail; the reference decoupling network must be placed within a few millimetres of the REF pins to avoid SFDR degradation at full sample rate.
ドロップイン代替品: ADC1012D065HN/C1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC1012D065HN/C1 （同一形状・フットプリント） — 相違点: Package, RoHS Status, Number of Channels, Resolution, Digital Output.
クイック比較ツール — 並列比較する代替部品を選択:
ADC1012D065HN/C1:5
✅ ドロップイン✓ 在庫あり
$17.8 / 個
データシートを見る →ADC1010S105HN/C1:5
✅ ドロップイン✓ 在庫あり
$9.62 / 個
データシートを見る →ADC1010S080HN/C1:5
✅ ドロップイン✓ 在庫あり
$7.32 / 個
データシートを見る →ADC1012D065HN/C1 最大定格＆電気的特性
| 分解能 | 10 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate (per channel) | 65 Msps |
| Data Interface | Serial, SPI |
| Digital Output | LVDS/CMOS selectable |
| Analog Supply Voltage | 1.8 V |
| Reference Type | Internal or external |
| パッケージ | 64-VFQFN Exposed Pad (HVQFN 9x9) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
ADC1012D065HN/C1 ピン構成
| ピン 1 | AINP_A — Channel A positive analog input |
| ピン 2 | AINN_A — Channel A negative analog input |
| ピン 3 | VCM_A — Channel A common-mode voltage output |
| ピン 4 | NC — Not connected |
| ピン 5 | AVDD — Analog supply voltage |
| ピン 6 | AVDD — Analog supply voltage |
| ピン 7 | AGND — Analog ground |
| ピン 8 | AGND — Analog ground |
| ピン 9 | REF_TOP — Top reference voltage - external decoupling |
| ピン 10 | REF_BOT — Bottom reference voltage - external decoupling |
| ピン 11 | REFT_A — Channel A reference top |
| ピン 12 | REFB_A — Channel A reference bottom |
| ピン 13 | REFT_B — Channel B reference top |
| ピン 14 | REFB_B — Channel B reference bottom |
| ピン 15 | AINP_B — Channel B positive analog input |
| ピン 16 | AINN_B — Channel B negative analog input |
| ピン 17 | VCM_B — Channel B common-mode voltage output |
| ピン 18 | NC — Not connected |
| ピン 19 | AVDD — Analog supply voltage |
| ピン 20 | AVDD — Analog supply voltage |
| ピン 21 | AGND — Analog ground |
| ピン 22 | AGND — Analog ground |
| ピン 23 | NC — Not connected |
| ピン 24 | NC — Not connected |
| ピン 25 | NC — Not connected |
| ピン 26 | NC — Not connected |
| ピン 27 | NC — Not connected |
| ピン 28 | NC — Not connected |
| ピン 29 | NC — Not connected |
| ピン 30 | NC — Not connected |
| ピン 31 | NC — Not connected |
| ピン 32 | NC — Not connected |
| ピン 33 | DVDD — Digital supply voltage |
| ピン 34 | DVDD — Digital supply voltage |
| ピン 35 | DGND — Digital ground |
| ピン 36 | DGND — Digital ground |
| ピン 37 | NC — Not connected |
| ピン 38 | NC — Not connected |
| ピン 39 | NC — Not connected |
| ピン 40 | NC — Not connected |
| ピン 41 | CLK_A — Channel A clock input |
| ピン 42 | CLK_B — Channel B clock input |
| ピン 43 | NC — Not connected |
| ピン 44 | NC — Not connected |
| ピン 45 | DCLK — Digital output clock |
| ピン 46 | DRDY_A — Channel A data ready output |
| ピン 47 | D_OUT_A[0] — Channel A digital data output bit 0 (LSB) |
| ピン 48 | D_OUT_A[1] — Channel A digital data output bit 1 |
| ピン 49 | D_OUT_A[2] — Channel A digital data output bit 2 |
| ピン 50 | D_OUT_A[3] — Channel A digital data output bit 3 |
| ピン 51 | D_OUT_A[4] — Channel A digital data output bit 4 |
| ピン 52 | D_OUT_A[5] — Channel A digital data output bit 5 |
| ピン 53 | D_OUT_A[6] — Channel A digital data output bit 6 |
| ピン 54 | D_OUT_A[7] — Channel A digital data output bit 7 |
| ピン 55 | D_OUT_A[8] — Channel A digital data output bit 8 |
| ピン 56 | D_OUT_A[9] — Channel A digital data output bit 9 (MSB) |
| ピン 57 | DRDY_B — Channel B data ready output |
| ピン 58 | D_OUT_B[0] — Channel B digital data output bit 0 (LSB) |
| ピン 59 | D_OUT_B[1] — Channel B digital data output bit 1 |
| ピン 60 | D_OUT_B[2] — Channel B digital data output bit 2 |
| ピン 61 | D_OUT_B[3] — Channel B digital data output bit 3 |
| ピン 62 | D_OUT_B[4] — Channel B digital data output bit 4 |
| ピン 63 | D_OUT_B[5..9] — Channel B digital data output bits 5 through 9 |
| ピン 64 | CSN — SPI chip-select (active low) |
| ピン EP | EPAD — Exposed thermal pad - must be soldered to analog ground |
主な用途
ADC1012D065HN/C1 の用途: 6 件s: Cellular Base-Station Receiver IF Sampling, Software-Defined Radio I/Q Digitizer, Test and Measurement Digitizer Front-End, Medical Ultrasound Receive Path, Three-Phase Power Quality Analyzer, Multi-Axis Vibration and Motion Sensing.
Cellular Base-Station Receiver IF Sampling
The ADC1012D065HN/C1 fits base-station IF chains because its 65 Msps per-channel rate lets designers place the digitizer close to the antenna output, simplifying analog filtering. The dual-channel configuration simultaneously captures I and Q streams, preserving orthogonal signal integrity for demodulation downstream. With LVDS digital outputs, the part drives FPGAs used for digital down-conversion while the SPI control bus allows per-channel gain and offset trim, critical for receiver calibration across temperature.
おすすめ
Software-Defined Radio I/Q Digitizer
The ADC1012D065HN/C1 is well matched to software-defined radio (SDR) boards performing direct-conversion or low-IF reception. Two synchronized 65 Msps channels capture the I and Q analog outputs of a quadrature demodulator without timing skew, a fault that destroys EVM in narrow-band waveforms. The HVQFN-64 exposed-pad package offers the thermal margin required for continuous streaming at full sample rate in compact SDR enclosures, while the CMOS output mode reduces FPGA pin count in low-power handheld designs.
おすすめ
Test and Measurement Digitizer Front-End
In benchtop oscilloscopes and modular digitizers, the ADC1012D065HN/C1 serves as a wideband front-end for two-channel simultaneous acquisition at 65 Msps. The 10-bit resolution suits general-purpose lab measurements, while the SPI-configurable input ranges allow the same hardware to handle sensor outputs, audio-band signals, and intermediate-frequency test points. Pairing it with a high-linearity ADC driver maximises SFDR at the Nyquist edge, enabling accurate harmonic and distortion measurements.
おすすめ
Medical Ultrasound Receive Path
Cartridge-style ultrasound probes with 16-64 elements require a high-channel-count ADC array; the ADC1012D065HN/C1's dual-channel integration lets a 32-element probe fit into a compact PCB. Sampling both transmit and receive echoes at 65 Msps captures the full Doppler bandwidth needed for blood-flow imaging, and the HVQFN-64 footprint keeps channel pitch small enough to place ADCs directly behind the transducer stack. The exposed pad aids thermal management during continuous-scan clinical exams.
おすすめ
Three-Phase Power Quality Analyzer
Three-phase industrial power monitors capture simultaneous voltage and current on each phase to compute real power, harmonics, and flicker. Two ADC1012D065HN/C1 ICs deliver four synchronized channels at 65 Msps-enough to oversample mains waveforms well past the 50th harmonic for class-A power-quality instruments. The LVDS/CMOS dual data path interfaces directly to DSPs that perform the FFT-based harmonic analysis, while the small 9x9 mm HVQFN package supports slim form-factor DIN-rail analyzers.
おすすめ
Multi-Axis Vibration and Motion Sensing
Industrial condition-monitoring systems stream vibration data from multiple accelerometers into a synchronized ADC array. The ADC1012D065HN/C1 handles two axes at 65 Msps, allowing bearing-fault analysis up to ~30 kHz with the dual-channel architecture reducing PCB area per axis. The exposed thermal pad supports continuous-monitoring installations that run 24/7, while SPI-programmable input ranges adapt to varied accelerometer sensitivities (5 g to 50 g) without external signal conditioning.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC1012D065HN/C1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC1012D065HN/C1:5 | ADC1010S105HN/C1:5 | ADC1010S080HN/C1:5 | ADC1002S020HL/C1:1 |
|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 64-VFQFN Exposed Pad (HVQFN 9x9) | 64-VFQFN Exposed Pad (HVQFN 9x9) - same | 64-VFQFN Exposed Pad (HVQFN 9x9) - same | 64-VFQFN Exposed Pad (HVQFN 9x9) - same | 44-LQFP - DIFFERENT footprint, NOT drop-in |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Number of Channels | 2 (dual, simultaneous) | 2 (dual, simultaneous) | 1 (single) | 1 (single) | 2 (dual) |
| Sampling Rate (per channel) | 65 Msps | 65 Msps | 105 Msps (+62%) | 80 Msps (+23%) | 20 Msps (-69%) |
| Data Interface | Serial SPI | Serial SPI | Serial SPI | Serial SPI | Serial SPI |
| Analog Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Quantity Code | C1 | C1:5 (tray/reel packaging code) | C1:5 | C1:5 | C1:1 |
主な差別化要因
- Dual-channel simultaneous sampling at 65 Msps （vs ADC1010S105HN/C1:5)
- Highest sample-rate headroom in the 64-HVQFN family at this resolution （vs ADC1002S020HL/C1:1)
- Exposed thermal pad for industrial-grade continuous operation （vs ADC1012D065HN/C1:5)
設計ノート
Estimated: At 65 Msps dual-channel operation with 1.8V analog and digital supplies, plan for a regulated low-noise LDO (e.g. ADP1755) followed by ferrite-bead + bulk-bypass networks. Place 0.1uF X7R ceramics within 2 mm of each AVDD pin and a shared 10uF bulk near the IC. The reference-decoupling capacitor at REF_TOP and REF_BOT is critical for SFDR at high input frequencies; per the NXP evaluation kit reference design, 10uF X7R plus 100nF NP0 stacked at the REF pins is the recommended layout.
The HVQFN-64 9x9 mm package requires careful routing of the analog input pairs to avoid common-mode-to-differential conversion in long parallel runs. Use a four-layer stack-up with continuous ground plane on layer 2 directly below the ADC; route the analog inputs as length-matched 50 ohm differential pairs from the front-end driver to the AINx_P/AINx_N pins. Maintain solid pours on AVDD and DVDD, stitching vias around the periphery of the exposed pad at 1.5x via diameter spacing for thermal relief.
The exposed thermal pad must be soldered to a low-impedance analog ground pour for both electrical ground reference and heat conduction. Decoupling capacitors should be placed adjacent to AVDD/AGND pairs and routed with short vias directly into the ground plane-no traces under the pad. Digital outputs (DRDY, DCLK, D_OUT_x) should be length-matched within 0.5 mm if running LVDS mode at full sample rate to maintain valid data capture across all bits.
Estimated: Driving the analog inputs through a wideband ADC driver (e.g. ADA4932-1 or ADA4950) preserves the part's dynamic range when fed from a 50-ohm source. For full 65 Msps operation, the -3 dB input bandwidth must exceed ~30 MHz; the source impedance seen at each analog input should be tuned with the common-mode capacitor to keep kick-back noise below 1 LSB at the worst-case code transitions.
Do not run long parallel traces under the input traces or between power domains - coupling into the analog input pairs can easily degrade SNR. Sharing the supply between AVDD and the noisy digital rails will inject switching noise into the reference and limit SFDR; use a dedicated linear regulator for the ADC and bulk-decoupling at the regulator's load pin. Per NXP, the REF pins require a 10uF decoupling capacitor in parallel with 100 nF for stable operation-omitting either reduces INL and increases noise.
コンプライアンス情報
RoHS compliance and lead-free status confirmed via DigiKey listing for ADC1012D065HN/C1:5 (same die as ADC1012D065HN/C1). REACH and AEC-Q100 grade were not specified in the verified web data - marked unknown/not_applicable accordingly. Halogen-free status not directly stated; consult NXP material declaration for confirmation.
