ADC12040CIVY - 12-Bit 40MSPS Pipelined ADC | Texas Instruments
部品番号: ADC12040CIVY ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $8.62 | $8.62 |
| 10 | $7.74 | $77.40 |
| 100 | $6.91 | $691.00 |
| 500 | $6.18 | $3,090.00 |
| 1,000 | $5.52 | $5,520.00 |
ADC12040CIVY 概要
An analog-to-digital converter (ADC) is a data-converter integrated circuit that samples continuous-time analog signals and produces discrete-time digital codes. Within the data-converter hierarchy, ADCs sit alongside DACs (digital-to-analog converters), and the pipelined ADC architecture used in the ADC12040 is one of the most popular for medium-to-high sampling rates (10 MSPS to several hundred MSPS) because it balances high throughput, low power, and small die area better than flash or SAR alternatives. Pipeline ADCs use multiple cascaded low-resolution stages with digital error correction, and the architecture scales efficiently with bit count.
Key specifications include ±0.4 LSB typical differential non-linearity (DNL), 69 dB typical signal-to-noise ratio (SNR) at fIN = 10 MHz, and 11.2 bits typical effective number of bits (ENOB) at the same input frequency. The integrated reference buffer eliminates the need for external reference buffering, and an on-chip power-down mode reduces consumption to microamp levels between conversions. Pin compatibility with the ADC12010, ADC12020, ADC12L063, and ADC12L066 simplifies migration between speed grades within the same family.
The device uses a CMOS pipeline core with an internal sample-and-hold and a selectable single-ended or differential input path. A buffered, high-impedance single-ended reference input is converted on-chip to a differential reference for the processing chain, simplifying PCB layout. Output data format is straight binary, and the parallel interface easily interfaces with FPGAs, ASICs, or microcontrollers.
Typical applications include IF sampling in communications receivers, ultrasound imaging front-ends, CCD digitizers, video digitizing, and portable instrumentation. The 40 MSPS rate is sufficient for baseband I/Q capture in narrowband radios and for time-domain analysis up to ~20 MHz of analog bandwidth when undersampling or full Nyquist operation is desired.
When designing with this part, route analog inputs as a 50-ohm matched differential pair and bypass the +5V supply with a 10uF tantalum plus 0.1uF ceramic decoupling network within 5 mm of the supply pin. Use a low-impedance analog ground plane and keep digital outputs away from the analog inputs to preserve SNR.
This page synthesizes distributor pricing, drop-in alternatives and practical design notes beyond what the manufacturer datasheet alone provides.
ドロップイン代替品: ADC12040CIVY — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC12040CIVY （同一形状・フットプリント） — 相違点: Package, Architecture, RoHS Status, Number of Channels, Analog Supply Voltage.
クイック比較ツール — 並列比較する代替部品を選択:
ADC12040CIVYX/NOPB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC12040CIVY/NOPB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC12020CIVY
✅ ドロップイン✓ 在庫あり
$7.25 / 個
データシートを見る →ADC12010CIVY
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC12L063CIVY
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC12L066CIVY
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC12040CIVY 最大定格＆電気的特性
| 分解能 | 12 bit |
| サンプリングレート | 40 MSPS (min 40 MSPS over temperature) |
| Number of Channels | 1 input |
| Architecture | Pipelined |
| 電源電圧 | +5V ±5% (single supply) |
| Power Consumption | 340 mW (typ) at 40 MHz |
| Differential Non-Linearity (DNL) | ±0.4 LSB (typ) |
| Signal-to-Noise Ratio (SNR) | 69 dB (typ) at fIN = 10 MHz |
| Effective Number of Bits (ENOB) | 11.2 bits (typ) at fIN = 10 MHz |
| Input Type | Differential (single-ended capable) |
| Reference Type | External, with internal buffer |
| Digital Output Interface | Parallel, CMOS, straight binary |
| Digital Output Logic Levels | 2.35V to 5V compatible |
| Power Down Mode | On-chip (low quiescent between conversions) |
| 動作温度範囲 | -40C to +85C (industrial) |
| パッケージ | 32-LQFP (NEY) 7x7 mm |
| 実装タイプ | Surface Mount |
| Pin Family Compatibility | Pin compatible with ADC12010, ADC12020, ADC12L063, ADC12L066 |
| RoHS ステータス | Compliant (NOPB suffix variants only; check exact suffix) |
ADC12040CIVY ピン構成
| ピン 1 | DVDD — Digital supply voltage |
| ピン 2 | DGND — Digital ground |
| ピン 3 | D0-D11 (LSB) — Parallel CMOS output bits |
| ピン 4 | D1 — Parallel CMOS output bit |
| ピン 5 | D2 — Parallel CMOS output bit |
| ピン 6 | D3 — Parallel CMOS output bit |
| ピン 7 | D4 — Parallel CMOS output bit |
| ピン 8 | D5 — Parallel CMOS output bit |
| ピン 9 | D6 — Parallel CMOS output bit |
| ピン 10 | D7 — Parallel CMOS output bit |
| ピン 11 | D8 — Parallel CMOS output bit |
| ピン 12 | D9 — Parallel CMOS output bit |
| ピン 13 | D10 — Parallel CMOS output bit |
| ピン 14 | D11 (MSB) — Parallel CMOS output bit |
| ピン 15 | PD — Power down (active high) |
| ピン 16 | AVDD — Analog supply voltage |
| ピン 17 | AGND — Analog ground |
| ピン 18 | VIN+ — Differential analog input positive |
| ピン 19 | VIN- — Differential analog input negative |
| ピン 20 | VREF — External reference input (buffered internally) |
| ピン 21 | VCM — Common-mode voltage bypass |
| ピン 22 | AGND — Analog ground |
| ピン 23 | NC — Not connected (per datasheet) |
| ピン 24 | NC — Not connected (per datasheet) |
| ピン 25 | CLK — Conversion clock input |
| ピン 26 | CLK\ — Complementary conversion clock (differential) |
| ピン 27 | DGND — Digital ground |
| ピン 28 | DVDD — Digital supply voltage |
| ピン 29 | OF — Output enable (tri-states parallel outputs) |
| ピン 30 | AGND — Analog ground |
| ピン 31 | AVDD — Analog supply voltage |
| ピン 32 | AGND — Analog ground |
主な用途
ADC12040CIVY の用途: 6 件s: IF Sampling in Communications Receivers, Ultrasound Imaging Front-End, CCD and Image Sensor Digitizer, Video Digitizing / Broadcast Equipment, Portable Test and Measurement Instrumentation, Industrial Data Acquisition Module.
IF Sampling in Communications Receivers
The ADC12040CIVY's 40 MSPS sampling rate and 69 dB SNR at 10 MHz input make it well-suited for IF sampling in narrowband communications receivers. Placing the ADC at the intermediate-frequency output of a superheterodyne chain lets the digital demodulator process baseband I/Q in software, eliminating analog quadrature mixers. The integrated sample-and-hold provides anti-aliasing at the IF stage, while the on-chip reference buffer simplifies PCB layout versus external ADCs. Power consumption is held to 340 mW typical, an advantage over flash converters at this speed. Pin compatibility with the ADC12010/020/12L063/12L066 family lets a single 32-LQFP footprint support multiple bandwidth SKUs.
おすすめ
Ultrasound Imaging Front-End
The ADC12040CIVY delivers 12-bit resolution at 40 MSPS, suitable for digitizing amplified echo signals in medical ultrasound receive channels up to 20 MHz analog bandwidth. The pipelined architecture provides low-latency deterministic conversion, critical for real-time beamforming. Differential inputs reject common-mode noise from the pulser, while the CMOS parallel output feeds the FPGA beam-former directly. Power stays at 340 mW per channel, allowing dense multi-channel array layouts. Internal reference buffer eliminates the per-channel external reference driver, lowering board area and BOM cost. The 32-LQFP footprint simplifies manufacturing compared to BGA parts on cost-sensitive probes.
おすすめ
CCD and Image Sensor Digitizer
The 12-bit ADC12040CIVY pairs well with CCD line-scan and area-image sensors that output pixel-rate streams up to 40 MHz, sampling each pixel accurately into the digital domain. Its differential inputs accept the typical CCD output via a differential driver, while the CMOS parallel output drops straight into an FPGA/ASIC for color-space conversion and gamma correction. The 69 dB SNR keeps pixel noise floor low enough for 10-bit precision in dim scenes. On-chip power-down lowers consumption between line scans, important for battery-powered portable scanners. The 32-LQFP (NEY) 7x7 mm footprint suits compact camera PCB layouts.
おすすめ
Video Digitizing / Broadcast Equipment
The ADC12040CIVY digitizes standard-definition and intermediate-bandwidth video signals up to 40 MSPS, supporting composite, Y/C, or component capture with 12-bit precision for capture cards, medical imaging, and broadcast test equipment. The 2.35V-5V CMOS outputs interface to HDMI receivers, processors, or FPGAs without extra level translation. Differential inputs reject ground bounce from long cable runs, and the 69 dB SNR ensures clean chroma capture free of converter-induced artifacts. The single +5V supply simplifies power architecture versus dual-supply parts. Pin compatibility with the lower-speed ADC12010/ADC12020 lets OEMs support multiple products with one PCB.
おすすめ
Portable Test and Measurement Instrumentation
The ADC12040CIVY works well in handheld oscilloscopes, spectrum analyzers and bench data-acquisition modules that demand 12-bit precision and 40 MSPS in a small, low-power footprint. Its 340 mW consumption keeps battery life tolerable, while the internal sample-and-hold and reference buffer minimize external parts count. Differential inputs accept active probes directly, and the parallel output feeds field-programmable gate arrays that perform triggering and waveform processing. Power-down mode allows the converter to be idle between acquired bursts, extending runtime. The 32-LQFP industrial -40C to +85C rating handles field-temperature environments.
おすすめ
Industrial Data Acquisition Module
The ADC12040CIVY digitizes wide-bandwidth transducer signals in industrial monitoring systems - vibration, sonar, and process-control analog channels - where 12-bit resolution and 40 MSPS give engineers adequate margin for analysis. Differential inputs reject common-mode noise from motor inverters and relay switching, while the CMOS parallel output drops into an industrial MCU or FPGA. The 32-LQFP NEY package and -40C to +85C rating suit factory-floor environments. Pin compatibility with the wider ADC120xx / ADC12L0xx family offers multiple speed grades from a single PCB, reducing SKUs in modular product lines.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC12040CIVY — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC12040CIVYX/NOPB | ADC12040CIVY/NOPB | ADC12020CIVY | ADC12010CIVY | ADC12L063CIVY |
|---|---|---|---|---|---|---|
| Package | 32-LQFP (NEY) 7x7 mm | 32-LQFP (NEY) 7x7 mm - same | 32-LQFP (NEY) 7x7 mm - same | 32-LQFP (NEY) 7x7 mm - same | 32-LQFP (NEY) 7x7 mm - same | 32-LQFP (NEY) 7x7 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sampling Rate | 40 MSPS | 40 MSPS | 40 MSPS | 20 MSPS (-50%) | 10 MSPS (-75%) | 63 MSPS (+57.5%) |
| Supply Voltage | +5V | +5V | +5V | +5V | +5V | +3.3V (lower-power family) |
| Power Consumption | 340 mW (typ) | 340 mW | 340 mW | lower (20 MSPS) | lower (10 MSPS) | lower-power family |
| ENOB at 10 MHz | 11.2 bits | 11.2 bits | 11.2 bits | 11.2 bits (typ) | 11.2 bits (typ) | 11.2 bits (typ) |
| RoHS / NOPB Option | Non-NOPB only (check callout) | Yes (NOPB, RoHS) | Yes (NOPB, RoHS) | Check suffix variant | Check suffix variant | Check suffix variant |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主な差別化要因
- Pin compatibility with the entire ADC120xx family （vs ADC12020CIVY)
- Lowest-power 40 MSPS in family （vs ADC12L063CIVY)
- Integrated reference buffer eliminates external driver （vs Discrete ADC + external reference)
設計ノート
Decouple the +5V AVDD with a 10uF tantalum in parallel with a 0.1uF ceramic capacitor placed within 5 mm of the AVDD pin; apply the same 0.1uF plus bulk scheme to DVDD. Keep AVDD and DVDD traces star-connected at a common ferrite bead to prevent digital switching noise from coupling into the analog supply. Estimated: power consumption is dominated by the analog supply at 340 mW when sampling at 40 MHz.
Place the ADC12040CIVY on a single solid analog ground plane that extends under the device, with the digital ground return path kept short. Route the parallel output bus as 50 ohm controlled-impedance traces and route the analog differential input pair (VIN+, VIN-) as a matched 100 ohm differential transmission line, terminating at a low-jitter clock source. Maintain at least 3x trace-spacing between analog inputs and digital outputs to minimize digital switching noise coupling.
Exceeding the +5V supply tolerance (>5.25V) may permanently damage the device. The PD (power-down) pin must be tied low during normal operation; if left floating, internal pull-ups can place the device in shutdown mode. The CLK and CLKB\ inputs require low-jitter (< 1 ps RMS) clocks; any jitter above ~1 ps degrades SNR by approximately 20 dB per decade.
Estimated: at 340 mW typical dissipation in a 32-LQFP with theta_JA of approximately 50 C/W, junction temperature rise above ambient is roughly 17C - well within the -40C to +85C industrial rating. Forced-air cooling is not required, but the part should still be placed away from high-power heat sources to maintain accuracy.
コンプライアンス情報
RoHS compliance applies to NOPB suffix variants (e.g., ADC12040CIVY/NOPB). Standard ADC12040CIVY is non-NOPB and may not be RoHS-compliant for end-markets requiring it; verify the exact suffix before ordering. AEC-Q100 is not applicable because this is a commercial/industrial-grade converter.
