ADS5103CPFB - 10-Bit 40MSPS 1.8V ADC w/Pwrdwn | Texas Instruments
部品番号: ADS5103CPFB ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $11.5 | $11.50 |
| 10 | $10.2 | $102.00 |
| 100 | $8.95 | $895.00 |
| 500 | $7.8 | $3,900.00 |
| 1,000 | $6.95 | $6,950.00 |
ADS5103CPFB 概要
An ADC is a data-conversion integrated circuit that samples a continuous-time analog signal and quantizes it into a discrete digital code. The pipelined architecture used in the ADS5103 family performs coarse quantization in early stages and fine quantization in later stages, allowing high sample rates (tens of MSPS) at modest power consumption. Within the broader hierarchy: ADC -> data converter -> data-acquisition IC -> mixed-signal semiconductor, the ADS5103 sits in the low-power, low-voltage, mid-speed tier typically used for imaging, video digitizers, and portable instrumentation.
Headline specifications include 10-bit resolution, 40 MSPS sample rate (the ADS5102 sibling in the same datasheet runs at 65 MSPS), 1.8 V analog and digital supply, an internal reference that can be overdriven externally, a 1.8 V CMOS-compatible digital interface (3.3 V tolerant at the output), and a low-power power-down mode that drops quiescent draw between bursts of conversion. The 48-pin TQFP exposes both IN+ and IN- differential inputs, an internal reference pin (REF), bandgap decoupling (REFT/REFB), and a parallel output bus.
The converter uses a switched-capacitor pipelined front end followed by an internal digital error-correction stage. The 1.8 V core reduces digital switching noise coupling back into the analog front end, while the internal reference eliminates the external reference and bias network typically required by older 5 V ADCs. The parallel CMOS/3.3 V output bus simplifies timing closure in FPGA capture logic compared with LVDS-output ADCs.
Typical applications include portable digital imaging, baseband I/Q digitization in low-cost software-defined radio, ultrasound front-end digitization, CCD/CIS sensor readout, and low-power medical instrumentation. Differential signaling on the analog inputs allows direct AC-coupling from single-ended sources via a 1:1 transformer or an active driver. The 40 MSPS rate comfortably captures 20 MHz of analog input bandwidth, adequate for IF-sampling digitizers in narrowband radio receivers.
When designing with this device, ensure the analog and digital grounds are tied at a single point near the REFT/REFB bypass capacitors, and place 0.1 uF plus 10 uF decoupling on every supply pin. The internal reference does not require external buffering but the REFT/REFB pins must be bypassed close to the package. Power-down timing must respect the wake-up latency before initiating conversions. This page synthesizes distributor pricing, drop-in alternative guidance, and design notes that are not aggregated on any single manufacturer or distributor page.
ドロップイン代替品: ADS5103CPFB — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS5103CPFB （同一形状・フットプリント） — 相違点: Package, Digital Supply Voltage, Input Type, Resolution, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
ADS5102IPFBR
✅ ドロップイン✓ 在庫あり
$5.05 / 個
データシートを見る →ADS5103CPFBR
✅ ドロップイン✓ 在庫あり
$4.45 / 個
データシートを見る →ADS5103CPFBG4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC12040CIVY
✅ ドロップイン✓ 在庫あり
$5.52 / 個
データシートを見る →ADC1003S050TS/C1
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$7.4 / 個
データシートを見る →ADS5103CPFB 最大定格＆電気的特性
| 分解能 | 10 bit |
| Sample Rate | 40 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V (3.3 V tolerant outputs) |
| Input Type | Differential |
| Reference | Internal, with external overdrive option |
| Data Interface | Parallel CMOS |
| Power-Down Mode | Yes |
| パッケージ | TQFP-48 (PFB) 7x7 mm |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C |
| RoHS ステータス | unknown |
ADS5103CPFB ピン構成
| ピン 1 | IN+ — Differential analog input positive |
| ピン 2 | IN- — Differential analog input negative |
| ピン 3 | REFT — Top reference decoupling |
| ピン 4 | REFB — Bottom reference decoupling |
| ピン 5 | REF — Internal reference output / external reference input |
| ピン 6 | AGND — Analog ground |
| ピン 7 | AVDD — 1.8 V analog supply |
| ピン 8 | AGND — Analog ground |
| ピン 9 | CLK — Conversion clock input |
| ピン 10 | DGND — Digital ground |
| ピン 11 | DVDD — 1.8 V digital supply |
| ピン 12 | DGND — Digital ground |
| ピン 13 | PDN — Power-down input (active high) |
| ピン 14 | D0 — Digital output bit 0 (LSB) |
| ピン 15 | D1 — Digital output bit 1 |
| ピン 16 | D2 — Digital output bit 2 |
| ピン 17 | D3 — Digital output bit 3 |
| ピン 18 | D4 — Digital output bit 4 |
| ピン 19 | D5 — Digital output bit 5 |
| ピン 20 | D6 — Digital output bit 6 |
| ピン 21 | D7 — Digital output bit 7 |
| ピン 22 | D8 — Digital output bit 8 |
| ピン 23 | D9 — Digital output bit 9 (MSB) |
| ピン 24 | DRDY — Data ready output |
| ピン 25 | NC — Not connected (per datasheet) |
| ピン 26 | NC — Not connected (per datasheet) |
| ピン 27 | NC — Not connected (per datasheet) |
| ピン 28 | NC — Not connected (per datasheet) |
| ピン 29 | NC — Not connected (per datasheet) |
| ピン 30 | NC — Not connected (per datasheet) |
| ピン 31 | AGND — Analog ground |
| ピン 32 | AVDD — 1.8 V analog supply |
| ピン 33 | AGND — Analog ground |
| ピン 34 | AVDD — 1.8 V analog supply |
| ピン 35 | AGND — Analog ground |
| ピン 36 | AVDD — 1.8 V analog supply |
| ピン 37 | BIAS — Bias decoupling |
| ピン 38 | AGND — Analog ground |
| ピン 39 | REFT — Top reference decoupling |
| ピン 40 | REFB — Bottom reference decoupling |
| ピン 41 | AGND — Analog ground |
| ピン 42 | IN+ — Differential analog input positive (alternate) |
| ピン 43 | IN- — Differential analog input negative (alternate) |
| ピン 44 | AGND — Analog ground |
| ピン 45 | DVDD — 1.8 V digital supply |
| ピン 46 | DGND — Digital ground |
| ピン 47 | DVDD — 1.8 V digital supply |
| ピン 48 | DGND — Digital ground |
主な用途
ADS5103CPFB の用途: 6 件s: Portable Digital Imaging, Baseband I/Q Digitization in Software-Defined Radio, Ultrasound Front-End Digitization, CCD/CIS Sensor Readout, Low-Power Test and Measurement Instrumentation, Industrial Process Control Monitoring.
Portable Digital Imaging
The ADS5103CPFB's 40 MSPS sample rate and 10-bit resolution are well matched to portable digital still-camera and camcorder imaging pipelines, where CCD/CIS sensor pixel clocks typically run in the 20-40 MHz range. The single 1.8 V supply reduces battery drain versus 5 V imaging ADCs, and the integrated power-down mode lets designers gate conversion current between frame captures, an essential feature for battery-powered cameras. Differential analog inputs accommodate direct transformer-coupled drive from CIS sensors. The TQFP-48 footprint fits compact board layouts, and the parallel CMOS outputs route cleanly into mobile image processors and entry-level FPGAs.
おすすめ
Baseband I/Q Digitization in Software-Defined Radio
In low-cost software-defined radio receivers, the ADS5103CPFB can digitize baseband I/Q signals directly after a quadrature demodulator. Its 40 MSPS rate comfortably captures 20 MHz of analog bandwidth, enough for narrowband amateur, ISM, and shortwave HF bands. The 1.8 V single supply simplifies power-rail design in portable SDR dongles, and the internal reference removes external bias components. Differential inputs pair cleanly with audio-style transformers feeding the demodulator outputs. The parallel CMOS bus maps directly into entry-level FPGA fabric for FFT and demodulation processing, and the power-down pin enables duty-cycled receive windows that extend battery life in field-deployable radios.
おすすめ
Ultrasound Front-End Digitization
Portable diagnostic ultrasound uses 8-12-bit ADCs running at 30-65 MSPS to digitize beamformer channels after the time-gain-compensation stage. The ADS5103CPFB fits 10-bit, 40 MSPS medical imaging designs where its 1.8 V low-power operation keeps per-channel thermal budgets low and its differential inputs reject common-mode pickup along long transducer cables. The integrated internal reference reduces external BOM count, important for multi-channel beamformer boards that stack many ADCs side-by-side. Parallel CMOS outputs simplify fan-out to FPGAs implementing delay-and-sum beamforming. Note that newer medical designs typically select 12-14-bit ADCs for greater dynamic range, but the ADS5103CPFB remains in legacy repair pipelines.
おすすめ
CCD/CIS Sensor Readout
Industrial line-scan and area-scan cameras using CCD or CMOS image sensors need a fast, low-power ADC on the analog video output. The ADS5103CPFB digitizes CIS analog outputs at 40 MSPS with 10-bit precision, matching typical 10-bit pixel pipelines. Its 1.8 V single supply and small TQFP-48 footprint suit compact camera-head electronics, while differential inputs reject noise picked up along flex cables between the sensor and ADC. The internal reference avoids external bandgap components. The parallel CMOS outputs stream pixels directly into FPGA logic that performs black-level clamping, gamma correction, and MIPI/USB3 output formatting.
おすすめ
Low-Power Test and Measurement Instrumentation
Bench-top oscilloscopes, logic-analyzer pods, and portable data-acquisition modules benefit from the ADS5103CPFB's 40 MSPS sample rate at low power consumption. Its 1.8 V supply keeps thermal design simple for handheld units, and the integrated internal reference plus 10-bit resolution cover general-purpose digitizer channels where 12-14 bits of dynamic range are not required. The parallel CMOS outputs interface easily with low-cost FPGAs implementing capture buffers and USB/Ethernet links. The power-down mode lets designers gate conversion activity between acquisition windows, extending battery life in field-portable instruments and remote data loggers.
おすすめ
Industrial Process Control Monitoring
Industrial 4-20 mA loop digitization, vibration sensor readout, and motor-control feedback paths often use 10-bit, 40 MSPS-class ADCs where high dynamic range is not the bottleneck. The ADS5103CPFB's differential inputs pair cleanly with instrumentation amplifiers monitoring low-level analog signals, and its 1.8 V supply allows integration into modern industrial controllers powered from 3.3 V or 5 V rails via local LDOs. The TQFP-48 package supports standard SMT assembly lines, and the parallel CMOS outputs feed directly into industrial MCUs and FPGAs running PID loops. The power-down mode is useful for duty-cycled monitoring to reduce average power in remote sensor nodes.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS5103CPFB — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS5102IPFBR | ADS5103CPFBR | ADS5103CPFBG4 | ADC12040CIVY | ADC1003S050TS/C1 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | TQFP-48 (PFB) 7x7 mm | TQFP-48 (PFB) 7x7 mm - same | TQFP-48 (PFB) 7x7 mm - same | TQFP-48 (PFB) 7x7 mm - same | TQFP-48 (PFB) 7x7 mm - same | TQFP-48 (PFB) 7x7 mm - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 12 bit | 10 bit |
| Sample Rate | 40 MSPS | 65 MSPS | 40 MSPS | 40 MSPS | 40 MSPS | 50 MSPS |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 3.0 V (verify) | 3.0 V (verify) |
| Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Input Type | Differential | Differential | Differential | Differential | Differential (verify) | Differential (verify) |
| Power-Down Mode | Yes | Yes | Yes | Yes | Yes (verify) | Yes (verify) |
主な差別化要因
- Pin-compatible upgrade path within same family （vs ADS5102IPFBR)
- Lower-voltage single-supply operation vs older 5V ADCs （vs ADC1003S050TS/C1)
- Integrated internal reference reduces external BOM （vs Older 5V 10-bit ADCs without internal reference)
設計ノート
The ADS5103CPFB is sensitive to digital switching noise coupling into the analog front end through the shared 1.8 V supply. Split AVDD and DVDD planes with a ferrite bead or small inductor, and place 0.1 uF plus 10 uF ceramic decoupling on every supply pin within 5 mm of the package. Reference the REFT and REFB bandgap pins close to the IC; long traces here degrade integral nonlinearity and SNR.
Use the device's power-down (PDN) pin to gate conversion activity in battery-powered designs. According to TI datasheet literature for the ADS5102/3 family, the wake-up latency from power-down is on the order of a few microseconds, so budget that delay when transitioning into a conversion burst. Power-down current is orders of magnitude lower than active quiescent, so duty-cycling between frame captures can extend battery life by 5-10x in portable imaging applications.
Drive the differential analog inputs through a 1:1 impedance-ratio transformer or a low-noise differential amplifier; do not drive single-ended signals directly into IN+ or IN-. The internal reference defaults to a typical value but can be overdriven externally if a tighter reference is required for calibration; in that case, decouple the REF pin to a clean analog ground. Route the parallel CMOS outputs with matched trace lengths to avoid setup/hold violations on the capture FPGA.
Do not exceed the absolute maximum analog input voltage, which is typically AVDD + 0.3 V; transient over-voltage events from input ESD or transformer ringing can latch-up the input stage. Ensure the CLK input is clean and monotonic - jitter on the conversion clock directly translates to aperture-time uncertainty and degrades SNR. According to TI datasheet literature for the ADS5102/3 family, this part is pin-compatible with ADS5102, so swapping to ADS5102IPFBR gives 65 MSPS without any PCB change.
コンプライアンス情報
RoHS/REACH compliance was not stated explicitly in the Verified Web Data; for new RoHS-compliant designs select a modern pin-compatible alternative such as ADS5102IPFBR
