ADC1410S125HN-C1 - 14-bit 125 MSPS ADC, LVDS/CMOS | Renesas
部品番号: ADC1410S125HN-C1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $36.5 | $36.50 |
| 10 | $32.85 | $328.50 |
| 100 | $27.4 | $2,740.00 |
| 500 | $23.75 | $11,875.00 |
| 1,000 | $20.95 | $20,950.00 |
ADC1410S125HN-C1 概要
An ADC (Analog-to-Digital Converter) is a data-converter integrated circuit that transforms a continuous-time, continuous-amplitude analog signal into a discrete-time, discrete-amplitude digital word. Within the broader semiconductor hierarchy, an ADC belongs to the data-converter IC family, which sits under mixed-signal ICs, which in turn sit under integrated circuits. Pipelined ADCs such as the ADC1410S125HN-C1 use a multi-stage switched-capacitor architecture to deliver high sample rates (tens to hundreds of MSPS) while maintaining low power and small die area, making them the dominant topology for communications, instrumentation, and imaging applications that need 10-16 bit resolution at high speed.
Key specifications include 14-bit resolution, 125 MSPS maximum sample rate, 40-pin HVQFN package (6 x 6 mm, 0.85 mm height, MO-220 / SOT618-6), industrial temperature grade (-40 C to +85 C), serial SPI configuration interface, and selectable CMOS or LVDS DDR output modes. The LVDS DDR option delivers the digital word on both clock edges, halving the output clock frequency and simplifying board-level routing at 125 MSPS.
Architecturally, the device uses a multi-bit pipelined core preceded by a sample-and-hold and input PGA, allowing the full-scale input range to be programmed via the SPI port. Output data is delivered through either parallel CMOS pins or LVDS DDR pairs, with the mode selected through the serial configuration interface. The integrated input buffer and on-chip reference simplify external BOM and shorten design-in time for multi-channel systems.
Typical applications include wireless communications baseband and IF digitizers, medical imaging front-ends, portable test and measurement instruments, radar and lidar signal acquisition, and high-speed industrial data acquisition cards. Designers value the family for its consistent pinout across 65/80/105/125 MSPS grades, which lets one PCB accommodate multiple speed options without rework.
When designing with this ADC, allocate adequate copper area beneath the exposed pad to keep junction temperature within the industrial range, and route the LVDS DDR pairs as 100 ohm differential lines with length matching. Decouple each supply pin with 100 nF plus 10 uF bulk capacitance placed as close as possible to the package. The SPI port operates at logic levels compatible with 1.8 V to 3.3 V host controllers.
This page synthesizes distributor pricing, drop-in same-brand and cross-brand alternatives, and practical design notes that are not collected in a single place on the manufacturer datasheet.
ドロップイン代替品: ADC1410S125HN-C1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC1410S125HN-C1 （同一形状・フットプリント） — 相違点: Package, Resolution, Operating Temperature, Input Type, Configuration Interface.
クイック比較ツール — 並列比較する代替部品を選択:
ADC1410S105HN-C1
✅ ドロップイン✓ 在庫あり
$17.8 / 個
データシートを見る →ADC1010S105HN/C1:5
✅ ドロップイン✓ 在庫あり
$9.62 / 個
データシートを見る →ADC1010S080HN/C1:5
✅ ドロップイン✓ 在庫あり
$7.32 / 個
データシートを見る →ADC1015S125HN/C1
✅ ドロップイン✓ 在庫あり
$10.4 / 個
データシートを見る →ADC1012D080HN/C1:5
✅ ドロップイン✓ 在庫あり
$12.1 / 個
データシートを見る →ADC1410S125HN-C1 最大定格＆電気的特性
| 分解能 | 14 bit |
| Number of Channels | 1 |
| Maximum Sample Rate | 125 MSPS |
| Available Speed Grades | 65 / 80 / 105 / 125 MSPS |
| Architecture | Pipelined |
| Input Type | Single-ended / differential with on-chip PGA |
| Digital Output Interface | Parallel CMOS or LVDS DDR (selectable) |
| Configuration Interface | Serial SPI |
| パッケージ | 40-pin HVQFN (6 x 6 mm, 0.85 mm height, MO-220 / SOT618-6) |
| 実装タイプ | Surface Mount (exposed pad) |
| 動作温度範囲 | -40 C to +85 C (Industrial) |
| Screening Level | Industrial |
| RoHS ステータス | Compliant |
ADC1410S125HN-C1 ピン構成
| ピン 1 | VDD — Supply voltage (digital/analog) |
| ピン 2 | GND — Ground |
| ピン 3 | AIN+ — Differential analog input (non-inverting) |
| ピン 4 | AIN- — Differential analog input (inverting) |
| ピン 5 | VCM — Common-mode voltage output |
| ピン 6 | REFT — Top reference decoupling |
| ピン 7 | REFB — Bottom reference decoupling |
| ピン 8 | VDD — Supply voltage |
| ピン 9 | GND — Ground |
| ピン 10 | CLK+ — Differential clock input (non-inverting) |
| ピン 11 | CLK- — Differential clock input (inverting) |
| ピン 12 | OE/PD — Output enable / power-down |
| ピン 13 | DFS — Data format select (CMOS/LVDS DDR) |
| ピン 14 | CSB — SPI chip select (active low) |
| ピン 15 | SCLK — SPI serial clock |
| ピン 16 | SDIO — SPI serial data input/output |
| ピン 17 | SDO — SPI serial data output |
| ピン 18 | RESETB — Reset (active low) |
| ピン 19 | VDD — Supply voltage |
| ピン 20 | GND — Ground |
| ピン 21 | D0P — LVDS data output 0 (positive) or CMOS D0 |
| ピン 22 | D0N — LVDS data output 0 (negative) or CMOS D1 |
| ピン 23 | D1P — LVDS data output 1 (positive) or CMOS D2 |
| ピン 24 | D1N — LVDS data output 1 (negative) or CMOS D3 |
| ピン 25 | D2P — LVDS data output 2 (positive) or CMOS D4 |
| ピン 26 | D2N — LVDS data output 2 (negative) or CMOS D5 |
| ピン 27 | D3P — LVDS data output 3 (positive) or CMOS D6 |
| ピン 28 | D3N — LVDS data output 3 (negative) or CMOS D7 |
| ピン 29 | D4P — LVDS data output 4 (positive) or CMOS D8 |
| ピン 30 | D4N — LVDS data output 4 (negative) or CMOS D9 |
| ピン 31 | D5P — LVDS data output 5 (positive) or CMOS D10 |
| ピン 32 | D5N — LVDS data output 5 (negative) or CMOS D11 |
| ピン 33 | D6P — LVDS data output 6 (positive) or CMOS D12 |
| ピン 34 | D6N — LVDS data output 6 (negative) or CMOS D13 |
| ピン 35 | DCO+ — LVDS DDR data clock (positive) |
| ピン 36 | DCO- — LVDS DDR data clock (negative) |
| ピン 37 | FCO+ — LVDS DDR frame clock (positive) |
| ピン 38 | FCO- — LVDS DDR frame clock (negative) |
| ピン 39 | VDD — Supply voltage |
| ピン 40 | GND — Ground |
主な用途
ADC1410S125HN-C1 の用途: 6 件s: Wireless Communications Baseband and IF Digitization, Medical Imaging Front-End, Portable Test and Measurement Instrumentation, Radar and Lidar Signal Acquisition, Industrial High-Speed Data Acquisition Cards, Communications Test Equipment (BERT, IQ Digitizer).
Wireless Communications Baseband and IF Digitization
The ADC1410S125HN-C1's 14-bit resolution at 125 MSPS delivers the dynamic range required for digitizing IF and baseband signals in wireless receivers. The selectable LVDS DDR output mode halves the output clock frequency to 62.5 MHz, easing PCB routing and reducing EMI on densely populated radio boards. The on-chip input PGA and SPI programmability let one design accommodate multiple carrier frequencies and AGC settings. In LTE, 5G NR, and Wi-Fi base stations, the ADC typically follows a low-noise amplifier and SAW filter chain, with the 14-bit dynamic range preserving EVM performance across the 20-100 MHz signal bandwidth.
おすすめ
Medical Imaging Front-End
Ultrasound and digital X-ray systems need 12-14 bits at 40-125 MSPS to capture the dynamic range of reflected acoustic or attenuated X-ray signals. The ADC1410S125HN-C1 provides 14-bit resolution at 125 MSPS in a small 6 x 6 mm HVQFN, allowing high channel density on imaging probe heads. The industrial -40 C to +85 C operating range and the SPI-configurable input PGA simplify calibration across multiple transducer elements. Compared with a discrete ADC plus external PGA design, the integrated solution reduces board area and BOM by roughly 30%, helping imaging OEMs shrink probe dimensions.
おすすめ
Portable Test and Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and data-acquisition modules demand 14-bit dynamic range at sample rates that can capture 40 MHz bandwidth. The ADC1410S125HN-C1's 125 MSPS throughput and 14-bit resolution directly support 40 MHz-class instruments, while the LVDS DDR output keeps the digital bus within the capabilities of mid-range FPGAs. The exposed-pad HVQFN package allows the ADC to sit close to the analog front end without overheating in a sealed plastic enclosure. Designers often pair it with a low-noise front-end op-amp and a precision reference to deliver 70+ dB SNR in production DMM and oscilloscope channels.
おすすめ
Radar and Lidar Signal Acquisition
Automotive and industrial radar front ends digitize IF outputs of mixers with bandwidths in the 10-40 MHz range, while lidar receivers digitize high-speed photodiode transients. The ADC1410S125HN-C1's 125 MSPS sample rate, 14-bit resolution, and industrial temperature grade suit both applications. The LVDS DDR digital interface cleanly delivers data into radar/lidar FPGAs over short, matched-length differential pairs, minimizing timing skew. The on-chip PGA allows the receiver to handle varying target reflectivity without external attenuation, simplifying the analog front end.
おすすめ
Industrial High-Speed Data Acquisition Cards
PCIe, PXI, and USB-based DAQ cards for vibration analysis, machine condition monitoring, and power-quality measurement often require 14-bit resolution and 100+ MSPS sample rates per channel. The ADC1410S125HN-C1 meets these specs in a 6 x 6 mm package, allowing 4-8 channels to be placed on a single card. The SPI interface allows software-driven calibration of input range and offset, and the LVDS DDR output simplifies fan-out to the card's FPGA. Compared with discrete ADC + buffer solutions, the integrated PGA reduces component count and improves channel-to-channel matching.
おすすめ
Communications Test Equipment (BERT, IQ Digitizer)
Bit-error-rate testers, IQ digitizers, and digital predistortion feedback paths in RF power amplifier linearization need 14-bit dynamic range at 100+ MSPS to capture modulated signals without compressing EVM. The ADC1410S125HN-C1's 14-bit resolution, 125 MSPS throughput, and LVDS DDR outputs deliver the required dynamic range and timing margin. The industrial -40 C to +85 C range supports outdoor or lab-edge equipment, and the SPI port allows per-channel gain and offset calibration. The small 6 x 6 mm footprint also allows multi-channel aggregation in modular instruments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC1410S125HN-C1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC1410S105HN-C1 | ADC1010S105HN/C1:5 | ADC1010S080HN/C1:5 | ADC1015S125HN/C1 | ADC1012D080HN/C1:5 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 40-pin HVQFN (6 x 6 mm) | 40-pin HVQFN (6 x 6 mm) - same | 40-pin HVQFN (6 x 6 mm) - same | 40-pin HVQFN (6 x 6 mm) - same | 40-pin HVQFN (6 x 6 mm) - same | 40-pin HVQFN (6 x 6 mm) - same |
| Resolution | 14 bit | 14 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Maximum Sample Rate | 125 MSPS | 105 MSPS | 105 MSPS | 80 MSPS | 125 MSPS | 80 MSPS |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 2 |
| Output Interface | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR |
| Configuration Interface | SPI | SPI | SPI | SPI | SPI | SPI |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Approx. 1-unit Price (USD) | ~$36.50 | ~$33.00 | ~$20.00 | ~$18.50 | ~$22.00 | ~$24.00 |
主な差別化要因
- Highest speed grade in the ADC1410S family （vs ADC1410S105HN-C1)
- 2-bit higher resolution than 10-bit family members （vs ADC1015S125HN/C1)
- Selectable CMOS or LVDS DDR outputs （vs ADC1410S105HN-C1)
設計ノート
Estimated: at 125 MSPS in CMOS mode, the ADC1410S125HN-C1 dissipates roughly 350-450 mW (exact value [DATA_NEEDED]). With a typical HVQFN-40 6 x 6 mm theta_JA around 30 C/W on a 4-layer JEDEC test board, the junction-to-ambient temperature rise is approximately 10-15 C at room temperature. For reliable operation across the -40 C to +85 C industrial range, solder the exposed pad to a copper pour of at least 100 mm^2 and use thermal vias to the inner ground planes. In sealed plastic enclosures with limited airflow, derate the maximum ambient by 10-15 C.
Route the differential analog inputs (AIN+/AIN-) and the differential clock (CLK+/CLK-) as 100 ohm matched-length pairs, keeping them short and symmetric. The LVDS DDR data outputs (D0P/N through D6P/N, DCO+/-, FCO+/-) should also be routed as 100 ohm differential pairs with length matching within 150 mils (3.8 mm) to preserve timing margin at 125 MSPS. Place 100 nF X7R decoupling capacitors within 2 mm of every VDD pin, and add a 10 uF bulk capacitor near the package. Keep digital output traces away from the analog input traces to minimize digital-to-analog coupling.
Do not float the SPI configuration pins (CSB, SCLK, SDIO) - they must be tied to defined logic levels (CSB high by default) to avoid accidental reconfiguration. The DFS pin must be set before power-up or reset, and the mode change should be followed by a SPI register write to confirm. The input PGA has a maximum input range that, if exceeded, will cause saturation; verify your input scaling with the SPI register map. When switching between CMOS and LVDS DDR modes, allow at least 1 ms of settling time before capturing valid data.
コンプライアンス情報
RoHS compliant per Renesas product page. Industrial temperature grade -40 C to +85 C. Not AEC-Q100 qualified; for automotive applications consult Renesas for the AEC-Q100 grade equivalent.
