ADC1112D125HN-C18 - Dual 11-bit 125MSPS ADC, LVDS/CMOS | Renesas
部品番号: ADC1112D125HN-C18 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $14.85 | $14.85 |
| 10 | $13.4 | $134.00 |
| 100 | $11.92 | $1,192.00 |
| 500 | $10.65 | $5,325.00 |
| 1,000 | $9.48 | $9,480.00 |
ADC1112D125HN-C18 概要
An ADC (Analog-to-Digital Converter) is a data-conversion integrated circuit that samples continuous analog signals and translates them into discrete digital codes for downstream digital signal processing. In the broader semiconductor taxonomy, an ADC belongs to the data-converter IC family, which sits within mixed-signal ICs, which in turn belong to the integrated circuits (semiconductors) category that also includes DACs, amplifiers, and interface ICs. The ADC1112D125 family specifically targets high-IF undersampling, baseband sampling, and multi-channel receiver architectures where dual ADCs share a clock and reference.
Key specifications include 11-bit resolution across two simultaneously sampling channels, 125 Msps maximum sample rate, dual CMOS or LVDS DDR output interface, internal programmable reference (1 dB steps from 0 dB to 6 dB), SPI control for mode configuration, and a per-channel independent power-down capability. The separate digital I/O supply rail (OVDD) lets the part drive 1.8 V FPGAs directly without level shifters, reducing BOM and board area in modern SoC designs.
Architecturally, the ADC1112D125 uses a pipelined multi-stage switched-capacitor core combined with on-chip reference buffering, calibrated offset and gain correction, and output error-correction logic. A programmable full-scale range (FSR) via INTREF[2:0] in 1 dB steps allows trade-off between SNR and input drive level. The LVDS DDR mode outputs data on both clock edges and supports a 7-bit DDR LVDS bus per channel, easing routing into FPGA/ASIC deserialization FIFOs.
Typical applications include multi-carrier LTE/3G base-station receivers, medical imaging and ultrasound front-ends, portable instrumentation, low-cost digital oscilloscopes, and dual-antenna diversity radar digitizers. Designers benefit from matched-channel sampling when calibrating I/Q imbalance in direct-conversion radios.
When designing with this device, place the analog input RC network close to each input pin, route AVDD and OVDD independently with ferrite-bead isolation, and provide solid ground planes under the exposed thermal pad. The SPI port must be pulled high during normal operation in hardware-mode defaults. Compared with discrete ADC + FPGA receiver designs, the ADC1112D125 saves board area, lowers power, and reduces FPGA pin count on the data bus.
ドロップイン代替品: ADC1112D125HN-C18 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC1112D125HN-C18 （同一形状・フットプリント） — 相違点: Package, Input Type, Resolution, Number of Channels, Digital Output Interface.
クイック比較ツール — 並列比較する代替部品を選択:
ADC1112D125HN/C1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1112D125HN/C1:5
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1015S125HN/C1
✅ ドロップイン✓ 在庫あり
$10.4 / 個
データシートを見る →ADC1012D080HN/C1:5
✅ ドロップイン✓ 在庫あり
$12.1 / 個
データシートを見る →ADC1010S125HN/C1:5
✅ ドロップイン✓ 在庫あり
$22.1 / 個
データシートを見る →ADC1112D125HN-C18 最大定格＆電気的特性
| 分解能 | 11-bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate (Max) | 125 Msps |
| Analog Supply Voltage (AVDD) | 3.0 V to 3.6 V |
| Digital I/O Supply (OVDD) | 1.8 V to 3.3 V |
| Output Interface | CMOS or LVDS DDR (selectable) |
| Input Type | Single-ended analog inputs (per channel) |
| Reference | Internal programmable (0-6 dB in 1 dB steps) or external |
| Control Interface | SPI (3-wire, mode configuration) |
| Power-Down Mode | Yes, per-channel via SPI |
| パッケージ | HVQFN-64 (8x8 mm with exposed thermal pad) |
| 実装タイプ | Surface Mount |
| 動作温度範囲 | -40 C to +85 C |
| MSLレベル | 3 (168 hours) |
| RoHS ステータス | Compliant |
ADC1112D125HN-C18 ピン構成
| ピン 1 | AINP1A — Channel 1A positive analog input |
| ピン 2 | AINM1A — Channel 1A negative analog input (complement to AINP1A) |
| ピン 3 | VREF — Reference voltage decoupling (external bypass) |
| ピン 4 | SENSE — Reference sense / mode select input |
| ピン 5 | GND — Ground return |
| ピン 6 | AVDD — Analog supply (3.0-3.6 V) |
| ピン 7 | AVDD — Analog supply (3.0-3.6 V) |
| ピン 8 | GND — Ground return |
| ピン 9 | AINP1B — Channel 1B positive analog input |
| ピン 10 | AINM1B — Channel 1B negative analog input (complement) |
| ピン 11 | GND — Ground return |
| ピン 12 | AVDD — Analog supply (3.0-3.6 V) |
| ピン 13 | CLKP1 — Channel 1 clock input positive |
| ピン 14 | CLKM1 — Channel 1 clock input negative (if differential; tied to GND if single-ended) |
| ピン 15 | OVDD — Output supply (1.8 V - 3.3 V) |
| ピン 16 | OGND — Output ground return |
| ピン 17 | D0_1 — Channel 1 CMOS data bit 0 (or LVDS pair) |
| ピン 18 | D1_1 — Channel 1 CMOS data bit 1 (or LVDS pair) |
| ピン 19 | D2_1 — Channel 1 CMOS data bit 2 |
| ピン 20 | D3_1 — Channel 1 CMOS data bit 3 |
| ピン 21 | D4_1 — Channel 1 CMOS data bit 4 |
| ピン 22 | D5_1 — Channel 1 CMOS data bit 5 |
| ピン 23 | D6_1 — Channel 1 CMOS data bit 6 / LVDS output enable |
| ピン 24 | D7_1 — Channel 1 CMOS data bit 7 / OTR out-of-range |
| ピン 25 | DRDY_1 — Channel 1 data ready output |
| ピン 26 | OVDD — Output supply (1.8 V - 3.3 V) |
| ピン 27 | OGND — Output ground return |
| ピン 28 | CS — SPI chip select (active low) |
| ピン 29 | SCLK — SPI serial clock |
| ピン 30 | SDIO — SPI serial data I/O |
| ピン 31 | SDO — SPI serial data out (read mode) |
| ピン 32 | RESET — Hardware reset (active low) |
| ピン 33 | PD — Power-down mode control |
| ピン 34 | MODE — Output interface select (CMOS or LVDS) |
| ピン 35 | OVDD — Output supply (1.8 V - 3.3 V) |
| ピン 36 | OGND — Output ground return |
| ピン 37 | D0_2 — Channel 2 CMOS data bit 0 |
| ピン 38 | D1_2 — Channel 2 CMOS data bit 1 |
| ピン 39 | D2_2 — Channel 2 CMOS data bit 2 |
| ピン 40 | D3_2 — Channel 2 CMOS data bit 3 |
| ピン 41 | D4_2 — Channel 2 CMOS data bit 4 |
| ピン 42 | D5_2 — Channel 2 CMOS data bit 5 |
| ピン 43 | D6_2 — Channel 2 CMOS data bit 6 |
| ピン 44 | D7_2 — Channel 2 CMOS data bit 7 |
| ピン 45 | DRDY_2 — Channel 2 data ready output |
| ピン 46 | OGND — Output ground return |
| ピン 47 | OVDD — Output supply (1.8 V - 3.3 V) |
| ピン 48 | OGND — Output ground return |
| ピン 49 | AVDD — Analog supply (3.0-3.6 V) |
| ピン 50 | GND — Ground return |
| ピン 51 | AINP2B — Channel 2B positive analog input |
| ピン 52 | AINM2B — Channel 2B negative analog input (complement) |
| ピン 53 | AVDD — Analog supply (3.0-3.6 V) |
| ピン 54 | GND — Ground return |
| ピン 55 | AINP2A — Channel 2A positive analog input |
| ピン 56 | AINM2A — Channel 2A negative analog input (complement) |
| ピン 57 | GND — Ground return |
| ピン 58 | AVDD — Analog supply (3.0-3.6 V) |
| ピン 59 | CLKP2 — Channel 2 clock input positive |
| ピン 60 | CLKM2 — Channel 2 clock input negative |
| ピン 61 | VCM — Common-mode voltage output (for DC-coupled driving) |
| ピン 62 | VREF — Reference voltage decoupling |
| ピン 63 | AVDD — Analog supply (3.0-3.6 V) |
| ピン 64 | GND — Ground return |
主な用途
ADC1112D125HN-C18 の用途: 6 件s: Multi-Carrier LTE / 3G Base-Station Receiver, Medical Ultrasound and Imaging Front-End, Digital Oscilloscope and Test Instrumentation, Dual-Antenna Diversity Radar Digitizer, Software Defined Radio (SDR) Receiver IF Stage, Industrial Process Control Data Acquisition.
Multi-Carrier LTE / 3G Base-Station Receiver
The ADC1112D125HN-C18's dual simultaneously sampling 11-bit channels at 125 Msps make it ideal for direct-IF sampling in multi-carrier LTE and 3G base-station receivers. The LVDS DDR output mode delivers 250 Mbps per channel into a SerDes or FPGA, preserving dynamic range across the IF spectrum while the programmable internal reference (0-6 dB in 1 dB steps) lets the receiver engineer optimize SNR-vs-headroom for the specific band plan. With separate AVDD and OVDD rails, the part can drive a 1.8 V FPGA directly without level shifters, reducing BOM and board area. Power consumption near 350 mW per channel is well below competing dual 125 Msps parts, easing thermal management in sealed radio units.
おすすめ
Medical Ultrasound and Imaging Front-End
In portable ultrasound and other medical imaging front-ends, the ADC1112D125HN-C18 provides matched-channel dual sampling essential for coherent beamforming across transducer arrays. Its low-power 3 V analog operation is well-suited to battery-powered cart-based and handheld ultrasound systems where thermal budget is constrained. The 11-bit resolution and wide analog input bandwidth support typical IF ranges of 5-65 MHz found in clinical ultrasound, and the per-channel power-down capability lets designers shut down inactive channels during low-acquisition phases to extend battery life. The HVQFN-64 package with exposed pad provides a low-profile footprint for compact probe and cart designs.
おすすめ
Digital Oscilloscope and Test Instrumentation
The ADC1112D125HN-C18 fits cost-sensitive low-bandwidth oscilloscope channels (up to 50 MHz useful analog input bandwidth) and modular data-acquisition front-ends. The dual-channel architecture lets two scope channels share one ADC chip, saving PCB area and easing channel-to-channel timing calibration. Its selectable CMOS or LVDS DDR output modes give the designer flexibility to route to an FPGA deserializer or directly to a microcontroller in low-cost variants. Internal reference adjustment via SPI also enables per-channel gain calibration during production test, improving unit-to-unit consistency in mid-tier instrumentation.
おすすめ
Dual-Antenna Diversity Radar Digitizer
For dual-antenna diversity or interferometric radar digitizers in short-range industrial and automotive surround-sensing applications, the ADC1112D125HN-C18's simultaneous dual sampling preserves inter-channel phase coherence essential for direction-of-arrival estimation. The LVDS DDR interface simplifies data transport over board traces to a companion FPGA, while per-channel independent power-down enables duty-cycling between radar bursts to conserve power in battery-fed nodes. The 64-pin HVQFN package offers the mechanical robustness required for chassis-mounted radar PCBs that may experience vibration.
おすすめ
Software Defined Radio (SDR) Receiver IF Stage
The ADC1112D125HN-C18 is well suited to SDR receiver IF stages that digitize 0-65 MHz signals for digital demodulation in a host FPGA. The selectable CMOS or LVDS DDR output gives flexibility for routing to either an FPGA or an MCU+ASIC front-end. At 11-bit resolution and 125 Msps sample rate, the part supports sufficient dynamic range for narrow-band signals (FM, DAB, DVB-T, DMR, P25) without aliasing, and the SPI-controlled gain adjustment (via the INTREF[2:0] bits) simplifies AGC implementation in adaptive front-end designs.
おすすめ
Industrial Process Control Data Acquisition
In multi-channel industrial data-acquisition modules - for example, multi-loop PID controllers, vibration monitoring systems, or power-quality analyzers - the ADC1112D125HN-C18's dual 11-bit channels enable compact front-end designs that digitize two sensor signals simultaneously per IC. The programmable internal reference simplifies the analog front-end chain (no external reference required for many designs), and the per-channel power-down mode allows duty-cycling of idle channels to reduce total system power in thermally constrained environments. The HVQFN-64 footprint and industrial -40 C to +85 C temperature range support factory-floor deployments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC1112D125HN-C18 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC1112D125HN/C1 | ADC1015S125HN/C1 | ADC1012D080HN/C1:5 | ADC1010S125HN/C1:5 |
|---|---|---|---|---|---|
| Brand | Renesas Electronics (formerly IDT) | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | HVQFN-64 | HVQFN-64 - same | HVQFN-64 - same | HVQFN-64 - same | HVQFN-64 - same |
| Resolution | 11-bit | 11-bit | 10-bit | 10-bit | 10-bit |
| Number of Channels | 2 (dual, simultaneous) | 2 (dual) | 1 (single) | 2 (dual) | 1 (single) |
| Sample Rate (Max) | 125 Msps | 125 Msps | 125 Msps | 80 Msps | 125 Msps |
| Output Interface | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR |
| Analog Supply (AVDD) | 3.0 - 3.6 V | 3.0 - 3.6 V | 3.0 - 3.6 V | 3.0 - 3.6 V | 3.0 - 3.6 V |
| Reel / Orientation | C18 | C1 | C1 | C1:5 | C1:5 |
主な差別化要因
- True simultaneous sampling on dual channels preserves inter-channel phase for I/Q and diversity receivers （vs ADC1015S125HN/C1)
- Higher dynamic range at 11-bit resolution vs 10-bit alternatives （vs ADC1010S125HN/C1:5)
- Selectable CMOS or LVDS DDR output flexibility on a single chip （vs ADC1175-50CILQ/NOPB)
- Programmable internal reference (0-6 dB in 1 dB steps) eliminates external reference IC for many designs （vs External reference design (costing $1.50+ at qty 1000))
設計ノート
Use a solid ground plane directly under the HVQFN-64 exposed thermal pad (EP) and stitch with multiple vias to a lower analog ground layer. Place input RC networks (typically 50 ohm series with 2 pF shunt to each AINP/AINM) within 5 mm of the analog input pins to limit common-mode kickback. Keep AVDD and OVDD rails decoupled with 100 nF + 10 uF ceramic capacitor pairs adjacent to each supply pin, separated by ferrite beads to prevent digital switching noise from coupling into the analog front-end.
Route the LVDS DDR output pairs (D0_1..D7_1, D0_2..D7_2) as tightly coupled 100 ohm differential microstrip on the top layer with continuous reference ground beneath, using matched trace lengths (within 150 mil) between pairs. Maintain a 3W spacing between adjacent LVDS pairs to reduce crosstalk at 250 Mbps data rates. Keep these traces short and route directly to the FPGA deserialization bank to avoid reflections.
Do not exceed 3.6 V on AVDD or 3.3 V on OVDD - the part is not 5 V tolerant on any pin. Always pull the SPI CS pin high between transactions; leaving CS floating can allow spurious SPI clocking that disrupts the internal mode settings. The MODE pin (CMOS/LVDS select) must be tied to a valid logic level before /RESET deasserts, otherwise the outputs may drive into an undefined state. Refer to the Renesas datasheet Rev. 03, July 2012, section 6 for the complete pinout and recommended operating conditions.
Estimated: at 3.3 V AVDD + 3.3 V OVDD with both channels active and 125 Msps clock, the ADC1112D125HN-C18 consumes approximately 700 mW. With the HVQFN-64 thermal resistance (theta_JA) of approximately 30 C/W on a 4-layer JEDEC test board, the junction temperature rise is about 21 C above 25 C ambient, leaving substantial headroom up to the +85 C industrial spec. Improve thermal coupling by maximizing copper area on the EP and connecting to an internal ground plane with at least 25 thermal vias.
コンプライアンス情報
Per Renesas product page (https://www.renesas.com/en/products/adc1112d125hn/part-details/adc1112d125hn-c18), the part is RoHS compliant and lead-free. Industrial-grade (-40 C to +85 C) only; no AEC-Q100 automotive version is offered for this MPN.
