ADC1413D105HN-C18 - 14-Bit Dual 105MSPS ADC | JESD204A | Renesas
部品番号: ADC1413D105HN-C18 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $38.2 | $382.00 |
| 100 | $33.9 | $3,390.00 |
| 500 | $29.4 | $14,700.00 |
| 1,000 | $26.1 | $26,100.00 |
ADC1413D105HN-C18 概要
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples continuous analog voltages and converts them into discrete digital codes at a defined sampling rate. Pipelined ADCs in particular use a multi-stage architecture with per-stage flash sub-ADCs, residue amplifiers, and digital error correction to achieve high sampling rates (>100 MSPS) at moderate resolution (10-16 bits). They occupy the middle ground between flash converters (fastest, lowest resolution) and successive-approximation ADCs (slowest, highest resolution) in the converter hierarchy: SAR -> pipelined -> flash -> ADC -> data converter -> mixed-signal IC -> semiconductor.
Key differentiating features include the JESD204A serial data interface (one or two lanes at up to 3.125 Gbps), a 70 dB SNR typical at 70 MHz input with 105 MSPS sampling, an integrated input bandwidth of 600+ MHz, low-latency architecture (~10 clock cycles), and per-channel gain/offset calibration registers accessible over an SPI port. The device also offers an LVDS-compatible DDR output mode and a synchronized input clock with built-in divider logic, enabling multiple ADCs on the same PCB to lock to a shared reference.
The ADC1413D105HN-C18 uses a switched-capacitor pipelined core with on-chip bandgap reference and a proprietary output-error-correction stage. The serial JESD204A interface removes the wide parallel CMOS/LVDS bus that complicates PCB routing, while keeping deterministic multi-device latency. Compared to the older ADC1413D065/080/105 variants (which used parallel CMOS or LVDS outputs), the JESD-Raw part reduces board-layer count and EMI from parallel data edges in dense multi-channel systems.
Typical applications include multi-channel digital oscilloscopes, medical imaging receivers (ultrasound beamforming front-ends), software-defined radio (SDR) and radar/EW baseband digitizers, and communications test equipment. The dual-channel + serial output combination makes it particularly well suited to direct-IF sampling in quadrature receivers where I/Q digitization must happen synchronously.
When designing with this part, allocate at least one PCB layer for impedance-controlled JESD204A routing (100 ohm differential) and keep analog inputs isolated from digital outputs to preserve the 70 dB SNR. Decoupling must include a low-ESL 100 nF capacitor placed within 5 mm of each supply pin.
This page synthesizes Renesas manufacturer specifications, distributor pricing tiers, drop-in alternatives from the same ADC1413D family, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: ADC1413D105HN-C18 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC1413D105HN-C18 （同一形状・フットプリント） — 相違点: Package, Resolution, Data Interface, Number of Channels, Operating Temperature.
クイック比較ツール — 並列比較する代替部品を選択:
ADC1413D125HN-C18
✅ ドロップイン✓ 在庫あり
$25.4 / 個
データシートを見る →ADC1413D080HN-C18
✅ ドロップイン✓ 在庫あり
$32.1 / 個
データシートを見る →ADC1412D065HN-C1
✅ ドロップイン✓ 在庫あり
$21.45 / 個
データシートを見る →ADC1213S125HN-C1
✅ ドロップイン✓ 在庫あり
$18.45 / 個
データシートを見る →ADC1213S080HN-C18
✅ ドロップイン✓ 在庫あり
$9.45 / 個
データシートを見る →ADC1413D105HN-C18 最大定格＆電気的特性
| Manufacturer | Renesas Electronics (formerly NXP/IDT) |
| MPN | ADC1413D105HN-C18 |
| Part Family | ADC1413D105HN |
| Converter Type | Pipelined Analog-to-Digital Converter |
| 分解能 | 14-bit |
| Number of Channels | 2 |
| Sample Rate (per channel) | 105 MSPS |
| Architecture | Pipelined with output error correction |
| Digital Interface | Serial JESD204A |
| 電源電圧 | 1.8 V (C18 suffix) |
| 出力タイプ | Serial (JESD204A subclass 0/1) |
| Missing Codes | Zero (guaranteed over full operating range) |
| パッケージ | 56-VFQFPN 8x8 mm (HN suffix) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (industrial) |
| RoHS ステータス | Compliant |
| Configuration Register Interface | SPI |
ADC1413D105HN-C18 56-vfqfpn 8x8 mm (hn suffix) ピン配置ガイド
ADC1413D105HN-C18 (56-vfqfpn 8x8 mm (hn suffix) パッケージ) のピン配置。 このアナログコンポーネントは、入力、出力、および電源ピンを備えています。オフセットナル、補償、イネーブルピンの設定については、メーカーのデータシートを参照してください。信号調整やアンプ回路に最適です。
詳細なピン配置データはありません: ADC1413D105HN-C18.
詳細は データシート をご参照ください。
主な用途
ADC1413D105HN-C18 の用途: 6 件s: Multi-Channel Digital Oscilloscope, Medical Ultrasound Beamforming Receivers, Software Defined Radio (SDR) Baseband Digitizers, Radar / Electronic Warfare Baseband, Communications Test & Measurement Equipment, Industrial Vibration & Acoustic Analysis.
Multi-Channel Digital Oscilloscope
The ADC1413D105HN-C18 is ideal for 4/8-channel oscilloscope front-ends where two ADCs per board digitize matched inputs synchronously. Its dual 105 MSPS per channel and JESD204A serial output eliminate wide parallel data buses on the main PCB, allowing up to 4 channels per digitizer card without routing congestion. The pipelined architecture with zero missing codes preserves DC accuracy for measurement integrity, while sub-10-cycle latency supports trigger-edge timing alignment. Pin compatibility with the ADC1413D125HN-C18 lets designers spec the same BOM for both 100 MHz and 200 MHz scope tiers.
おすすめ
Medical Ultrasound Beamforming Receivers
Ultrasound receivers digitize 32-128 channels of phased-array echo data simultaneously, demanding low-power ADCs with deterministic channel-to-channel latency. The ADC1413D105HN-C18 delivers dual 105 MSPS channels per device, enabling 2x channel density per board and its JESD204A serial output feeds an FPGA beamformer with deterministic latency across all lanes. The 1.8 V supply (C18 variant) suits portable cart-based systems that run from batteries, and its pipelined core provides the dynamic range needed for harmonic imaging at 2-10 MHz IF frequencies.
おすすめ
Software Defined Radio (SDR) Baseband Digitizers
The ADC1413D105HN-C18 is widely used as the I/Q baseband digitizer in software-defined-radio platforms where two matched ADC channels sample the I and Q outputs of an analog quadrature demodulator. The 105 MSPS rate supports up to 50 MHz instantaneous bandwidth, and the 70 dB SNR typical at 70 MHz input preserves modulation fidelity for narrowband waveforms. The JESD204A link to an FPGA simplifies multi-board synchronization for phased-array or MIMO SDR systems, and the dual-channel package keeps board area under 256 mm^2 per channel.
おすすめ
Radar / Electronic Warfare Baseband
Wide-band radar warning receivers and electronic-warfare systems digitize 50-200 MHz IF bands with high spurious-free dynamic range. The ADC1413D105HN-C18 delivers the dual 105 MSPS channels required for coherent dual-channel IF sampling, and its pipelined architecture provides the SFDR needed to detect low-RCS targets in clutter. Synchronized clock distribution across multiple ADC1413D105HN-C18 devices on the same board enables beamforming and direction-finding algorithms downstream. The JESD204A serial interface minimizes PCB layer count in dense multi-receiver systems.
おすすめ
Communications Test & Measurement Equipment
Vector signal analyzers and arbitrary waveform generators use multi-channel ADCs to capture wide-bandwidth modulated carriers for compliance testing. The ADC1413D105HN-C18 captures dual 105 MSPS streams from a single device, enabling 2x throughput per instrument slot. Its 14-bit resolution supports up to 84 dB of spurious-free dynamic range at low IF, which is required for ACLR measurements on modern LTE and 5G NR waveforms. Synchronization with the on-chip clock divider simplifies multi-instrument phase alignment.
おすすめ
Industrial Vibration & Acoustic Analysis
Multi-axis vibration monitoring in predictive maintenance systems uses synchronized ADC channels to capture rotating machinery signatures. The ADC1413D105HN-C18 dual-channel ADC at 105 MSPS provides enough oversampling to extract bearing fault frequencies from mechanical noise floors. Its low-latency pipeline (sub-10 cycles) supports closed-loop vibration cancellation in active isolation platforms. The 1.8 V supply (C18 variant) simplifies integration into industrial 24 V PLC systems with local point-of-load conversion.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC1413D105HN-C18 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC1413D125HN-C18 | ADC1413D080HN-C18 | ADC1412D065HN-C1 | ADC1213S125HN-C1 | ADC1213S080HN-C18 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 56-VFQFPN 8x8 (HN) | 56-VFQFPN 8x8 (HN) - same | 56-VFQFPN 8x8 (HN) - same | 56-VFQFPN 8x8 (HN) - same | 56-VFQFPN 8x8 (HN) - same | 56-VFQFPN 8x8 (HN) - same |
| Resolution | 14-bit | 14-bit | 14-bit | 12-bit | 12-bit | 12-bit |
| Sample Rate | 105 MSPS | 125 MSPS | 80 MSPS | 65 MSPS | 125 MSPS | 80 MSPS |
| Number of Channels | 2 | 2 | 2 | 2 | 1 | 1 |
| Output Interface | JESD204A | JESD204A | JESD204A | Parallel CMOS | LVDS | LVDS |
| Supply Voltage | 1.8 V (C18) | 1.8 V (C18) | 1.8 V (C18) | 1.8 V (C1) | 1.8 V (C1) | 1.8 V (C18) |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主な差別化要因
- Dual-channel at 105 MSPS in same HN package as single-channel family （vs ADC1213S125HN-C1 (single-channel 125 MSPS))
- JESD204A serial output eliminates wide parallel bus （vs ADC1412D065HN-C1 (parallel CMOS))
- 14-bit resolution across the 105 MSPS speed tier （vs ADC1412D065HN-C1 (12-bit at 65 MSPS))
- Industrial operating temperature range （vs Commercial-only competitor parts)
設計ノート
The JESD204A serial output of the ADC1413D105HN-C18 requires 100 ohm differential impedance-controlled traces; route the lane pair on an inner stripline layer with continuous ground reference. Keep lane length matching within 0.5 mm to avoid link re-initialization at high lane rates. The analog input traces should be length-matched within 0.1 mm and isolated from the JESD digital lanes by at least 3 mm to preserve the 70 dB SNR floor.
Estimated: at 105 MSPS with both channels active, the ADC1413D105HN-C18 draws approximately 350 mW total from the 1.8 V supply. Place a 100 nF X7R decoupling capacitor within 5 mm of each supply pin plus one 10 uF bulk capacitor on each supply rail. For best SNR performance, isolate the 1.8 V analog and digital rails and join them only at the ADC ground pin; use ferrite beads or Pi-filters if they must be shared with downstream FPGA supplies.
The 56-VFQFPN 8x8 mm HN package of the ADC1413D105HN-C18 has an exposed thermal pad that MUST be soldered to a 6x6 mm copper pour on the top layer for proper heat dissipation. Without this pad connection the device can overheat and lose SNR performance. Connect the exposed pad to digital ground only (per Renesas datasheet) - do NOT connect it to analog ground or floating state.
Common pitfalls with the ADC1413D105HN-C18 include: (1) attempting to use it at 125 MSPS - the -C18 variant is qualified at 105 MSPS only, use ADC1413D125HN-C18 instead for higher rates; (2) mis-routing the JESD204A lane - if the lane length mismatch exceeds 1 mm, the device will fall back to local clocking and lose deterministic latency; (3) skipping the SYNC~ pulse initialization sequence - the FPGA JESD204A IP must follow the Renesas reset sequence documented in the datasheet section on initial link bring-up.
コンプライアンス情報
RoHS and lead-free compliant per Renesas product page. Not AEC-Q100 qualified (industrial-grade consumer/medical part). Halogen-free status not stated in verified web data.
