ADS131E08SPAGR - 8-Ch 24-Bit 64-kSPS Delta-Sigma ADC | TI
部品番号: ADS131E08SPAGR ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.3 | $113.00 |
| 100 | $10.1 | $1,010.00 |
| 500 | $9.2 | $4,600.00 |
| 1,000 | $8.4 | $8,400.00 |
ADS131E08SPAGR 概要
An analog front-end (AFE) is a circuit block that conditions and digitizes analog signals before digital processing. Within the signal-chain hierarchy (delta-sigma ADC -> analog front-end -> data acquisition system -> signal chain), the ADS131E08S is a complete AFE that integrates eight delta-sigma converters, programmable gain amplifiers (PGAs), an internal voltage reference, and an internal oscillator in a single IC, drastically reducing the component count of multi-channel data acquisition systems.
Key features include 24-bit resolution across eight simultaneous channels, a 64 kSPS maximum sample rate, differential or pseudo-differential inputs, an SPI serial interface, and a fast power-up/start-up time. Simultaneous sampling is essential for power monitoring because phase relationships between voltage and current channels must be preserved for accurate power calculations.
Architecturally, each channel uses a delta-sigma modulator with an internal digital decimation filter, providing noise shaping and high resolution at moderate bandwidth. The fast start-up specification enables quick power-on to valid conversion data, which is critical for protection relays that must detect and respond to faults within milliseconds. The integrated PGA allows direct connection of sensors with varying output levels without external amplification.
Typical applications include grid protection relays, power quality analyzers, energy metering, and industrial motor monitoring, where eight synchronized channels capture three-phase voltage and current waveforms. The 1.8V digital / 5V analog supply configuration fits standard industrial rails.
Design consideration: decouple the analog and digital supplies independently and maintain a single, quiet ground plane; isolate the SPI bus when it crosses to noisy digital domains to preserve the specified noise floor. Price data as of 2026-08-30.
ドロップイン代替品: ADS131E08SPAGR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
ADS131E08IPAGR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS131E06SPAGR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS131E04SPAGR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS131E08SPAGR 最大定格＆電気的特性
| 分解能 | 24 bit |
| チャネル数 | 8 (simultaneous sampling) |
| Maximum Sample Rate | 64 kSPS |
| ADC Architecture | Delta-Sigma |
| Analog Supply Voltage | 5 V |
| Digital Supply Voltage | 1.8 V |
| Power Consumption | 17.6 mW |
| Input Type | Differential / Pseudo-Differential |
| PGA | Integrated programmable gain amplifier |
| Internal Reference | Yes |
| インターフェース | SPI |
| Start-Up | Fast power-up time |
| 動作温度 | -40C to +105C |
| パッケージ | 64-TQFP (PAG), 10x10 mm |
| 実装タイプ | Surface Mount |
| Application | Monitoring and protection (power monitoring) |
ADS131E08SPAGR ピン構成
| ピン 1 | CH0_INP — Channel 0 differential positive input [DATA_NEEDED: confirm exact pin assignment] |
| ピン [DATA_NEEDED] | CH0_INN — Channel 0 differential negative input |
| ピン [DATA_NEEDED] | AVDD — 5V analog supply |
| ピン [DATA_NEEDED] | DVDD — 1.8V digital supply |
| ピン [DATA_NEEDED] | AVSS — Analog ground / negative supply |
| ピン [DATA_NEEDED] | DGND — Digital ground |
| ピン [DATA_NEEDED] | SCLK — SPI serial clock input |
| ピン [DATA_NEEDED] | DIN — SPI data input |
| ピン [DATA_NEEDED] | DOUT — SPI data output |
| ピン [DATA_NEEDED] | DRDY — Data ready indicator |
| ピン [DATA_NEEDED] | CS — SPI chip select |
| ピン [DATA_NEEDED] | VREF — Reference voltage / internal reference output |
主な用途
ADS131E08SPAGR の用途: 6 件s: Grid Protection Relays, Power Quality Analyzers, Energy Metering, Industrial Motor Monitoring, Multi-Channel Data Acquisition (DAQ), Battery Management System Sensing.
Grid Protection Relays
Protection relays must detect overcurrent, overvoltage, and frequency events within milliseconds. The ADS131E08SPAGR fits because its fast start-up delivers valid conversion data quickly after power-up, and its eight simultaneous 24-bit channels preserve phase alignment between current and voltage inputs - mandatory for impedance and direction calculations. Sampling at 64 kSPS gives ample oversampling for 50/60 Hz fundamental extraction plus harmonics. The integrated PGA allows direct CT/PT input conditioning without external amplifiers, reducing board area and calibration effort.
おすすめ
Power Quality Analyzers
Power quality instruments capture voltage and current waveforms on all phases simultaneously to compute THD, sags, swells, and unbalance. The ADS131E08SPAGR's eight simultaneous channels cover three phases plus neutral voltage and current in one device, while the 24-bit resolution and 64-kSPS rate support harmonic analysis up to the 63rd order. Its 17.6 mW consumption suits portable analyzers, and the internal reference keeps channel-to-channel gain matching tight for accurate per-phase power and energy computations.
おすすめ
Energy Metering
Three-phase smart meters require synchronized sampling of phase voltages and currents for accurate active and reactive energy calculation. The ADS131E08SPAGR provides phase-coherent 24-bit data that eliminates skew errors inherent in multiplexed ADCs, supporting metering-class accuracy. The 5V/1.8V supply scheme matches industrial meter power rails, and the integrated reference reduces the calibration burden across the eight channels. Low 17.6 mW power draw helps meet idle-consumption regulations in always-on meters.
おすすめ
Industrial Motor Monitoring
Condition monitoring of industrial motors digitizes three-phase current and voltage plus vibration and temperature sensor channels. The ADS131E08SPAGR's simultaneous sampling correlates electrical signatures (for MCSA analysis) with mechanical sensor data, and the PGA accommodates sensors with different output amplitudes without external gain stages. Its 64-kSPS rate captures both fundamental components and higher-frequency fault signatures, while SPI output integrates directly with factory automation controllers.
おすすめ
Multi-Channel Data Acquisition (DAQ)
Industrial DAQ systems benefit from the ADS131E08SPAGR's integration: eight 24-bit delta-sigma converters, PGAs, reference, and oscillator in one 10x10 mm TQFP replaces dozens of discrete components. Simultaneous sampling avoids the inter-channel skew of multiplexed front ends, important when correlating channels in time. The SPI interface with DRDY handshake simplifies firmware, and the fast start-up supports duty-cycled acquisition that extends battery life in remote monitoring nodes.
おすすめ
Battery Management System Sensing
BMS applications sense cell voltages and pack current with high resolution for accurate state-of-charge estimation. The ADS131E08SPAGR's 24-bit resolution and integrated PGA allow measurement of small cell voltage differentials, and its low 17.6 mW consumption limits self-discharge impact on monitored packs. Isolation is typically required between the analog front end and system controller - pair with isolated digital isolators on the SPI bus to meet high-voltage stack requirements.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS131E08SPAGR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS131E08IPAGR | ADS131E06SPAGR | ADS131E04SPAGR |
|---|---|---|---|---|
| Package | 64-TQFP (PAG) 10x10 mm | 64-TQFP (PAG) - same | 64-TQFP (PAG) - same | 64-TQFP (PAG) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 24 bit | 24 bit | 24 bit | 24 bit |
| Channels | 8 simultaneous | 8 simultaneous | 6 simultaneous | 4 simultaneous |
| Max Sample Rate | 64 kSPS | 64 kSPS | 64 kSPS | 64 kSPS |
| Integrated PGA | Yes | Yes | Yes | Yes |
| Interface | SPI | SPI | SPI | SPI |
主な差別化要因
- Full 8 simultaneous channels in one AFE （vs ADS131E06SPAGR)
- Fast start-up for protection （vs ADS131E08 (non-S))
- Integrated PGA and reference （vs ADS131E04SPAGR)
設計ノート
Decouple the 5V analog and 1.8V digital supplies independently with 100 nF ceramic capacitors placed within 2 mm of each supply pin, plus bulk 10 uF capacitance per rail. Maintain a single, unbroken ground plane; do not split analog and digital grounds under the ADC. Route differential input pairs as matched-length traces away from the SPI clock to preserve the 24-bit noise floor.
The SPI bus crossing from a noisy digital domain can inject errors into conversion data. Use digital isolators (e.g., ISO77xx family) when the host MCU shares a different ground domain, and add series termination (22-33 ohm) on SCLK to control ringing. Keep DRDY lines short and monitor timing against the datasheet SPI frame requirements.
Do not exceed the datasheet absolute maximum ratings on the analog inputs - the integrated PGA front end is sensitive to overvoltage; add external clamping for field-wired protection-relay inputs. Verify the start-up sequence requirements in the datasheet register map before assuming default configurations, and allow the internal reference to settle before the first conversions are trusted.
コンプライアンス情報
Compliance data not present in provided web data; confirm RoHS/REACH status on TI product page.
