ADS8371IPFBRG4 - 16-Bit 750kHz SAR ADC | Texas Instruments
部品番号: ADS8371IPFBRG4 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.92 | $5,960.00 |
| 1,000 | $10.5 | $10,500.00 |
ADS8371IPFBRG4 概要
A SAR ADC is a type of analog-to-digital converter that uses a binary-search successive-approximation algorithm and a capacitive charge-redistribution digital-to-analog converter to digitize a sampled input voltage in N conversion clock cycles. SAR ADCs sit in the broader category of data-converter ICs (ADC subfamily) alongside delta-sigma, pipeline, and flash architectures. They are favored for applications requiring deterministic latency, low power, and high accuracy at moderate sample rates, making them a workhorse for industrial automation, multi-channel data acquisition systems, and precision instrumentation.
Key features of the ADS8371 include 750 kHz maximum sample rate, 16-bit no-missing-codes performance, a true 16-bit parallel interface (or 8-bit bus option over three read cycles), low power dissipation, and 0 V to 5 V or 0 V to 10 V unipolar analog input ranges when paired with an external front-end. The device supports hardware configuration of input range and output format via dedicated control pins, simplifying host MCU/DSP interface. The wide -40 °C to +85 °C industrial operating range and 48-lead TQFP (PFB) 7x7 mm package make it suitable for board-level industrial designs where thermal headroom and footprint density matter.
Typical applications include multi-axis industrial process control, motor-control feedback loops, sonar and acoustic imaging front-ends, optical networking instrumentation, and medical patient-monitoring equipment. The combination of throughput and low power also suits portable or battery-backed test equipment. When designing with the ADS8371, ensure analog inputs are buffered with a low-impedance driver to settle within the acquisition window, and follow recommended layout practices for the reference and power decoupling pins to preserve 16-bit linearity.
ドロップイン代替品: ADS8371IPFBRG4 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS8371IPFBRG4 （同一形状・フットプリント） — 相違点: Input Type, Package, Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
ADS8371IPFBT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS8371IPFBTG4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS8371IBPFBT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS8371IBPFBRG4
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS8371IPFB
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS8371IPFBRG4 最大定格＆電気的特性
| 分解能 | 16 bit |
| Sample Rate | 750 kHz |
| Architecture | SAR (Successive Approximation) |
| Number of Channels | 1 |
| Input Type | Unipolar, pseudo-bipolar input |
| Analog Input Range | 0 V to 5 V or 0 V to 10 V (configuration dependent) |
| Digital Interface | Parallel (16-bit wide or 8-bit bus option) |
| 動作温度 | -40 °C to +85 °C (industrial) |
| パッケージ | 48-pin TQFP (PFB) 7x7 mm |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| MSLレベル | 2 (per JEDEC J-STD-020 surface-mount classification) |
ADS8371IPFBRG4 ピン構成
| ピン 1 | AVDD — Analog supply (5 V nominal) |
| ピン 2 | AVSS — Analog ground return |
| ピン 3 | IN+ — Analog positive input |
| ピン 4 | IN- — Analog negative input / signal common |
| ピン 5 | REFIN+ — External reference input positive |
| ピン 6 | REFIN- — External reference input negative |
| ピン 7 | REFGND — Reference ground |
| ピン 8 | CAPP — Reference capacitor pins (CAP logic) |
| ピン 9 | CAPM — Internal DAC capacitor (per datasheet top-decoder) |
| ピン 10 | BYTESEL — Bus width select (high=16-bit, low=8-bit mode) |
| ピン 11 | RESET — Hardware reset input (active low) |
| ピン 12 | RANGE — Input range select (0-5 V or 0-10 V) |
| ピン 13 | CS — Chip select (active low) |
| ピン 14 | RD — Read strobe (active low) |
| ピン 15 | CONVST — Conversion start (active high) |
| ピン 16 | BUSY — Conversion-in-progress indicator |
| ピン 17 | TAG — Tag input (multiplexed mode placeholder) |
| ピン 18 | DVDD — Digital supply (5 V) |
| ピン 19 | DGND — Digital ground |
| ピン 20 | DB15 — Data bit 15 (MSB) |
| ピン 21 | DB14 — Data bit 14 |
| ピン 22 | DB13 — Data bit 13 |
| ピン 23 | DB12 — Data bit 12 |
| ピン 24 | DB11 — Data bit 11 |
| ピン 25 | DB10 — Data bit 10 |
| ピン 26 | DB9 — Data bit 9 |
| ピン 27 | DB8 — Data bit 8 |
| ピン 28 | DB7 — Data bit 7 |
| ピン 29 | DB6 — Data bit 6 |
| ピン 30 | DB5 — Data bit 5 |
| ピン 31 | DB4 — Data bit 4 |
| ピン 32 | DB3 — Data bit 3 |
| ピン 33 | DB2 — Data bit 2 |
| ピン 34 | DB1 — Data bit 1 |
| ピン 35 | DB0 — Data bit 0 (LSB) |
| ピン 36 | DGND — Digital ground |
| ピン 37 | DVDD — Digital supply (5 V) |
| ピン 38 | CLOCKIN — External conversion clock input |
| ピン 39 | NC — Not connected (per datasheet) |
| ピン 40 | NC — Not connected (per datasheet) |
| ピン 41 | NC — Not connected (per datasheet) |
| ピン 42 | NC — Not connected (per datasheet) |
| ピン 43 | MODE — Mode select (hardware strap per datasheet) |
| ピン 44 | ANALOG — Analog auxiliary pin (per datasheet table) |
| ピン 45 | AVSS — Analog ground |
| ピン 46 | AVDD — Analog supply |
| ピン 47 | AVSS — Analog ground |
| ピン 48 | AVDD — Analog supply |
主な用途
ADS8371IPFBRG4 の用途: 6 件s: Multi-Axis Industrial Process Control, Motor Drive Current Feedback Loop, Portable Medical Patient Monitoring, Optical Networking Instrumentation, Sonar / Acoustic Imaging Front-End, Test and Measurement Instrumentation.
Multi-Axis Industrial Process Control
The ADS8371IPFBRG4 fits multi-axis industrial process-control boards where 16-bit resolution and 750 kHz sample rate convert multiple 0-10 V sensor channels per scan. According to TI datasheet specifications, the SAR architecture delivers deterministic conversion latency that simplifies closed-loop PID execution, while the 48-TQFP (PFB) 7x7 mm footprint keeps analog front-end and digital host isolated. Engineers pair the ADC with low-impedance op-amp buffers (e.g., OPA2277) and a reference such as REF5040 to preserve 16-bit linearity across -40 °C to +85 °C operation.
おすすめ
Motor Drive Current Feedback Loop
Direct-axis and quadrature-axis current feedback signals in motor drives need to be digitized quickly and deterministically - exactly the regime the ADS8371IPFBRG4 is built for. At 750 kHz sample rate and 16-bit SAR timing, the ADC and a host DSP can run a 100 kHz+ current loop. Unlike delta-sigma ADCs, the ADS8371 publishes a fresh conversion in a fixed number of clock cycles; the 48-TQFP (PFB) footprint accepts standard optocoupler-isolated drive boards and sits next to TI's C2000 DSP family for compact three-phase drives in industrial servo systems.
おすすめ
Portable Medical Patient Monitoring
Battery-powered patient monitors demand 16-bit precision and low power dissipation; the ADS8371IPFBRG4 supports both with 750 kHz sample rate and a micro-power SAR core. ECG, SpO2, and temperature signal chains convert cleanly with 16-bit no-missing-codes performance, while the 48-TQFP (PFB) 7x7 mm footprint fits compact hand-held form factors. TI's reference designs typically pair the ADC with instrumentation amplifiers (INA128) and a low-power MCU, with the host running continuous sample-rate reduction between heavy processing intervals to extend battery life.
おすすめ
Optical Networking Instrumentation
Optical transceiver modules and line-card test boards demand tight 16-bit acquisition at hundreds of kilohertz for monitoring bias points and signal envelopes. The ADS8371IPFBRG4's 750 kHz sample rate digitizes four to six photodiode channels within a small timeframe. The 48-TQFP (PFB) 7x7 mm package occupies minimal board area, while the parallel interface routes directly to an FPGA, which is the canonical host for line-card data paths. Industrial -40 °C to +85 °C operation tolerates the wide thermal profile of outdoor telecom enclosures.
おすすめ
Sonar / Acoustic Imaging Front-End
Multi-element hydrophone and microphone arrays for sonar and acoustic imaging rely on parallel sampling of 16-bit precision at hundreds of kilohertz per channel. ADS8371IPFBRG4 suits analog-front-end digitization between an array of op-amp chains and an FPGA-based beamformer. The SAR architecture provides deterministic phase across simultaneous-sampled channels that impulsive acoustic threats require, and the 750 kHz sample rate covers the bandwidth of typical active imaging pings before narrowband filtering.
おすすめ
Test and Measurement Instrumentation
Bench-top data acquisition and DMM designs use the ADS8371IPFBRG4 to convert 0-10 V sensor and process-voltage ranges at 750 kHz with 16-bit precision. The parallel interface connects directly to an FPGA or USB-capture bridge, while the 48-TQFP (PFB) package survives repeated assembly rework during prototype iteration. When paired with TI's REF5040 reference and a low-noise front-end op-amp, the ADC delivers the linearity required for laboratory-grade instruments across the full -40 °C to +85 °C industrial range.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS8371IPFBRG4 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS8371IPFBT | ADS8371IPFBTG4 | ADS8371IBPFBT | ADS8371IBPFBRG4 | ADS8371IPFB |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-TQFP (PFB) 7x7 mm | 48-TQFP (PFB) - same | 48-TQFP (PFB) - same | 48-TQFP (PFB) - same | 48-TQFP (PFB) - same | 48-TQFP (PFB) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit (B-grade, tightened linearity) | 16 bit (B-grade) | 16 bit |
| Sample Rate | 750 kHz | 750 kHz | 750 kHz | 750 kHz | 750 kHz | 750 kHz |
| Architecture | SAR | SAR | SAR | SAR | SAR | SAR |
| Input Range | 0-5 V / 0-10 V unipolar | 0-5 V / 0-10 V unipolar | 0-5 V / 0-10 V unipolar | 0-5 V / 0-10 V unipolar | 0-5 V / 0-10 V unipolar | 0-5 V / 0-10 V unipolar |
| Interface | Parallel 16-bit/8-bit | Parallel 16-bit/8-bit | Parallel 16-bit/8-bit | Parallel 16-bit/8-bit | Parallel 16-bit/8-bit | Parallel 16-bit/8-bit |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Lifecycle Status | Obsolete | Active (per TI listing) | Active (per TI listing) | Active (per TI listing) | Obsolete | Obsolete |
主な差別化要因
- Highest-volume TI SAR ADC in the 750 kHz / 16-bit industrial class （vs ADS8371IPFBT)
- B-grade silicon option for tightened linearity （vs ADS8371IBPFBT)
- Parallel interface simplifies FPGA/DSP attachment （vs ADS8343EB/2K5G4)
設計ノート
Estimated: at 750 kHz continuous sample rate the ADS8371 IPFBRG4 draws roughly tens of mW from the AVDD/DVDD 5 V rails according to the device's datasheet power graphs. Place a low-impedance 10 µF tantalum in parallel with a 0.1 µF ceramic within 50 mm of each AVDD pin and replicate the pattern for each DVDD pin. For the REFIN pins, follow TI's reference-decoupling recommendation closely because any reference noise couples directly into the conversion result; do not share decoupling caps across AVDD and REFIN nets.
Route analog input traces (IN+, IN-) symmetrically and keep them away from the parallel digital bus to minimize ADC-to-input crosstalk. Use a guarded analog ground plane that joins the AVSS pins and REFGND at a single point, ideally under the part. If the layout is 4-layer, dedicate the L2 plane as analog ground and place the digital bus above L3 to keep return paths compact. The 48-TQFP (PFB) 7x7 mm package's exposed thermal pad must be soldered to a contiguous copper pour equal to or larger than the part footprint.
Estimated: with a 750 kHz sample clock, the analog-input bandwidth must be at least 0.41 × f_SAMPLE (~308 kHz) per datasheet settling guidelines. A wide-bandwidth op-amp driver (GBW > 5 MHz, low THD) such as OPA2277 or OPA277 is typical; place a 10 kΩ to 50 kΩ resistor between the op-amp output and the ADC input to limit transient current into the on-chip switch-cap network. Verify the input RC network settles within the device's internal acquisition window or linearity suffers at high frequencies.
Because the ADS8371 IPFBRG4 is marked obsolete, designers applying it to new boards should secure sufficient inventory during the last-time-buy window and validate second sources. Always pin-connect the BYTESEL, RESET, RANGE, and CS pins: leaving them floating generates unpredictable interface behavior. Avoid using the digital I/O pins (DB[15:0], BUSY, CS, RD) with pull-ups that exceed 50 µA; refer to the datasheet VI/VOH curves. Finally, do not bypass the reference input - a noisy 50 Hz/60 Hz fundamental on REFIN propagates directly into the ADC output at the same frequency.
コンプライアンス情報
RoHS/lead-free termination indicated by -G4 suffix; AEC-Q100 not applicable to industrial-grade SAR ADC family.
