ATSAMA5D31A-CFU - ARM Cortex-A5 MPU 536MHz | Microchip
部品番号: ATSAMA5D31A-CFU ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $17.42 | $17.42 |
| 10 | $15.68 | $156.80 |
| 100 | $13.97 | $1,397.00 |
| 500 | $12.45 | $6,225.00 |
| 1,000 | $11.86 | $11,860.00 |
ATSAMA5D31A-CFU 概要
An ARM Cortex-A5 MPU is a microprocessor that executes the 32-bit ARMv7-A instruction set under a full operating system (typically Linux), distinguishing it from a microcontroller (MCU) which runs bare-metal or RTOS firmware. Within the SoC hierarchy, this part sits as an MPU -> applications processor -> embedded processor -> semiconductor. The Cortex-A5 core delivers higher compute density than Cortex-M MCUs while retaining deterministic interrupt behaviour, making it suitable for HMIs, gateways, and edge nodes that need graphical or network stacks.
Key features of the ATSAMA5D31A-CFU include 536 MHz maximum CPU clock, hardware floating-point unit (FPU), dual 32 KB L1 caches, 128 KB SRAM, 160 KB boot ROM, an LCD controller supporting TFT displays up to WXGA, a 12-bit ADC, dual Ethernet GMAC with 1588 PTP, dual CAN, USB 2.0 high-speed host and device, and DDR2/LPDDR memory controller. The "-CFU" suffix denotes the industrial temperature grade (-40C to +85C) and TFBGA-324 package, distinguishing it from commercial-grade (-CU) variants.
The architecture integrates a multilayer bus matrix connecting the Cortex-A5 subsystem, SRAM, ROM, and a peripheral bridge to high-bandwidth interfaces (HSMCI, EMAC, USB, LCD, ISI). Hardware encryption is optionally supported through the AES/TDES/SHA crypto block on pin-compatible SAMA5D3 siblings, enabling secure boot and TLS acceleration in connected products. The 160 KB boot ROM contains pre-programmed Atmel/Microchip bootstrap firmware supporting NAND, SD card, SPI flash and serial boot modes.
Typical applications include industrial IoT gateways, building automation HMIs, smart-home controllers, point-of-sale terminals, human-machine interfaces with LCD, medical data loggers, fleet-management telematics, and edge-compute nodes running embedded Linux. The combination of Cortex-A5 compute, integrated FPU, LCD controller, and industrial temperature range suits it to graphical HMI panels and Linux-driven control boxes.
When designing with the ATSAMA5D31A-CFU, plan for a multi-rail power design (typically 1.2V core, 1.8V DDR, 3.3V IO) and a JTAG/SWD debug path. The TFBGA-324 package requires multi-layer PCB with microvia stackups and controlled-impedance routing for DDR2; reference the SAMA5D3 XULT evaluation kit and Microchip application note AT09332 for validated schematics and Linux BSP boot time.
This page synthesizes distributor pricing, drop-in SAMA5D3 family alternatives, and reference design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: ATSAMA5D31A-CFU — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ATSAMA5D31A-CFU （同一形状・フットプリント） — 相違点: Package, Ethernet, USB, LCD Controller, Core Architecture.
クイック比較ツール — 並列比較する代替部品を選択:
ATSAMA5D31A-CUR
✅ ドロップイン✓ 在庫あり
$12.85 / 個
データシートを見る →ATSAMA5D35A-CUR
✅ ドロップイン✓ 在庫あり
$15 / 個
データシートを見る →ATSAMA5D36A-CU
✅ ドロップイン✓ 在庫あり
$46.1 / 個
データシートを見る →ATSAMA5D33A-CU
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$8.95 / 個
データシートを見る →ATSAMA5D34A-CU
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.62 / 個
データシートを見る →ATSAMA5D31A-CFUR
✅ ドロップイン✓ 在庫あり
$11.65 / 個
データシートを見る →ATSAMA5D31A-CFU 最大定格＆電気的特性
| Core Architecture | ARM Cortex-A5 (32-bit) |
| Core Count | 1 |
| Maximum CPU Clock | 536 MHz |
| Floating Point Unit | Yes (hardware FPU) |
| L1 Instruction Cache | 32 KB |
| L1 Data Cache | 32 KB |
| Internal SRAM | 128 KB |
| Boot ROM | 160 KB |
| Instruction Set | ARMv7-A |
| パッケージ | 324-TFBGA (15x15 mm) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (industrial grade) |
| 電源電圧 | 1.2 V core / 1.8 V DDR2 / 3.3 V IO (multi-rail) |
| Memory Controller | DDR2 / LPDDR / LPDDR2 (16-bit, up to 128 MB) |
| LCD Controller | Yes, up to WXGA TFT |
| Ethernet | 2x GMAC with IEEE 1588 PTP |
| USB | 2x USB 2.0 High-Speed (Host + Device) |
| CAN | 2x CAN 2.0B |
| RoHS ステータス | Compliant (Green, Pb-free) |
ATSAMA5D31A-CFU 324-tfbga (15x15 mm) ピン配置ガイド
ATSAMA5D31A-CFU (324-tfbga (15x15 mm) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: ATSAMA5D31A-CFU.
詳細は データシート をご参照ください。
主な用途
ATSAMA5D31A-CFU の用途: 6 件s: Industrial IoT Gateway, Human-Machine Interface (HMI) Panel, Building Automation Controller, Point-of-Sale (POS) Terminal, Medical Data Logger / Patient Monitor, Smart-Home Edge Gateway.
Industrial IoT Gateway
The ATSAMA5D31A-CFU fits industrial IoT gateways because its 536 MHz Cortex-A5 core with FPU runs full Linux, MQTT, and TLS stacks while the dual GMAC with IEEE 1588 PTP delivers deterministic Ethernet for protocol bridging. The industrial temperature grade (-40C to +85C) tolerates factory-floor heat. The DDR2 controller supports 128 MB of low-power RAM, and the dual CAN ports interface with legacy PLCs. Engineers typically pair this MPU with a sub-GHz or Wi-Fi module, an external SPI flash for filesystem, and 4G LTE for cloud uplink, using the 160 KB boot ROM to bootstrap a Yocto Linux image from NAND.
おすすめ
Human-Machine Interface (HMI) Panel
For HMI panels with TFT LCDs up to WXGA resolution, the ATSAMA5D31A-CFU's integrated LCD controller, 2D graphics acceleration, and 128 KB SRAM drive Qt/Embedded or LVGL UIs without an external GPU. The 536 MHz Cortex-A5 with FPU handles 60 fps refresh at 1024x768 with alpha blending, while the 12-bit ADC reads backlight current and touch-panel coordinates. Compared to microcontroller-only solutions, the Cortex-A5 core provides a full POSIX environment for HTML5 web UIs. The TFBGA-324 package and -40C to +85C range suit sealed front-panel mounting.
おすすめ
Building Automation Controller
The ATSAMA5D31A-CFU powers building-automation controllers because its dual CAN buses interface with BACnet, KNX, or Modbus fieldbus networks, while the dual Ethernet MACs segregate fieldbus and IP traffic. The Cortex-A5 runs protocols such as MQTT-SN, BACnet/IP, and OPC UA. The 536 MHz clock with FPU handles cryptographic handshakes for TLS-secured remote access, and the industrial temperature grade meets HVAC panel requirements. The 128 KB SRAM plus external DDR2 supports multi-protocol stacks simultaneously, and the 12-bit ADC monitors analog sensors.
おすすめ
Point-of-Sale (POS) Terminal
POS terminals use the ATSAMA5D31A-CFU because its 536 MHz Cortex-A5 runs full Android or Linux POS stacks, while the integrated LCD controller drives customer-facing and cashier TFT displays. The USB 2.0 high-speed ports connect barcode scanners, receipt printers, and customer displays. The hardware FPU accelerates encryption for EMV chip-card transactions, and the industrial temperature grade tolerates retail environments. Engineers typically pair this MPU with a Secure Access Module (SAM) slot via SPI and an Ethernet PHY for payment-network connectivity.
おすすめ
Medical Data Logger / Patient Monitor
The ATSAMA5D31A-CFU fits medical data loggers because the 536 MHz Cortex-A5 with FPU runs signal-processing algorithms for ECG, SpO2, and temperature waveforms, while the 12-bit ADC digitizes sensor outputs at clinical sampling rates. The dual CAN buses interface with hospital asset-tracking networks, and the LCD controller drives bedside TFT displays. The industrial temperature grade and Microchip's longevity program suit regulated medical-device lifecycles. Engineers add a Wi-Fi/BLE module for HL7 data export and use the boot ROM to enforce signed firmware images.
おすすめ
Smart-Home Edge Gateway
Smart-home edge gateways benefit from the ATSAMA5D31A-CFU's Cortex-A5 running Matter, Thread border router, or Zigbee hub stacks in parallel with a Linux user interface. The dual GMAC separates WAN and LAN, while the dual USB 2.0 high-speed ports host external radios. The 128 KB internal SRAM plus DDR2 supports concurrent protocol translation, and the -40C to +85C range meets wall-mounted enclosure thermal budgets. Engineers typically load the application from SPI NOR flash via the 160 KB boot ROM.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ATSAMA5D31A-CFU — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ATSAMA5D31A-CUR | ATSAMA5D35A-CUR | ATSAMA5D36A-CU | ATSAMA5D33A-CU | ATSAMA5D31A-CFUR |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 324-TFBGA (15x15 mm) | 324-TFBGA (15x15 mm) - same | 324-TFBGA (15x15 mm) - same | 324-TFBGA (15x15 mm) - same | 324-TFBGA (15x15 mm) - same | 324-TFBGA (15x15 mm) - same |
| Core | ARM Cortex-A5, 1 core | ARM Cortex-A5, 1 core | ARM Cortex-A5, 1 core | ARM Cortex-A5, 1 core | ARM Cortex-A5, 1 core | ARM Cortex-A5, 1 core |
| Max CPU Clock | 536 MHz | 536 MHz | 536 MHz | 536 MHz | 536 MHz | 536 MHz |
| Internal SRAM | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB |
| Temperature Grade | Industrial (-40C to +85C) | Industrial | Industrial | Commercial | Commercial | Industrial |
| Ethernet | 2x GMAC with 1588 PTP | 2x GMAC with 1588 PTP | 2x GMAC with 1588 PTP | 2x GMAC with 1588 PTP | 1x GMAC | 2x GMAC with 1588 PTP |
主な差別化要因
- Industrial temperature grade in the same TFBGA package as commercial siblings （vs ATSAMA5D36A-CU)
- Single-cost Cortex-A5 with hardware FPU （vs ATSAMA5D35A-CUR)
- 128 KB internal SRAM without external memory for boot-time tasks （vs ATSAMA5D33A-CU)
- Dual GMAC with IEEE 1588 PTP precision time stamping （vs ATSAMA5D33A-CU)
設計ノート
The ATSAMA5D31A-CFU requires a multi-rail power design: 1.2V for the Cortex-A5 core (capable of ~500 mA peak at 536 MHz), 1.8V for the DDR2/LPDDR2 controller and PHY, and 3.3V for IO and analog blocks. Use a sequenced power-up with the 1.2V rail last so that IO lines are not driven before the core is alive; the SAMA5D3 reference schematic uses a TPS65217 or equivalent PMIC. Estimated total power at full load is approximately 1.5W worst case, requiring attention to thermal dissipation even at industrial temperatures.
The 324-TFBGA package at 0.8 mm ball pitch demands a microvia stack-up (typically 4-6 layers, laser-drilled microvias) and impedance-controlled DDR2 traces (50 ohm single-ended, 100 ohm differential for clock). Reference the SAMA5D3 XULT evaluation kit for validated routing. Maintain a continuous ground plane under the BGA to provide a low-impedance return path and to spread heat. Decoupling: place 100 nF X7R caps within 2 mm of every VDDCORE/VVDDIO power ball and one 4.7 uF bulk cap per rail.
Estimated: at 1.2V core voltage, 536 MHz, full peripheral activity, the part dissipates ~1.5 W. The 324-TFBGA has theta_JA approximately 25-30 C/W on a 4-layer JEDEC test board, yielding a junction temperature rise of ~40-45 C above ambient. For -40C to +85C operation, ensure ambient stays below ~45 C under full load, or attach a thermal pad and heatsink. The exposed die pad (if present on the package bottom) must be soldered to a copper pour to maximize heat spreading.
Do not assume DDR2 timing is automatic - the SPD/EWlite byte-programmable DDR2 controller must be calibrated via the bootstrap loader for the chosen memory chip. Booting fails silently if the boot ROM cannot detect a valid image; ensure the BMS (Boot Mode Select) pins are correctly pulled at reset. Watchdog timer must be enabled in production firmware to recover from Linux kernel panics. Always validate the JTAG/SWD debug chain with an external programmer before sealing the enclosure.
コンプライアンス情報
RoHS compliant and Pb-free per Microchip product page (BGA, GREEN, IND TEMP suffix). Not AEC-Q100 qualified - this is an MPU, not an automotive-grade part. Halogen-free status not explicitly stated in verified data.
