DSPIC33CK128MC106T-I/MR - 16-bit DSC 100MHz 128KB 64-QFN | Microchip
部品番号: DSPIC33CK128MC106T-I/MR ✓ 生産中DSPIC33CK128MC106T-I/MR 概要
A digital signal controller combines the compute architecture of a microcontroller with the math acceleration of a DSP in a single chip. Within the embedded hierarchy, the DSC sits above general-purpose MCUs and beside DSPs, offering deterministic interrupt latency and single-cycle MAC instructions that make it a power management IC controller of choice for switch-mode converters and motor drives.
Key features include high-speed PWM peripherals with advanced dead-time and fault control, two 12-bit DACs for comparator references, integrated operational amplifiers that off-board external op-amps in current-sense paths, and CAN Flexible Data-Rate (CAN FD) for automotive and industrial networking. The 20-channel 12-bit ADC supports simultaneous sampling critical for three-phase current sensing.
Architecturally, the dsPIC33CK core reaches 100 MIPS from a 3.3V rail using a pipelined design with DSP engine, barrel shifter, four DMA channels, and boundary-scan testability. The Cortex-like deterministic response keeps control loops predictable, and the extended -40C to +125C industrial temperature grade suits harsh environments.
Typical applications include brushless DC and PMSM motor control (FOC), digital power supplies such as totem-pole PFC and LLC converters, and automotive/industrial CAN FD nodes. The op-amps and high-resolution PWM directly serve current shunt amplification and dead-time control in these loops.
Design consideration: the 3.0V to 3.6V supply window is strict; provide a regulated 3.3V rail with local 0.1uF decoupling at every VDD/VSS pair, and exploit the 64-QFN exposed pad for ground return integrity.
This page synthesizes distributor availability, drop-in family alternatives, and application-specific design notes beyond what the 984-page manufacturer datasheet presents.
ドロップイン代替品: DSPIC33CK128MC106T-I/MR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
DSPIC33CK256MC106T-I/MR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33CK64MC106T-I/MR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33CK128MC105T-I/MR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33CK128MC106T-E/MR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DSPIC33CH64MP506T-I/MR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DSPIC33CK128MC106T-I/MR 最大定格＆電気的特性
| Core | dsPIC33C 16-bit DSC |
| Max CPU Speed | 100 MHz (100 MIPS) |
| Program Memory (FLASH) | 128KB (128K x 8) |
| RAM | 16KB |
| Operating Voltage | 3 V to 3.6 V |
| ADC Resolution | 12-bit |
| ADC Channels | 20 |
| DAC Channels | 2 x 12-bit |
| Integrated Op-Amps | Yes |
| Communication Interfaces | CAN FD, UART, SPI, I2C |
| PWM | High-Speed PWM with fault protection |
| GPIO Count | 53 I/O |
| DMA Channels | 4 |
| パッケージ | 64-QFN (9x9x0.9 mm), MR |
| 動作温度 | -40C to +125C (I grade) |
| 実装タイプ | Surface Mount |
| Technology | CMOS |
| Packaging | Tape & Reel (T suffix) |
| RoHS ステータス | Compliant |
DSPIC33CK128MC106T-I/MR 64-qfn (9x9x0.9 mm), mr ピン配置ガイド
DSPIC33CK128MC106T-I/MR (64-qfn (9x9x0.9 mm), mr パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: DSPIC33CK128MC106T-I/MR.
詳細は データシート をご参照ください。
主な用途
DSPIC33CK128MC106T-I/MR の用途: 6 件s: Brushless DC / PMSM Motor Control (FOC), Digital Power Supplies (Totem-Pole PFC, LLC), Automotive CAN FD Network Nodes, Sensorless BLDC Fans, Pumps and Compressors, Solar Micro-Inverters and MPPT Converters, Industrial Robotics and Automation Motion Control.
Brushless DC / PMSM Motor Control (FOC)
The DSPIC33CK128MC106T-I/MR fits field-oriented control motor drives because its 100 MIPS dsPIC33C core executes the Clarke/Park transforms and PI current loops with single-cycle MAC instructions, while the 20-channel 12-bit ADC samples two or three phase currents simultaneously. The high-speed PWM generates complementary gate signals with programmable dead time, and cycle-by-cycle current limiting is implemented via the 12-bit DACs driving on-chip comparators, removing external trip circuitry. Integrated op-amps amplify low-side shunt voltages directly, trimming BOM cost. Typical topology places the DSC between a gate driver (e.g., MIC4104-class half-bridge driver) and the inverter stage; the quantified benefit is deterministic loop rates in the tens of kHz with fault response within one PWM cycle.
おすすめ
Digital Power Supplies (Totem-Pole PFC, LLC)
In digitally controlled AC-DC and DC-DC converters, the DSPIC33CK128MC106T-I/MR provides the high-resolution PWM and fast 12-bit ADC needed for totem-pole PFC and LLC control loops at 100 kHz-plus switching frequencies. Its on-chip comparators with 12-bit DAC references implement hardware overcurrent protection independent of software latency, while four DMA channels stream ADC results to RAM without CPU loading. The 3.3V isolated-supply friendly rail simplifies bias design after an isolated flyback. Placed as the sole control IC, it replaces analog control loops and offers firmware-tunable compensation; the trade-off versus a fixed analog controller is the need for firmware development, repaid by adaptability across output-voltage variants of the same power stage.
おすすめ
Automotive CAN FD Network Nodes
The integrated CAN Flexible Data-Rate module of the DSPIC33CK128MC106T-I/MR supports 64-byte payloads and faster data-phase bit rates than classical CAN, making the device a strong node controller for automotive body, actuator, and pump-control units. The -40C to +125C I-grade covers underhood-adjacent zones, and the 128KB flash accommodates UDS/OBD-style firmware stacks. Paired with an external CAN FD transceiver such as the MCP2562FD and a low-dropout regulator, the DSC forms a compact node on the same 64-QFN footprint as higher-flash family members, allowing one PCB to scale across feature tiers. The key performance consideration is confirming qualification level for the target automotive program.
おすすめ
Sensorless BLDC Fans, Pumps and Compressors
Sensorless trapezoidal and sinusoidal control of fans, pumps, and compressors leverages the DSPIC33CK128MC106T-I/MR op-amps and comparators for back-EMF and shunt signal conditioning entirely on-chip, minimizing external analog components. The 100 MIPS core runs commutation and speed-loop software at sample rates that keep acoustic noise low, and the high-speed PWM supports 120-degree and 180-degree modulation schemes. The two 12-bit DACs set BEMF zero-cross thresholds and overcurrent trip levels digitally, so a single firmware image can serve multiple motor ratings. Designs benefit from the 53 GPIO count for tach output, fault indication, and host interface, with the 64-QFN 9x9 mm package fitting compact fan-hub and pump-controller PCBs.
おすすめ
Solar Micro-Inverters and MPPT Converters
In solar micro-inverter and MPPT buck/boost stages, the DSPIC33CK128MC106T-I/MR executes the maximum-power-point algorithm while its 12-bit ADC tracks panel voltage and current with 20 available channels, enabling multi-panel or multi-string monitoring from one controller. High-resolution PWM phases with the LLC or interleaved-boost power stage, and hardware comparators provide the fast cycle-by-cycle overcurrent trip that grid-tie safety requires. The 128KB flash stores MPPT, grid-monitoring, and communication firmware together, and the CAN FD or UART interfaces link to string-level telemetry. The performance trade-off versus a dedicated MPPT ASIC is firmware effort, offset by field-updatable algorithm tuning across panel generations on the identical PCB.
おすすめ
Industrial Robotics and Automation Motion Control
Robot joint and actuator controllers use the DSPIC33CK128MC106T-I/MR to close high-bandwidth current loops (via the 12-bit ADC and op-amps) while handling encoder interfaces and CAN FD communication on the same chip, removing a separate communication MCU. The 100 MIPS core with DSP instructions and four DMA channels supports multi-axis coordination tasks at the node level, and boundary-scan capability aids production test of dense 64-QFN boards. Operating to +125C, the controller tolerates enclosed actuator thermal environments. A quantified benefit is deterministic PWM fault shutdown via hardware, essential for safety in collaborative robotics; the consideration is that higher-level trajectory planning typically remains in a host PLC or central controller.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33CK128MC106T-I/MR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33CK256MC106T-I/MR | DSPIC33CK64MC106T-I/MR | DSPIC33CK128MC105T-I/MR | DSPIC33CH64MP506T-I/MR |
|---|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| FLASH Memory | 128KB | 256KB | 64KB | 128KB | 64KB (master) + 256KB (slave system) |
| CPU Speed | 100 MHz (100 MIPS) | 100 MHz | 100 MHz | 100 MHz | 2 x 100 MHz (dual core) |
| Core Architecture | Single-core dsPIC33C | Single-core dsPIC33C | Single-core dsPIC33C | Single-core dsPIC33C | Dual-core dsPIC33CH |
| Temperature Grade | -40C to +125C (I) | -40C to +125C (I) | -40C to +125C (I) | -40C to +125C (I) | -40C to +125C (I) |
| Operating Voltage | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
主な差別化要因
- Balanced 128KB flash / 16KB memory point （vs DSPIC33CK64MC106T-I/MR)
- Cost-efficient for single-core control （vs DSPIC33CH64MP506T-I/MR)
- Flash headroom trade-off （vs DSPIC33CK256MC106T-I/MR)
設計ノート
The DSPIC33CK128MC106T-I/MR requires a regulated 3.0V to 3.6V supply for full 100 MIPS operation. Place 0.1uF ceramic capacitors at every VDD/VSS pin pair, plus at least one 10uF bulk capacitor near the package. Route each decoupling capacitor with minimal loop inductance directly to the adjacent VDD/VSS pair rather than sharing traces. On motor-drive boards, separate the digital 3.3V rail from gate-driver supply rails or use ferrite isolation to prevent PWM switching transients from coupling into the ADC reference and corrupting current-sense readings.
The 64-QFN (9x9 mm) MR package has a center exposed pad that must be soldered to a grounded copper pour with an array of thermal vias; do not leave it floating, as it carries ground return and heat. For 100 MHz internal clocking, keep the crystal/oscillator traces short and guard them with ground. Use Microchip's reference designs for the dsPIC33CK MC10x family as layout starting points, particularly regarding placement of the peripheral-pin-selectable PWM outputs away from sensitive analog ADC input traces.
Verify Peripheral Pin Select (PPS) assignments before committing the PCB: most GPIO on the DSPIC33CK128MC106 is multiplexed and incorrect PPS configuration is the most common bring-up failure. Confirm flash sizing margin: keep at least 20% of the 128KB free for firmware growth and field updates. When substituting the DSPIC33CH64MP506T-I/MR, note that the dual-core CH pin map differs - it is not a blind drop-in despite the same 64-QFN footprint. Use MPLAB X with the PICkit 4 or ICD 4 for programming; legacy PICkit 3 support is limited.
コンプライアンス情報
Newark explicitly lists ROHS COMPLIANT: YES for this MPN. Standard commercial/industrial part - not AEC-Q100 qualified; consult Microchip for automotive-grade ordering options.
