DSPIC33CK128MC106T-I/MR - 16-bit DSC 100MHz 128KB 64-QFN | Microchip
부품 번호: DSPIC33CK128MC106T-I/MR ✓ 활성DSPIC33CK128MC106T-I/MR 개요
A digital signal controller combines the compute architecture of a microcontroller with the math acceleration of a DSP in a single chip. Within the embedded hierarchy, the DSC sits above general-purpose MCUs and beside DSPs, offering deterministic interrupt latency and single-cycle MAC instructions that make it a power management IC controller of choice for switch-mode converters and motor drives.
Key features include high-speed PWM peripherals with advanced dead-time and fault control, two 12-bit DACs for comparator references, integrated operational amplifiers that off-board external op-amps in current-sense paths, and CAN Flexible Data-Rate (CAN FD) for automotive and industrial networking. The 20-channel 12-bit ADC supports simultaneous sampling critical for three-phase current sensing.
Architecturally, the dsPIC33CK core reaches 100 MIPS from a 3.3V rail using a pipelined design with DSP engine, barrel shifter, four DMA channels, and boundary-scan testability. The Cortex-like deterministic response keeps control loops predictable, and the extended -40C to +125C industrial temperature grade suits harsh environments.
Typical applications include brushless DC and PMSM motor control (FOC), digital power supplies such as totem-pole PFC and LLC converters, and automotive/industrial CAN FD nodes. The op-amps and high-resolution PWM directly serve current shunt amplification and dead-time control in these loops.
Design consideration: the 3.0V to 3.6V supply window is strict; provide a regulated 3.3V rail with local 0.1uF decoupling at every VDD/VSS pair, and exploit the 64-QFN exposed pad for ground return integrity.
This page synthesizes distributor availability, drop-in family alternatives, and application-specific design notes beyond what the 984-page manufacturer datasheet presents.
드롭인 대체품: DSPIC33CK128MC106T-I/MR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
DSPIC33CK256MC106T-I/MR
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
DSPIC33CK64MC106T-I/MR
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
DSPIC33CK128MC105T-I/MR
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
DSPIC33CK128MC106T-E/MR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DSPIC33CH64MP506T-I/MR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DSPIC33CK128MC106T-I/MR 최대 정격 & 전기적 특성
| Core | dsPIC33C 16-bit DSC |
| Max CPU Speed | 100 MHz (100 MIPS) |
| Program Memory (FLASH) | 128KB (128K x 8) |
| RAM | 16KB |
| Operating Voltage | 3 V to 3.6 V |
| ADC Resolution | 12-bit |
| ADC Channels | 20 |
| DAC Channels | 2 x 12-bit |
| Integrated Op-Amps | Yes |
| Communication Interfaces | CAN FD, UART, SPI, I2C |
| PWM | High-Speed PWM with fault protection |
| GPIO Count | 53 I/O |
| DMA Channels | 4 |
| 패키지 | 64-QFN (9x9x0.9 mm), MR |
| 동작 온도 | -40C to +125C (I grade) |
| 실장 유형 | Surface Mount |
| Technology | CMOS |
| Packaging | Tape & Reel (T suffix) |
| RoHS 상태 | Compliant |
DSPIC33CK128MC106T-I/MR 64-qfn (9x9x0.9 mm), mr 핀 구성 가이드
DSPIC33CK128MC106T-I/MR(64-qfn (9x9x0.9 mm), mr 패키지)의 핀 구성입니다. 이 디지털 IC에는 GPIO, 통신 인터페이스(UART, SPI, I2C), 전원 핀이 포함되어 있습니다. 대체 핀 기능과 구성 옵션은 제조사 데이터시트를 참조하십시오. 임베디드 시스템 설계와 PCB 레이아웃에 필수적입니다.
다음에 대한 상세 핀아웃 데이터 없음: DSPIC33CK128MC106T-I/MR.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
DSPIC33CK128MC106T-I/MR 적합 용도: 6 애플리케이션s: Brushless DC / PMSM Motor Control (FOC), Digital Power Supplies (Totem-Pole PFC, LLC), Automotive CAN FD Network Nodes, Sensorless BLDC Fans, Pumps and Compressors, Solar Micro-Inverters and MPPT Converters, Industrial Robotics and Automation Motion Control.
Brushless DC / PMSM Motor Control (FOC)
The DSPIC33CK128MC106T-I/MR fits field-oriented control motor drives because its 100 MIPS dsPIC33C core executes the Clarke/Park transforms and PI current loops with single-cycle MAC instructions, while the 20-channel 12-bit ADC samples two or three phase currents simultaneously. The high-speed PWM generates complementary gate signals with programmable dead time, and cycle-by-cycle current limiting is implemented via the 12-bit DACs driving on-chip comparators, removing external trip circuitry. Integrated op-amps amplify low-side shunt voltages directly, trimming BOM cost. Typical topology places the DSC between a gate driver (e.g., MIC4104-class half-bridge driver) and the inverter stage; the quantified benefit is deterministic loop rates in the tens of kHz with fault response within one PWM cycle.
추천
Digital Power Supplies (Totem-Pole PFC, LLC)
In digitally controlled AC-DC and DC-DC converters, the DSPIC33CK128MC106T-I/MR provides the high-resolution PWM and fast 12-bit ADC needed for totem-pole PFC and LLC control loops at 100 kHz-plus switching frequencies. Its on-chip comparators with 12-bit DAC references implement hardware overcurrent protection independent of software latency, while four DMA channels stream ADC results to RAM without CPU loading. The 3.3V isolated-supply friendly rail simplifies bias design after an isolated flyback. Placed as the sole control IC, it replaces analog control loops and offers firmware-tunable compensation; the trade-off versus a fixed analog controller is the need for firmware development, repaid by adaptability across output-voltage variants of the same power stage.
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Automotive CAN FD Network Nodes
The integrated CAN Flexible Data-Rate module of the DSPIC33CK128MC106T-I/MR supports 64-byte payloads and faster data-phase bit rates than classical CAN, making the device a strong node controller for automotive body, actuator, and pump-control units. The -40C to +125C I-grade covers underhood-adjacent zones, and the 128KB flash accommodates UDS/OBD-style firmware stacks. Paired with an external CAN FD transceiver such as the MCP2562FD and a low-dropout regulator, the DSC forms a compact node on the same 64-QFN footprint as higher-flash family members, allowing one PCB to scale across feature tiers. The key performance consideration is confirming qualification level for the target automotive program.
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Sensorless BLDC Fans, Pumps and Compressors
Sensorless trapezoidal and sinusoidal control of fans, pumps, and compressors leverages the DSPIC33CK128MC106T-I/MR op-amps and comparators for back-EMF and shunt signal conditioning entirely on-chip, minimizing external analog components. The 100 MIPS core runs commutation and speed-loop software at sample rates that keep acoustic noise low, and the high-speed PWM supports 120-degree and 180-degree modulation schemes. The two 12-bit DACs set BEMF zero-cross thresholds and overcurrent trip levels digitally, so a single firmware image can serve multiple motor ratings. Designs benefit from the 53 GPIO count for tach output, fault indication, and host interface, with the 64-QFN 9x9 mm package fitting compact fan-hub and pump-controller PCBs.
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Solar Micro-Inverters and MPPT Converters
In solar micro-inverter and MPPT buck/boost stages, the DSPIC33CK128MC106T-I/MR executes the maximum-power-point algorithm while its 12-bit ADC tracks panel voltage and current with 20 available channels, enabling multi-panel or multi-string monitoring from one controller. High-resolution PWM phases with the LLC or interleaved-boost power stage, and hardware comparators provide the fast cycle-by-cycle overcurrent trip that grid-tie safety requires. The 128KB flash stores MPPT, grid-monitoring, and communication firmware together, and the CAN FD or UART interfaces link to string-level telemetry. The performance trade-off versus a dedicated MPPT ASIC is firmware effort, offset by field-updatable algorithm tuning across panel generations on the identical PCB.
추천
Industrial Robotics and Automation Motion Control
Robot joint and actuator controllers use the DSPIC33CK128MC106T-I/MR to close high-bandwidth current loops (via the 12-bit ADC and op-amps) while handling encoder interfaces and CAN FD communication on the same chip, removing a separate communication MCU. The 100 MIPS core with DSP instructions and four DMA channels supports multi-axis coordination tasks at the node level, and boundary-scan capability aids production test of dense 64-QFN boards. Operating to +125C, the controller tolerates enclosed actuator thermal environments. A quantified benefit is deterministic PWM fault shutdown via hardware, essential for safety in collaborative robotics; the consideration is that higher-level trajectory planning typically remains in a host PLC or central controller.
추천
추천 제품 요약
엔지니어링 참조 데이터: DSPIC33CK128MC106T-I/MR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | DSPIC33CK256MC106T-I/MR | DSPIC33CK64MC106T-I/MR | DSPIC33CK128MC105T-I/MR | DSPIC33CH64MP506T-I/MR |
|---|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| FLASH Memory | 128KB | 256KB | 64KB | 128KB | 64KB (master) + 256KB (slave system) |
| CPU Speed | 100 MHz (100 MIPS) | 100 MHz | 100 MHz | 100 MHz | 2 x 100 MHz (dual core) |
| Core Architecture | Single-core dsPIC33C | Single-core dsPIC33C | Single-core dsPIC33C | Single-core dsPIC33C | Dual-core dsPIC33CH |
| Temperature Grade | -40C to +125C (I) | -40C to +125C (I) | -40C to +125C (I) | -40C to +125C (I) | -40C to +125C (I) |
| Operating Voltage | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
주요 차별점
- Balanced 128KB flash / 16KB memory point (vs DSPIC33CK64MC106T-I/MR)
- Cost-efficient for single-core control (vs DSPIC33CH64MP506T-I/MR)
- Flash headroom trade-off (vs DSPIC33CK256MC106T-I/MR)
설계 노트
The DSPIC33CK128MC106T-I/MR requires a regulated 3.0V to 3.6V supply for full 100 MIPS operation. Place 0.1uF ceramic capacitors at every VDD/VSS pin pair, plus at least one 10uF bulk capacitor near the package. Route each decoupling capacitor with minimal loop inductance directly to the adjacent VDD/VSS pair rather than sharing traces. On motor-drive boards, separate the digital 3.3V rail from gate-driver supply rails or use ferrite isolation to prevent PWM switching transients from coupling into the ADC reference and corrupting current-sense readings.
The 64-QFN (9x9 mm) MR package has a center exposed pad that must be soldered to a grounded copper pour with an array of thermal vias; do not leave it floating, as it carries ground return and heat. For 100 MHz internal clocking, keep the crystal/oscillator traces short and guard them with ground. Use Microchip's reference designs for the dsPIC33CK MC10x family as layout starting points, particularly regarding placement of the peripheral-pin-selectable PWM outputs away from sensitive analog ADC input traces.
Verify Peripheral Pin Select (PPS) assignments before committing the PCB: most GPIO on the DSPIC33CK128MC106 is multiplexed and incorrect PPS configuration is the most common bring-up failure. Confirm flash sizing margin: keep at least 20% of the 128KB free for firmware growth and field updates. When substituting the DSPIC33CH64MP506T-I/MR, note that the dual-core CH pin map differs - it is not a blind drop-in despite the same 64-QFN footprint. Use MPLAB X with the PICkit 4 or ICD 4 for programming; legacy PICkit 3 support is limited.
규정 준수 정보
Newark explicitly lists ROHS COMPLIANT: YES for this MPN. Standard commercial/industrial part - not AEC-Q100 qualified; consult Microchip for automotive-grade ordering options.
