DSPIC33FJ128GP804-H/PT - 16-bit DSC, 128KB Flash, 40MHz | Microchip
部品番号: DSPIC33FJ128GP804-H/ ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $7.2 | $7.20 |
| 10 | $6.55 | $65.50 |
| 100 | $5.8 | $580.00 |
| 500 | $5.25 | $2,625.00 |
| 1,000 | $4.7 | $4,700.00 |
DSPIC33FJ128GP804-H/ 概要
A digital signal controller combines the peripheral set and ease of use of a microcontroller with the multiply-accumulate computational engine of a DSP. Within the power-management hierarchy of embedded systems, a DSC sits between general-purpose 16-bit MCUs and dedicated DSPs, making it the natural choice for control loops that require both fast math and rich analog integration. The dsPIC33FJ family is pin-migration compatible toward PIC24 and dsPIC30F devices.
Key features include the 16-bit modified Harvard architecture core, single-cycle MAC and DSP instruction support, two on-chip audio-grade peripherals typical of the GP (General Purpose) family, and Peripheral Pin Select that lets digital peripherals such as UART, SPI and I2C be remapped to many of the 21 available I/O pins, dramatically simplifying PCB layout.
The architecture pairs the DSP engine with a broad advanced-analog portfolio, allowing sensor signal chains to be digitized and processed on-chip. Microchip provides a BSD boundary-scan file and PIM support on the Explorer 16/32 development board, easing hardware bring-up and migration between 44-pin and 100-pin family members.
Typical applications include digital power supplies and power factor correction, sensor signal acquisition and conditioning, motor-adjacent general-purpose control, and audio processing pipelines where the DSP engine handles filtering in real time.
A key design consideration is supply voltage: the device operates from 3 V to 3.6 V, so a well-regulated 3.3 V rail with adequate decoupling is essential, and 5 V signals must be level-shifted or series-resistor limited per Microchip connection guidelines.
This page synthesizes distributor pricing context, drop-in same-family alternatives, and practical design notes not consolidated in the manufacturer datasheet.
ドロップイン代替品: DSPIC33FJ128GP804-H/ — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33FJ128GP804-H/ （同一形状・フットプリント） — 相違点: Core Architecture, Package, Operating Temperature, Max Clock Speed, Serial I/O Ports.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33FJ128GP804-I/PT
✅ ドロップイン✓ 在庫あり
$4.46 / 個
データシートを見る →DSPIC33FJ64GP804-H/PT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ64GP804-I/PT
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.72 / 個
データシートを見る →DSPIC33FJ32GP304-H/PT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ128MC804-H/PT
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$6.85 / 個
データシートを見る →DSPIC33FJ128GP804-H/ 最大定格＆電気的特性
| Core Architecture | 16-bit dsPIC33F DSC |
| Max Clock Speed | 40 MHz |
| Performance | 20 MIPS |
| Program Memory Type | Flash |
| Flash Memory | 128 KB |
| SRAM | 16 KB |
| 電源電圧 | 3 V to 3.6 V |
| I/O Ports / Pins | 21 |
| パッケージ | 44-pin TQFP (PT) / 44-pin QFN (ML), 6 x 6 mm QFN height 0.90 mm |
| Peripheral Pin Select | Yes (PPS remappable peripherals) |
| DSP Engine | Single-cycle MAC, DSP instructions |
| Life Cycle Stage | ACTIVE |
| Boundary Scan Support | Yes (BSD file available) |
| Development Board Support | Explorer 16/32 via PIM (70325A) |
| 実装タイプ | Surface Mount |
| Migration Path | Pin-migration to/from PIC24 and dsPIC30F, 44-to-100-pin |
DSPIC33FJ128GP804-H/ 44-pin tqfp (pt) / 44-pin qfn (ml), 6 x 6 mm qfn height 0.90 mm ピン配置ガイド
DSPIC33FJ128GP804-H/ (44-pin tqfp (pt) / 44-pin qfn (ml), 6 x 6 mm qfn height 0.90 mm パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: DSPIC33FJ128GP804-H/.
詳細は データシート をご参照ください。
主な用途
DSPIC33FJ128GP804-H/ の用途: 6 件s: Digital Power Conversion, Sensor Signal Acquisition, Industrial Automation Control, Audio Signal Processing, Motor-Adjacent Embedded Control, Portable and Battery-Powered Instruments.
Digital Power Conversion
The dsPIC33FJ128GP804's 20 MIPS DSP core with single-cycle MAC executes the proportional-integral control math of digital power supplies and PFC stages within each switching cycle, while its advanced analog blocks sample current and voltage feedback directly on-chip. Peripheral Pin Select lets the designer place PWM outputs and ADC-triggered capture on optimal pins, minimizing loop-area parasitics on a compact 44-pin TQFP board. Because the 3 V to 3.6 V supply isolates the digital core from power-stage noise with proper grounding, control-loop jitter stays low. For converters above 100 W, pair the controller with gate-driver ICs and a switching regulator front end; the 44-pin footprint leaves routing channels for the high-voltage section.
おすすめ
Sensor Signal Acquisition
With 128 KB Flash and a DSP engine, the dsPIC33FJ128GP804 can run on-board filtering, FFT analysis, and calibration algorithms on raw sensor data, reducing host-processor load. Its analog integration digitizes signals close to the source, while 21 remappable I/O lines (via PPS) connect UART, SPI, or I2C sensors on any convenient pin of the 44-pin TQFP. The 16 KB SRAM buffers multiple channels of sampled data for burst processing. Supply tolerance of 3 V to 3.6 V matches standard 3.3 V sensor rails, simplifying the power tree. Multi-board designs can migrate the same firmware to 100-pin family members using the documented 44-to-100-pin pinout table from Microchip sheet 70325A when channel counts grow.
おすすめ
Industrial Automation Control
In factory automation nodes, the dsPIC33FJ128GP804 serves as a compact intelligence point executing 20 MIPS of control logic, protocol handling, and diagnostics. PPS remapping of UART, SPI, and I2C lets one firmware image support multiple board revisions with different connector pinouts, cutting qualification cost. The industrial supply range of 3 V to 3.6 V and surface-mount 44-pin package suit dense DIN-rail and distributed I/O hardware. Its DSP instructions accelerate condition-monitoring tasks such as vibration signature analysis on motors. Developers validate designs on Microchip's Explorer 16/32 board via the dedicated PIM (sheet 70325A) before committing PCBs, and the device's In Production lifecycle status secures long-term sourcing for industrial product lifecycles.
おすすめ
Audio Signal Processing
The GP (General Purpose) dsPIC33FJ family targets audio-grade designs, and the dsPIC33FJ128GP804's 40 MHz DSP core implements real-time IIR/FIR filtering, AGC, and audio effect algorithms within its 16 KB SRAM. PPS allows UART and SPI audio-data links to be routed flexibly across the 44-pin TQFP, and the on-chip ADC can sample microphone-level signals directly with software post-processing. Because the device operates from a quiet 3.3 V rail, audio noise coupling is manageable with sound PCB practice. Typical deployments include intercoms, voice-band modems, and sound-reactive control systems. For full-fidelity codec applications, pair the DSC with an external codec over the SPI/I2C pins assigned through Peripheral Pin Select.
おすすめ
Motor-Adjacent Embedded Control
While the MC (Motor Control) family carries dedicated high-resolution PWM hardware, the dsPIC33FJ128GP804 is well suited to supervisory motor-adjacent control: envelope protection, speed profiling, communication with a host PLC, and encoder signal conditioning via input capture. Its 20 MIPS core and DSP MAC handle quadrature decoding and reference-profile math without external logic, and 21 remappable I/O pins adapt to various encoder and sensor wiring through PPS. Running from a clean 3 V to 3.6 V rail away from the noisy power stage, it complements an MC-series motor DSC or a discrete gate-driver stage. The 44-pin QFN variant offers a 6 x 6 mm footprint for compact drive boards with shared firmware.
おすすめ
Portable and Battery-Powered Instruments
Handheld instruments benefit from the dsPIC33FJ128GP804's balance of compute and integration: a single 44-pin TQFP provides the DSP engine for measurement math, on-chip analog for signal capture, and remappable serial peripherals for displays and wireless modules via PPS. The 3 V to 3.6 V supply matches a single lithium cell regulated to 3.3 V, and 128 KB Flash accommodates field-updatable measurement firmware. The 6 x 6 mm QFN packaging option (suffix /ML) minimizes PCB area for pen-style and compact test tools. Developers prototype on Explorer 16/32 with the documented PIM, then drop the same die into the production footprint. Lifecycle status In Production supports multi-year instrument product lines.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33FJ128GP804-H/ — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33FJ128GP804-I/PT | DSPIC33FJ64GP804-H/PT | DSPIC33FJ32GP304-H/PT | DSPIC33FJ128MC804-H/PT |
|---|---|---|---|---|---|
| Package | 44-TQFP (PT) | 44-TQFP - same | 44-TQFP - same | 44-TQFP - same | 44-TQFP - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core Performance | 40 MHz / 20 MIPS | 40 MHz / 20 MIPS | 40 MHz / 20 MIPS | 40 MHz / 20 MIPS | 40 MHz / 20 MIPS |
| Flash Memory | 128 KB | 128 KB | 64 KB | 32 KB | 128 KB |
| Supply Voltage | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
| Temperature Grade | -H (high temp; verify range in datasheet) | -I (industrial) | -H (same grade) | -H (same grade) | -H (same grade) |
| Peripheral Family Orientation | GP (General Purpose) | GP - identical | GP | GP (reduced analog set) | MC (motor-control PWM oriented) |
主な差別化要因
- Maximum family memory in a 44-pin GP package （vs DSPIC33FJ64GP804-H/PT)
- Full GP peripheral and analog set （vs DSPIC33FJ32GP304-H/PT)
- General Purpose I/O orientation for signal-chain designs （vs DSPIC33FJ128MC804-H/PT)
設計ノート
The dsPIC33FJ128GP804 operates from a 3 V to 3.6 V supply, so a regulated 3.3 V rail is required; 5 V logic must be level-shifted or series-limited per Microchip connection guidelines. Place 0.1 uF ceramic decoupling capacitors on every VDD pin pair within 2 mm of the package, plus one bulk 10 uF capacitor per board. Follow the datasheet's VDDCORE capacitor requirement exactly - the internal regulator's external capacitor must be the specified value and low-ESR, or the core may become unstable during flash write operations.
Exploit Peripheral Pin Select (PPS) during layout, not after: because UART, SPI, and I2C pins are software-remappable on this 44-pin device (per Microchip PIM sheet 70325A), route signals first for signal-integrity and then assign PPS registers in firmware to match. Keep the exposed analog pins away from switching digital traces and use a solid ground plane under the TQFP. The QFN (/ML) variant needs an exposed-pad via array to ground for thermal and return-path performance; the TQFP (/PT) does not.
MCLR, programmed via ICSP through MPLAB ICD/PICkit, must not be pulled to 5 V - keep the programming header on the 3.3 V domain. Do not assume the /PT (TQFP) and /ML (QFN) footprints are interchangeable; they are different land patterns for the same die. Verify the -H grade temperature range in the current datasheet ordering table before qualifying for high-temperature environments, and confirm your firmware fits the chosen Flash size if substituting 64 KB or 32 KB family members.
コンプライアンス情報
Compliance data was not present in the retrieved web data. Confirm RoHS/REACH status on the Microchip product page or datasheet packaging section.
