DSPIC33FJ128GP310T-I/PT - 16-bit 40 MIPS DSC 128KB Flash | Microchip
部品番号: DSPIC33FJ128GP310T-I/PT ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $8.42 | $8.42 |
| 10 | $7.58 | $75.80 |
| 100 | $6.74 | $674.00 |
| 500 | $6.06 | $3,030.00 |
| 1,000 | $5.46 | $5,460.00 |
DSPIC33FJ128GP310T-I/PT 概要
A digital signal controller (DSC) is a single-chip device that merges the control flow of a microcontroller with the mathematical throughput of a DSP. Within the power-management hierarchy of embedded systems, the dsPIC33F family sits between general-purpose PIC microcontrollers and dedicated DSPs, providing deterministic interrupt latency, hardware multiply-accumulate units, and rich peripherals on one die.
Key differentiators include the 16-bit modified Harvard architecture with DSP engine (single-cycle MAC, 40-bit accumulators), 128 KB of self-programmable FLASH, 85 general-purpose I/O on the 100-pin variant, and the industrial temperature range of -40C to +85C indicated by the I suffix. The /PT suffix identifies the 100-pin TQFP package in tape-and-reel delivery for automated assembly.
Architecturally, the device pairs a pipelined C compiler-friendly core with peripherals such as high-speed PWM, advanced analog (ADC), and serial interfaces (UART, SPI, I2C), enabling single-chip control of motor drives, power conversion, and precision sensing loops. The GP (General Purpose) subfamily emphasizes analog and communication peripherals over the motor-control-focused MC variants.
Typical applications include digital power supplies and PFC stages, sensor acquisition and signal-conditioning nodes, industrial automation controllers, and general embedded systems that benefit from DSP-grade math without a second processor.
When designing in this part, budget the 3.3V rail carefully: all I/O are 3.3 V only (5 V tolerance is absent in this family), and decoupling of every VDD/VSS pair plus the internal regulator capacitor is required per the manufacturer datasheet.
This page consolidates distributor stock signals, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: DSPIC33FJ128GP310T-I/PT — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33FJ128GP310T-I/PT （同一形状・フットプリント） — 相違点: Package, Core Architecture, Programming Interface, Series, Packaging.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33FJ128GP310-I/PT
✅ ドロップイン✓ 在庫あり
$4.4 / 個
データシートを見る →DSPIC33FJ128GP310A-I/PT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ128GP310A-I/PF
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$5.7 / 個
データシートを見る →DSPIC33FJ64GP310-I/PT
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$5.48 / 個
データシートを見る →DSPIC33FJ256GP310-I/PT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ128GP306-I/PT
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$4.55 / 個
データシートを見る →DSPIC33FJ128GP310T-I/PT 最大定格＆電気的特性
| Core Architecture | 16-bit dsPIC33F RISC with DSP engine |
| Max CPU Speed | 40 MIPS |
| Program Memory (FLASH) | 128 KB (128K x 8) |
| RAM Size | 16 KB |
| 電源電圧 | 3 V to 3.6 V |
| 動作温度 | -40C to +85C (Industrial) |
| パッケージ | 100-TQFP (12x12 mm) |
| 実装タイプ | Surface Mount |
| I/O Ports | 51 I/O available (package dependent) |
| Timers | General purpose timers per dsPIC33FJ family |
| Serial Interfaces | UART, SPI, I2C |
| Analog Peripherals | ADC (advanced analog, GP subfamily) |
| Packaging | Tape and Reel (T prefix) |
| RoHS ステータス | Compliant / Lead free |
| Programming Interface | ICSP (In-Circuit Serial Programming), 2-wire |
| Series | dsPIC33FJ128GP (General Purpose) |
DSPIC33FJ128GP310T-I/PT 100-tqfp (12x12 mm) ピン配置ガイド
DSPIC33FJ128GP310T-I/PT (100-tqfp (12x12 mm) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: DSPIC33FJ128GP310T-I/PT.
詳細は データシート をご参照ください。
主な用途
DSPIC33FJ128GP310T-I/PT の用途: 6 件s: Digital Power Conversion, Industrial Automation Controllers, Sensor Acquisition and Signal Conditioning, Motor Drive Control, Embedded Communication Nodes, Test and Measurement Instrumentation.
Digital Power Conversion
The DSPIC33FJ128GP310T-I/PT's 40 MIPS core with single-cycle MAC and 40-bit accumulators executes current- and voltage-loop control mathematics fast enough for digital SMPS, PFC, and DC-DC stages. The dsPIC33FJ GP family high-speed PWM generates precisely timed switching edges, while the on-chip ADC samples feedback with low jitter. Placed as the sole supervisory controller, it replaces analog compensation networks with firmware, enabling adaptive gain scheduling and soft-start control. Designers must budget FLASH for compensator state machines and verify PWM resolution against switching frequency before layout freeze.
おすすめ
Industrial Automation Controllers
In factory automation nodes, the DSPIC33FJ128GP310T-I/PT combines 51 usable I/O, multiple UART/SPI/I2C ports, and 128 KB of self-programmable FLASH, letting one chip handle sensor polling, actuator drive, and fieldbus communication. The industrial -40C to +85C rating survives panel and machine-mount environments, and ICSP allows firmware field updates without desoldering. Its DSP engine accelerates filtering of noisy encoder and analog feedback signals. Consider the A-silicon variants to inherit errata corrections, and plan the 3.3 V-only I/O interfaces with level shifters where 5 V legacy peripherals are present.
おすすめ
Sensor Acquisition and Signal Conditioning
The GP (General Purpose) subfamily emphasizes advanced analog, making the DSPIC33FJ128GP310T-I/PT well suited for multi-channel data acquisition: the ADC digitizes sensor inputs while the DSP MAC engine runs FIR/IIR filters, RMS computations, and FFT-based analysis in real time at 40 MIPS. 128 KB FLASH retains calibration tables and logging buffers, and 16 KB RAM supports moderate buffering. UART or SPI streams results to a host. Designers should confirm exact ADC channel count and sampling rate in the family datasheet and keep analog routing away from the PWM pins for best noise performance.
おすすめ
Motor Drive Control
Although the MC subfamily is purpose-built for motors, the DSPIC33FJ128GP310T-I/PT still supports PWM-based drive of BLDC/PMSM stages up to moderate complexity, computing FOC-style transformations on its 40 MIPS DSP core. The 100-pin package exposes enough PWM and ADC pins for three-phase sensing. For demanding motor control with complementary PWM and dead-time hardware, designers should compare the DSPIC33EP64MC504 variants - same ecosystem and toolchain, motor-centric peripherals. Using the GP310 keeps PCB reuse across product lines sharing a common controller footprint and 3.3 V power architecture.
おすすめ
Embedded Communication Nodes
With multiple UART, SPI, and I2C peripherals on a single die, the DSPIC33FJ128GP310T-I/PT serves as protocol converters, gateways, and sensor-bus masters. The 40 MIPS core sustains line-rate UART throughput with CRC and framing computed in software, while DMA-free interrupt service is manageable given deterministic dsPIC33F interrupt latency. 128 KB FLASH accommodates stacked protocol stacks and OTA-style update loaders. Because I/O is strictly 3.0-3.6 V, RS-232/RS-485 transceivers must be 3.3 V-compatible or level-shifted; the ICSP port doubles as the field firmware channel.
おすすめ
Test and Measurement Instrumentation
Bench instruments and handheld meters benefit from the DSPIC33FJ128GP310T-I/PT's combination of 40 MIPS DSP math for RMS/THD computation, on-chip ADC for digitization, and generous I/O for keypad and display interfaces. The 100-pin TQFP gives layout flexibility to separate analog ground from digital switching, improving measurement resolution. Firmware fits comfortably in 128 KB FLASH including calibration and UI code. Battery-powered designs should exploit low-power idle/sleep states documented in the family reference manual, and the industrial temperature grade keeps specifications stable in field service environments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33FJ128GP310T-I/PT — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33FJ128GP310-I/PT | DSPIC33FJ128GP310A-I/PT | DSPIC33FJ64GP310-I/PT | DSPIC33FJ256GP310-I/PT |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 100-TQFP (12x12) | 100-TQFP (12x12) - same | 100-TQFP (12x12) - same | 100-TQFP (12x12) - same | 100-TQFP (12x12) - same |
| FLASH Program Memory | 128 KB | 128 KB | 128 KB | 64 KB | 256 KB |
| CPU Performance | 40 MIPS (16-bit) | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Supply Voltage | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
| Operating Temperature | -40C to +85C (I grade) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Silicon Revision | Original (non-A) | Original | A revision (errata corrected) | Original | Original |
| Packaging Format | Tape & Reel | Tray | Tape & Reel | Tape & Reel | Tape & Reel |
| RoHS / Lead Free | Compliant / Yes | Compliant / Yes | Compliant / Yes | Compliant / Yes | Compliant / Yes |
主な差別化要因
- Errata-corrected A-silicon available in the same footprint （vs DSPIC33FJ128GP310A-I/PT)
- FLASH scaling without PCB redesign （vs DSPIC33FJ256GP310-I/PT)
- Tape-and-reel delivery for high-volume assembly （vs DSPIC33FJ128GP310-I/PT)
設計ノート
The dsPIC33FJ requires an external low-ESR capacitor (nominally 10 uF, ceramic) on the internal regulator output pin (VCAP/VDDCORE). Omitting it or using an undersized part causes brown-out resets and unreliable flash writes. Decouple every VDD/VSS pair with 0.1 uF ceramics placed within 2 mm of the pins, plus bulk 4.7-10 uF per power domain. Estimated: with typical 50 mA core + I/O current at 3.3 V, a 3.3 V rail regulator should be sized with at least 2x margin (100 mA) per controller.
All I/O on this family is 3.0-3.6 V only - there is no 5 V tolerance. Interfacing to 5 V sensors or legacy RS-232 logic requires level translators or 3.3 V-compatible transceivers. Keep the analog ADC inputs routed on a quiet island away from PWM and clock traces; use the dsPIC33F configuration bits to enable digital filtering where the peripheral supports it. For long SPI runs, series-terminate near the driver (22-33 ohm) to damp reflections.
Early non-A dsPIC33FJ silicon carries published errata affecting certain peripherals; check the Microchip errata sheet for your device revision and prefer the DSPIC33FJ128GP310A variants in new designs. Also verify oscillator configuration: the PLL multiplier settings must produce Fcy = Fosc/2 with Fosc <= 80 MHz (40 MIPS ceiling); out-of-range PLL configs simply fail to start. Reserve the ICSP pins (PGD/PGC/MCLR) on a header in production layouts - retrofitting debug access to a sealed 100-TQFP assembly is impractical.
コンプライアンス情報
Distributor records (Infinity Electron, ABC Semi) state Lead free / RoHS Compliant. REACH and halogen-free status not stated in provided data - verify on Microchip's environmental compliance page.
