DSPIC33FJ64GP708A-I/PT - 16-bit 40 MIPS DSC 64KB Flash | Microchip
部品番号: DSPIC33FJ64GP708A-I/PT ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.42 | $6.42 |
| 10 | $5.78 | $57.80 |
| 100 | $5.12 | $512.00 |
| 500 | $4.65 | $2,325.00 |
| 1,000 | $4.18 | $4,180.00 |
DSPIC33FJ64GP708A-I/PT 概要
A Digital Signal Controller blends the control peripherals of a microcontroller with the math acceleration of a DSP in a single chip. Within the power-management hierarchy of embedded processors, the dsPIC33FJ family sits between basic 16-bit MCUs (PIC24) and dedicated DSPs, offering DSP engine instructions, a hardware MAC, and seamless migration paths to PIC24H MCUs and dsPIC30F DSCs.
Key features include 40 MIPS core performance, 64 KB flash with self-programming capability, 16 KB SRAM, dual 4-wire SPI ports, two I2C ports, two UARTs, up to eight input capture and eight output compare channels, and a 5V-tolerant digital I/O structure. The A revision improves flash endurance and reliability over the original dsPIC33FJ64GP708.
Technically, the modified Harvard architecture executes most instructions in a single cycle, while the DSP engine performs single-cycle MAC with dual data fetch, 40-bit wide accumulators, and barrel shifting. Two 3-wire 16-bit program/ICSP interfaces (PGECx/PGEDx pairs) enable in-circuit debugging and programming via MPLAB ICD 3, REAL ICE, PICkit 3, or MPLAB Snap.
Typical applications include digital power supplies and PFC loops, motor control (BLDC, PMSM, induction), LED lighting drivers, and sensor acquisition systems. The 85-C industrial temperature range (I grade) covers most factory environments.
Design tip: all VDD/VSS pairs must be decoupled with 0.1 uF ceramics, and the VCAP/VDDCORE pin requires a low-ESR 10 uF capacitor plus a 0.1 uF bypass - omitting this is the most common bring-up failure.
This page synthesizes distributor pricing, verified drop-in alternatives, pinout data, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: DSPIC33FJ64GP708A-I/PT — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33FJ64GP708A-I/PT （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Core Architecture, Packaging, Supply Voltage.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33FJ128GP708A-I/PT
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$11.8 / 個
データシートを見る →DSPIC33FJ256GP708A-I/PT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ32GP708A-I/PT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ64GP708A-E/PT
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →DSPIC33FJ64GP708-I/PT
✅ ドロップイン✓ 在庫あり
$6.35 / 個
データシートを見る →DSPIC33FJ64GP708A-I/PT 最大定格＆電気的特性
| Core Architecture | 16-bit modified Harvard (DSC) |
| Core Speed | 40 MIPS |
| Program Memory (Flash) | 64 KB (22 Kwords) |
| SRAM | 16 KB |
| Operating Voltage | 3.0 V to 3.6 V |
| 動作温度 | -40C to +85C (I grade) |
| パッケージ | 80-pin TQFP (PT), 12 x 12 mm |
| 実装タイプ | Surface Mount |
| I/O Pins | Up to 66 digital I/O |
| ADC | 10-bit, 1.1 Msps, multi-channel |
| UART | 2 |
| SPI | 2 (4-wire) |
| I2C | 2 |
| Input Capture / Output Compare | 8 IC / 8 OC |
| Timers | Type A and Type B 16-bit timers |
| Debug/Programming | ICSP via PGECx/PGEDx pairs, 2-wire |
| DSP Engine | Single-cycle MAC, dual 40-bit accumulators |
| Supply Class | 3.3 V |
DSPIC33FJ64GP708A-I/PT ピン構成
| ピン 1 | AN0/VREF+/CN2/RB0 — Analog input 0 / positive voltage reference / change notification / port B |
| ピン 2 | AN1/VREF-/CN3/RB1 — Analog input 1 / negative voltage reference / change notification / port B |
| ピン 3 | AN2/SS1/CN4/RB2 — Analog input 2 / SPI1 slave select / port B |
| ピン 4 | AN3/INDX/CN5/RB3 — Analog input 3 / QEA index input / port B |
| ピン 5 | AN4/QEA/IC7/CN6/RB4 — Analog input 4 / QEA encoder / input capture 7 / port B |
| ピン 6 | AN5/QEB/IC8/CN7/RB5 — Analog input 5 / QEB encoder / input capture 8 / port B |
| ピン 7 | AN6/OCFA/RB6 — Analog input 6 / output compare fault A / port B |
| ピン 7 | AN6/OCFA/RB6 — Analog input 6 / output compare fault A / port B |
| ピン 8 | AN7/PGD/RB7 — Analog input 7 / programming data / port B |
| ピン 9 | AN8/PGC/RB8 — Analog input 8 / programming clock / port B |
| ピン 10 | AN9/RB9 — Analog input 9 / port B |
| ピン 11 | VDD — Power supply 3.3V |
| ピン 12 | VSS — Ground reference |
| ピン 13 | AN10/T2CK/RC0 — Analog input 10 / Timer2 clock / port C |
| ピン 14 | AN11/T3CK/RC1 — Analog input 11 / Timer3 clock / port C |
| ピン 15 | AN12/U1RTS/SDO2/RC2 — Analog input 12 / UART1 RTS / SPI2 data out / port C |
| ピン 16 | AN13/U1CTS/SDI2/RC3 — Analog input 13 / UART1 CTS / SPI2 data in / port C |
| ピン 17 | PGD2/AN14/SCK2/CN9/RC4 — Programming data 2 / analog input 14 / SPI2 clock / port C |
| ピン 18 | PGC2/AN15/CN10/RC5 — Programming clock 2 / analog input 15 / port C |
| ピン 19 | VDD — Power supply 3.3V |
| ピン 20 | VSS — Ground reference |
| ピン 21 | TMS/RC6 — JTAG test mode select / port C |
| ピン 22 | TCK/RC7 — JTAG test clock / port C |
| ピン 23 | TDO/SDO1/RF1 — JTAG test data out / SPI1 data out / port F |
| ピン 24 | TDI/RF2 — JTAG test data in / port F |
| ピン 25 | U1RX/RF2 — UART1 receive / port F |
| ピン 26 | U1TX/RF3 — UART1 transmit / port F |
| ピン 27 | SDA2/RF4 — I2C2 data / port F |
| ピン 28 | SCL2/RF5 — I2C2 clock / port F |
| ピン 29 | VSS — Ground reference |
| ピン 30 | VDD — Power supply 3.3V |
| ピン 31 | SDA1/RF6 — I2C1 data / port F |
| ピン 32 | SCL1/RF7 — I2C1 clock / port F |
| ピン 33 | SCK1/RF8 — SPI1 clock / port F |
| ピン 34 | U2TX/RF10 — UART2 transmit / port F |
| ピン 35 | U2RX/RF11 — UART2 receive / port F |
| ピン 36 | RF12 — General purpose I/O port F |
| ピン 37 | RF13 — General purpose I/O port F |
| ピン 38 | SDI1/RF7 — SPI1 data in / port F (remappable) |
| ピン 39 | SS1/RF6 — SPI1 slave select / port F (remappable) |
| ピン 40 | RG0 — General purpose I/O port G |
| ピン 41 | RG1 — General purpose I/O port G |
| ピン 42 | VSS — Ground reference |
| ピン 43 | VDD — Power supply 3.3V |
| ピン 44 | OC1/RD0 — Output compare 1 / port D |
| ピン 45 | OC2/RD1 — Output compare 2 / port D |
| ピン 46 | OC3/RD2 — Output compare 3 / port D |
| ピン 47 | OC4/RD3 — Output compare 4 / port D |
| ピン 48 | OC5/RD4 — Output compare 5 / port D |
| ピン 49 | OC6/RD5 — Output compare 6 / port D |
| ピン 50 | OC7/RD6 — Output compare 7 / port D |
| ピン 51 | OC8/RD7 — Output compare 8 / port D |
| ピン 52 | VSS — Ground reference |
| ピン 53 | IC1/RD8 — Input capture 1 / port D |
| ピン 54 | IC2/RD9 — Input capture 2 / port D |
| ピン 55 | IC3/RD10 — Input capture 3 / port D |
| ピン 56 | IC4/RD11 — Input capture 4 / port D |
| ピン 57 | IC5/RD12 — Input capture 5 / port D |
| ピン 58 | IC6/RD13 — Input capture 6 / port D |
| ピン 59 | RTCC/RG2 — Real-time clock alarm / port G |
| ピン 60 | RG3 — General purpose I/O port G |
| ピン 61 | PGED3/RG4 — Programming data 3 / port G |
| ピン 62 | PGEC3/RG5 — Programming clock 3 / port G |
| ピン 63 | VDD — Power supply 3.3V |
| ピン 64 | VSS — Ground reference |
| ピン 65 | MCLR — Master clear reset (active low), programming mode entry |
| ピン 66 | RA0 — General purpose I/O port A |
| ピン 67 | RA1 — General purpose I/O port A |
| ピン 68 | PGED1/AN16/CN11/RA2 — Programming data 1 / analog input 16 / port A |
| ピン 69 | PGEC1/AN17/CN12/RA3 — Programming clock 1 / analog input 17 / port A |
| ピン 70 | VCAP/VDDCORE — Core voltage regulator output - requires 10 uF low-ESR capacitor to VSS |
| ピン 71 | OSC1/CLKI/RA2 — Oscillator crystal input / external clock input |
| ピン 72 | OSC2/CLKO/RA3 — Oscillator crystal output / clock output |
| ピン 73 | RA4 — General purpose I/O port A |
| ピン 74 | RA5 — General purpose I/O port A |
| ピン 75 | ENVREG — Voltage regulator enable - tie to VDD for internal regulator or to VSS for external 3.3V core supply |
| ピン 76 | VDD — Power supply 3.3V |
| ピン 77 | VSS — Ground reference |
| ピン 78 | RA9 — General purpose I/O port A |
| ピン 79 | RA10 — General purpose I/O port A |
| ピン 80 | AVDD — Analog power supply (3.3V) for ADC |
主な用途
DSPIC33FJ64GP708A-I/PT の用途: 6 件s: Digital Power Supplies, BLDC / PMSM Motor Control, LED Lighting Drivers, Industrial Data Acquisition and Sensor Hubs, Audio and Signal Processing Front Ends, Embedded Control and IoT Nodes.
Digital Power Supplies
The DSPIC33FJ64GP708A-I/PT fits digital SMPS and PFC control because its 40 MIPS core executes single-cycle MAC operations that close fast voltage and current loops with deterministic latency, while the 10-bit 1.1 Msps ADC samples the power stage synchronized to the PWM cycle. In a typical topology, ADC results trigger control-loop ISR execution and output compare/PWM peripherals drive the MOSFET gate stage, giving cycle-by-cycle current limiting in firmware. Because the entire 80-pin device runs from a 3.3V rail with 5V-tolerant inputs, it interfaces directly with common gate drivers and feedback dividers. The 64 KB flash accommodates multi-mode control (CCM, DCM, burst) plus compensation and fault management without external memory.
おすすめ
BLDC / PMSM Motor Control
For motor drives, the DSPIC33FJ64GP708A-I/PT provides eight output compare channels for six-step or sinusoidal commutation and eight input capture channels for hall-sensor or encoder feedback. The DSP engine executes Clarke and Park transforms for field-oriented control with single-cycle MAC throughput at 40 MIPS, allowing current loops running at 20 kHz switching to complete in a fraction of the PWM period. The 3.0V to 3.6V core interfaces to gate drivers through level-shifted logic, and the -40C to +85C industrial rating covers most drive enclosures. With 16 KB SRAM, sensorless algorithms with state observers fit without external RAM.
おすすめ
LED Lighting Drivers
In high-power LED systems, the DSPIC33FJ64GP708A-I/PT implements constant-current control, dimming (PWM and analog), color mixing, and DALI or DMX protocol handling concurrently. The eight output compare channels generate multi-channel dimming PWMs with hardware precision, while the 1.1 Msps ADC monitors output current, LED forward voltage, and temperature for protection. The 40 MIPS core has ample headroom to run communications protocols alongside the control loop on a single chip, replacing discrete MCU-plus-DSP solutions. Its 85C industrial rating suits enclosed luminaire drivers, and the 80-pin TQFP provides enough I/O for large multi-string fixtures.
おすすめ
Industrial Data Acquisition and Sensor Hubs
As a sensor hub, the DSPIC33FJ64GP708A-I/PT combines a multi-channel 10-bit ADC sampling up to 1.1 Msps with dual SPI and dual I2C ports for external precision ADCs, and dual UARTs for RS-485/Modbus field connectivity. The DSP engine performs windowed filtering and FFT-based diagnostics locally at 40 MIPS, reducing data traffic to a supervisory controller. Up to 66 general-purpose I/O pins on the 80-pin TQFP handle relay control, limit switches, and front-panel interfaces in one footprint. The -40C to +85C range and 3.3V operation with 5V-tolerant inputs simplify integration into legacy industrial signal chains.
おすすめ
Audio and Signal Processing Front Ends
The GP-family DSPIC33FJ64GP708A-I/PT serves audio and biomedical front ends where sampled signal processing is required: the dual 40-bit accumulators and single-cycle MAC execute FIR/IIR filters at 40 MIPS, while dual SPI ports stream data to external audio codecs or SD/SD-card storage. The 1.1 Msps ADC covers instrumentation channels, and eight input capture channels timestamp event signals for acoustic analytics. With 64 KB flash and 16 KB SRAM, complete filter banks and protocol stacks reside on chip. The single 3.3V rail and low peripheral count reduce BOM cost compared to a DSP-plus-MCU two-chip solution.
おすすめ
Embedded Control and IoT Nodes
For general embedded control and connected nodes, the DSPIC33FJ64GP708A-I/PT offers a balanced profile: 40 MIPS of headroom for protocol stacks (Modbus, CAN via external transceiver, or software-defined serial), 64 KB flash for bootloader plus application, and rich timers for scheduling and measurement. ICSP debugging through MPLAB Snap or REAL ICE keeps development fast, and seamless migration to PIC24H or higher-density dsPIC33FJ parts protects the PCB investment as requirements grow. The 80-pin TQFP with 66 I/O lines handles HMI buttons, displays, and actuators directly, making it a cost-effective single-chip controller for industrial IoT gateways and equipment controllers.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33FJ64GP708A-I/PT — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33FJ128GP708A-I/PT | DSPIC33FJ256GP708A-I/PT | DSPIC33FJ32GP708A-I/PT | DSPIC33FJ64GP708A-E/PT | DSPIC33FJ64GP708-I/PT |
|---|---|---|---|---|---|---|
| Package | 80-pin TQFP (PT), 12 x 12 mm | 80-pin TQFP (PT) - same | 80-pin TQFP (PT) - same | 80-pin TQFP (PT) - same | 80-pin TQFP (PT) - same | 80-pin TQFP (PT) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core Speed | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Flash Memory | 64 KB | 128 KB | 256 KB | 32 KB | 64 KB | 64 KB |
| Operating Temperature | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) | -40C to +125C (E) | -40C to +85C (I) |
| Silicon Revision | A revision (improved) | A revision | A revision | A revision | A revision | Original (non-A) |
| Communication Ports | 2x UART, 2x SPI, 2x I2C | 2x UART, 2x SPI, 2x I2C | 2x UART, 2x SPI, 2x I2C | 2x UART, 2x SPI, 2x I2C | 2x UART, 2x SPI, 2x I2C | 2x UART, 2x SPI, 2x I2C |
| Lifecycle Status | Active | Active | Active | Active | Active | Active (superseded by A version) |
主な差別化要因
- Best price/performance in the GP708A family for 64 KB designs （vs DSPIC33FJ128GP708A-I/PT)
- A-revision silicon reliability （vs DSPIC33FJ64GP708-I/PT)
- Extended temperature availability in same footprint （vs DSPIC33FJ64GP708A-E/PT)
- DSC capability vs plain MCU alternatives （vs PIC24HJ64GP504-I/PT (functional alternative, different package))
設計ノート
The dsPIC33FJ64GP708A integrates an on-chip 3.3V-to-1.8V core regulator whose output appears on the VCAP/VDDCORE pin. Fit a low-ESR 10 uF tantalum or ceramic plus a 0.1 uF ceramic capacitor directly at this pin. If ENVREG is tied to VDD the regulator is enabled; tying ENVREG to VSS disables it, requiring an external clean core supply. All VDD/VSS pairs (multiple around the 80-pin ring) each need their own 0.1 uF decoupling capacitor placed within 2-3 mm of the pin.
ICSP programming uses PGECx/PGEDx pin pairs - the device has multiple pairs (PGEC1/PGED1, PGEC2/PGED2, PGEC3/PGED3), and the clock and data must come from the SAME pair; mixing PGEC2 with PGED1 will fail programming. Do not load PGECx/PGEDx pins with heavy capacitive loads or pull-downs that could violate ICSP timing. Also note the original dsPIC33FJ64GP708 (non-A) is documented by third parties as having very low flash endurance (guaranteed only ~100 erase/write cycles), another reason to standardize on the A revision.
For motor control and digital power firmware, route PWM outputs (OC1-OC8 on port D) away from analog inputs AN0-AN16 and keep AVDD (pin 80) filtered with an RC (e.g., 10 ohm + 0.1 uF) from VDD to supply a quiet analog rail. The QEA/QEB/INDX quadrature pins on RB3-RB5 should be treated as fast digital signals with short returns. Use a solid ground plane under the TQFP and stitch VSS vias near each VSS pin for low-inductance return paths.
Estimated: at 40 MIPS with all peripherals active, core current is typically on the order of tens of mA from 3.3V, giving power dissipation well under 0.5 W in the 12 x 12 mm TQFP; theta_JA of a standard 4-layer board keeps junction rise below 25C at 85C ambient, comfortably within the I-grade rating. For high-pin-count I/O switching at full drive, verify with Microchip power estimation tools, but heatsinking is not required for this device class.
コンプライアンス情報
Standard Microchip catalog device in lead-free TQFP package; RoHS/REACH statements per Microchip product page for this MPN. Not an automotive AEC-Q100 qualified part.