EP20K100BC356-1 - APEX-20K FPGA 100K Gates 356-BGA | Intel
部品番号: EP20K100BC356-1 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132 | $1,320.00 |
| 100 | $118.5 | $11,850.00 |
| 500 | $105 | $52,500.00 |
| 1,000 | $92.75 | $92,750.00 |
EP20K100BC356-1 概要
An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit that can be configured by the customer or designer after manufacturing to implement any digital logic function. FPGAs sit in the programmable logic hierarchy above CPLDs (Complex Programmable Logic Devices) and below fixed-function ASICs (Application-Specific Integrated Circuits), and they are widely used in telecommunications, video processing, and DSP prototyping where time-to-market and design flexibility outweigh pure unit-cost minimization. The APEX-20K family was introduced as one of the first multi-tier, fine-grained programmable fabrics with embedded array blocks and high-speed LVDS-capable I/O.
The EP20K100BC356-1 features 252 user I/O pins, 4,160 logic elements, 53,248 bits of embedded RAM, and a propagation delay of 1.6 ns at the standard -1 speed grade. It is housed in a 356-ball LBGA (Large Ball Grid Array) package measuring 35 mm by 35 mm with a 1.27 mm pitch. The device operates from a 1.71 V to 1.89 V core supply (typical 1.8 V) with separate VCCIO banks for I/O voltage flexibility. Per the device suffix, the speed grade is -1 (standard, slowest of three grades) and the operating temperature range is commercial 0 C to 85 C.
Architecturally, the EP20K100BC356-1 combines a fine-grained LUT-based logic array with embedded system blocks (ESBs) that can be configured as RAM, ROM, or content-addressable memory. This dual-fabric architecture makes it well suited to designs that mix datapath logic with on-chip memory. The device supports JTAG (IEEE 1149.1) boundary-scan and can be configured via passive serial, passive parallel, or synchronous configuration modes.
Typical applications include high-speed telecom data-path processing, video and image preprocessing, glue-logic integration around microprocessors, DSP co-processing, and industrial control backplanes. The wide operating voltage range and rich I/O count make it a fit for designs bridging legacy and modern buses. Because the part is in the APEX-20K family (launched circa 1999), most new designs target Cyclone, Arria, or Stratix equivalents; existing designs are typically maintained through Rochester Electronics or licensed second-source channels.
When designing with this device, ensure decoupling follows the Altera reference board layout - one bulk 47 uF or larger tantalum plus a 0.1 uF ceramic per VCC pin pair is typical. JTAG chain integrity and configuration mode selection (MSEL pins) must be verified before board bring-up. A heatsink or forced-air cooling is generally not required because static CMOS logic dissipates power primarily during switching.
This page synthesizes distributor pricing from Octopart, Mouser, and DigiKey, drop-in alternatives from the same APEX-20K family and compatible AMD/Xilinx Spartan-class devices, and practical design notes not found in the original APEX-20K datasheet alone.
ドロップイン代替品: EP20K100BC356-1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP20K100BC356-1 （同一形状・フットプリント） — 相違点: Process Technology, Speed Grade, Package, Operating Temperature, Mounting Type.
クイック比較ツール — 並列比較する代替部品を選択:
EP20K100BC356-1V
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP20K100BC356-1X
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP20K100EBC356-2
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP20K100EBC356-1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP20K100BC356-3V
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP20K100BC356-1 最大定格＆電気的特性
| Series | APEX-20K |
| Device Type | Field Programmable Gate Array (FPGA) |
| Logic Elements / Cells | 4160 |
| Total RAM Bits | 53248 |
| User I/O Count | 252 |
| Number of Gates | 100000 (typical) |
| Propagation Delay | 1.6 ns |
| Speed Grade | -1 |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V typical) |
| 動作温度 | 0 C to 85 C (commercial) |
| Package Type | 356-LBGA (Large BGA) |
| Package Dimensions | 45 x 45 mm, 1.27 mm pitch |
| 実装タイプ | Surface Mount |
| Process Technology | 0.15 micrometer all-layer copper CMOS |
| Configuration Interface | JTAG (IEEE 1149.1), passive serial/parallel |
EP20K100BC356-1 45 x 45 mm, 1.27 mm pitch ピン配置ガイド
EP20K100BC356-1 (45 x 45 mm, 1.27 mm pitch パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP20K100BC356-1.
詳細は データシート をご参照ください。
主な用途
EP20K100BC356-1 の用途: 6 件s: Telecom Data-Path Processing, Video and Image Preprocessing, DSP Co-Processing and Hardware Acceleration, Industrial Control Backplane Glue Logic, Legacy Communication Infrastructure Sustainment, Test and Measurement Front-End Logic.
Telecom Data-Path Processing
The EP20K100BC356-1 fits telecom backplane data-path processing where 100K gates of logic and 53,248 bits of embedded RAM are sufficient for a single line-card or framer function. Its 252 user I/O pins support multiple parallel bus interfaces (UTOPIA, POS-PHY, or proprietary telecom buses) without external mux logic, and the 1.6 ns propagation delay at -1 speed grade is adequate for 60-80 MHz state-machine operation. In production cards, the device is paired with a TI TMS320C6x DSP or a PowerPC host CPU, with the FPGA implementing glue logic, FIFO buffers, and protocol adaptation layers. The APEX-20K embedded system blocks (ESBs) are configured as dual-port RAM for cell buffering at line rates up to 155 Mbps, which is why the part remains in service on legacy STM-1/OC-3 line cards.
おすすめ
Video and Image Preprocessing
The EP20K100BC356-1 is well suited to video preprocessing blocks that require real-time pixel pipeline and frame buffering. With 53,248 embedded RAM bits distributed across multiple ESBs, the device can hold at least one full CIF-resolution (352x288) frame buffer on-chip, eliminating an external SRAM in cost-sensitive designs. The 252 I/O pins support 16-bit video buses plus ITU-R BT.656 or parallel RGB interfaces. The 1.6 ns propagation delay allows pixel-clock rates up to about 60 MHz, covering NTSC/PAL and SDTV video rates. Pairing the FPGA with a video ADC such as the ADV7181 or a DAC such as the ADV7171 forms a complete video capture or playback subsystem, with the APEX-20K implementing color-space conversion and deinterlacing in hardware.
おすすめ
DSP Co-Processing and Hardware Acceleration
The EP20K100BC356-1 serves as a hardware accelerator alongside a general-purpose DSP in latency-sensitive DSP co-processing applications. The 4,160 logic elements provide enough capacity for FFT butterflies, Viterbi decoders, or FIR filter arrays that would otherwise consume 30-50 percent of a DSP core's cycles. The ESBs configured as dual-port RAM implement coefficient tables and circular buffers needed by streaming DSP algorithms. With 252 I/O pins, the FPGA interfaces to the DSP's external memory interface (EMIF) and host-port bus without glue logic. A representative design pairs the EP20K100BC356-1 with a TMS320C6701 DSP at 100 MHz, where the FPGA offloads a 256-point FFT and reduces DSP load by 40 percent.
おすすめ
Industrial Control Backplane Glue Logic
The EP20K100BC356-1 is used in industrial PLC and backplane designs where it integrates multiple bus protocols (VME, CompactPCI, or proprietary industrial buses) into a single programmable bridge. The 252 I/O pins allow direct interfacing to 8-bit and 16-bit parallel buses without external transceivers, and the 53,248 embedded RAM bits implement FIFO buffers and command queues for asynchronous bus conversion. The commercial 0-85 C operating range suits factory-floor enclosures, while the 1.6 ns propagation delay accommodates standard 33 MHz PCI or VME64 bus rates. Production boards pair the FPGA with a microcontroller such as the Motorola MPC860 or an Intel i960 host processor for protocol translation.
おすすめ
Legacy Communication Infrastructure Sustainment
The EP20K100BC356-1 is predominantly used today as a sustainment part for legacy communication infrastructure where board re-design is impractical due to long qualification cycles. Long-life programs in defense, aerospace, and telecom central offices rely on Rochester Electronics and authorized distributors to maintain supply of the original APEX-20K device. The 1.6 ns propagation delay and 100K-gate density match the original design specification, so no firmware or timing closure changes are needed when replacing a board. The same firmware bitstream loads unchanged into EP20K100BC356-1, EP20K100BC356-1V, and EP20K100EBC356-2 variants, simplifying long-term inventory management.
おすすめ
Test and Measurement Front-End Logic
The EP20K100BC356-1 is well matched to test and measurement equipment front ends where it implements custom trigger logic, pattern generators, and protocol-aware decode engines. The 4,160 logic elements allow a single FPGA to handle multiple parallel instrument channels, while the 53,248 bits of embedded RAM buffer captured waveform segments at sample rates up to 200 MSPS. The 252 I/O pins fan out to multiple ADC and DAC channels without external mux logic. In a typical oscilloscope or logic-analyzer design, the FPGA is paired with an 8-bit 200 MSPS ADC such as the AD9288 and a high-speed comparator array, with the APEX-20K implementing peak detection and decimation in hardware.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP20K100BC356-1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP20K100BC356-1V | EP20K100BC356-1X | EP20K100EBC356-2 | EP20K100EBC356-1 | EP20K100BC356-3V |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 356-LBGA (35x35 mm, 1.27 mm pitch) | 356-LBGA (35x35 mm) - same | 356-LBGA (35x35 mm) - same | 356-LBGA (35x35 mm) - same | 356-LBGA (35x35 mm) - same | 356-LBGA (35x35 mm) - same |
| Series | APEX-20K | APEX-20K | APEX-20K | APEX-20K | APEX-20K | APEX-20K |
| Logic Elements | 4160 | 4160 | 4160 | 4160 | 4160 | 4160 |
| Total RAM Bits | 53248 | 53248 | 53248 | 53248 | 53248 | 53248 |
| User I/O Count | 252 | 252 | 252 | 252 | 252 | 252 |
| Speed Grade | -1 | -1 | -1 | -2 (faster) | -1 | -3 (fastest) |
| Core Voltage | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.8 V (lower-power E process) | 1.8 V (lower-power E process) | 1.71-1.89 V |
| Lifecycle Status | Obsolete | Obsolete (Rochester stock) | Obsolete (Rochester stock) | Obsolete (Rochester stock) | Obsolete (Rochester stock) | Obsolete (Rochester stock) |
主な差別化要因
- Pin-compatible with full APEX-20K 356-LBGA family （vs EP20K100EBC356-2)
- Same die across -1 and -V variants （vs EP20K100BC356-1V)
- Lower cost than -3 speed grade for legacy systems （vs EP20K100BC356-3V)
設計ノート
Place decoupling capacitors as close as possible to each VCC and VCCIO pin of the 356-LBGA. The Altera APEX-20K reference design recommends one 0.1 microfarad X7R ceramic per VCC pin plus a single 47 microfarad tantalum bulk capacitor per supply rail. Place the configuration PROG and CONFIG_DONE pull-up resistors within 1 inch of their respective pins to avoid spurious reconfiguration during power-up.
Do not exceed the maximum VCCIO of 3.6 V when driving 3.3 V LVCMOS signals; the 5 V tolerant I/O version is a different part suffix. The MSEL[2:0] pins must be tied to logic-high or logic-low through 1 kohm resistors, not left floating, otherwise the device may power up in the wrong configuration mode. JTAG TCK should be series-terminated with 33 ohm if the trace exceeds 2 inches to prevent reflection-induced configuration failures.
Static CMOS logic in the APEX-20K family dissipates power primarily during switching, so worst-case junction temperature depends on toggle rate rather than quiescent current. For the 356-LBGA package with theta_JA around 15 C/W on a 4-layer JEDEC test board, a continuous 1 W dissipation yields about 15 C junction rise above ambient, generally within the 0-85 C commercial range. Forced-air cooling is required only when the design exceeds 60-70 percent of available logic elements switching simultaneously.
Route the 252 user I/O signals in groups matching the bank voltage (VCCIO) assignments on the APEX-20K pin table; mixing 3.3 V and 2.5 V signals in the same bank will damage the device. Keep all clock inputs (CLK[3:0] and FCLK) on inner layers with ground reference and length-matched to within 100 mil of each other to minimize skew. The 356-ball BGA at 1.27 mm pitch requires microvia or via-in-pad PCB technology for reliable assembly - confirm with your board house before layout.
コンプライアンス情報
RoHS/REACH compliance status not present in the verified web data; the APEX-20K family predates RoHS requirements. AEC-Q100 is not applicable because this is a commercial-grade FPGA without automotive qualification.
