EP20K100CB356C8 - APEX-20K 100K-Gate FPGA, 356-BGA | Intel
部品番号: EP20K100CB356C8 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $128 | $1,280.00 |
| 100 | $110 | $11,000.00 |
| 500 | $95 | $47,500.00 |
| 1,000 | $82 | $82,000.00 |
EP20K100CB356C8 概要
A Field-Programmable Gate Array (FPGA) is a type of integrated circuit that can be reprogrammed after manufacture to implement arbitrary digital logic, occupying a position in the programmable-logic hierarchy between simple programmable logic devices (SPLDs/CPLDs) and application-specific integrated circuits (ASICs). Within Intel's programmable solutions portfolio, the APEX 20K family predates the Cyclone and Arria series, and is now classified as a mature legacy device. EP20K100CB356C8 occupies the lower-density tier of the APEX 20K lineup, while sharing the same Quartus development-tool ecosystem and the same embedded-memory philosophy used in subsequent families.
Key features of the EP20K100CB356C8 include 4,160 logic elements, 12 EABs providing 24 Kbits of embedded memory, a maximum of 252 user I/O pins, and four PLLs with up to six clock outputs. The device supports LVTTL, LVCMOS, SSTL, and GTL+ I/O standards via MultiVolt I/O and operates from a core supply of 1.8 V. Configuration is supported through passive serial (PS), passive parallel synchronous (PPS), passive parallel asynchronous (PPA), and JTAG modes, and the device is in-system programmable via IEEE 1532.
The 356-ball LBGA package exposes a large number of user I/O and high-speed clock pins while providing a controlled-impedance substrate for high-speed signals. The on-chip PLLs enable frequency synthesis, phase shifting, and clock-skew management, which is essential for synchronous designs with multiple clock domains. The 0.18 µm process and embedded array block architecture deliver a favourable logic-to-memory ratio for datapath-intensive designs such as DSP filters, FIFO buffers, and bus-interface bridges.
Typical applications include telecommunications line cards, industrial automation controllers, ASIC prototyping, glue-logic and bus-bridging designs, and legacy upgrades of designs that were originally implemented on APEX 20K silicon. Designers migrating to a current Intel FPGA should consider Cyclone IV/V or MAX 10 as the recommended modern equivalents, depending on logic, memory, and I/O requirements.
When designing with this device, note that the 1.8 V core supply is internally generated by an on-chip voltage regulator when the 2.5 V VCCINT is applied, but the PLL analog supply and the JTAG pull-up voltage still require dedicated rails. Ensure the JTAG chain is terminated correctly and that the configuration scheme matches the system boot timing, as the APEX 20K family uses a 16-bit-wide passive-parallel mode in addition to the more common serial modes.
ドロップイン代替品: EP20K100CB356C8 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP20K100CB356C8 （同一形状・フットプリント） — 相違点: Process Technology, Speed Grade, Package, Operating Temperature, Family.
クイック比較ツール — 並列比較する代替部品を選択:
EP20K100CB356C7
✅ ドロップイン✓ 在庫あり
$71 / 個
データシートを見る →EP20K100CB356C7ES
✅ ドロップイン✓ 在庫あり
$92 / 個
データシートを見る →EP20K100BC356-1
✅ ドロップイン✓ 在庫あり
$92.75 / 個
データシートを見る →EP20K100CB356C8N
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EP20K100CB356C8 最大定格＆電気的特性
| Family | APEX 20K |
| Logic Elements | 4,160 |
| Typical Gates | 100,000 |
| Maximum User I/O | 252 |
| Embedded Array Blocks (EABs) | 12 |
| Embedded Memory (EAB-based) | 24 Kbits |
| Phase-Locked Loops (PLLs) | 4 |
| Core Supply Voltage (VCCINT) | 1.8 V |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| パッケージ | 356-ball LBGA |
| Process Technology | 0.18 µm CMOS |
| Configuration Modes | PS / PPS / PPA / JTAG (IEEE 1532) |
| Speed Grade | C8 |
| 実装タイプ | Surface Mount (BGA) |
EP20K100CB356C8 356-ball lbga ピン配置ガイド
EP20K100CB356C8 (356-ball lbga パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP20K100CB356C8.
詳細は データシート をご参照ください。
主な用途
EP20K100CB356C8 の用途: 6 件s: Telecommunications Line Cards, Industrial Automation Controllers, ASIC Prototyping and Emulation, Glue Logic and Bus Bridging, Legacy Design Maintenance and Upgrades, DSP Co-Processor for Datapath Pipelines.
Telecommunications Line Cards
The EP20K100CB356C8 fits telecommunications line-card applications because its 4,160 logic elements and 252 user I/O pins deliver sufficient density for framer/mapper glue logic, while the 24 Kbits of embedded array-block memory implement small elastic stores and look-up tables. Its 1.8 V core and 2.5 V/3.3 V MultiVolt I/O allow direct connection to legacy TDM buses and ATM/POS PHY devices operating at 3.3 V, eliminating level-shifters on multi-rail backplanes. The four on-chip PLLs synthesize the multiple clock domains required for TDM-to-packet conversion, and the 356-ball LBGA package preserves signal integrity on the high-speed serial control plane. Designers value the JTAG-based in-system reprogrammability for field firmware updates on installed line cards.
おすすめ
Industrial Automation Controllers
The EP20K100CB356C8 is well suited to industrial automation controllers because its 100,000-gate capacity and rich I/O complement support multi-axis motion-control state machines, encoder-interface logic, and EtherCAT/CAN glue logic in a single device. The 0.18 µm CMOS process and industrial temperature screening allow reliable operation in factory-floor enclosures with ambient temperatures up to 85 °C. The 24 Kbits of EAB-based dual-port RAM implement fast PID loop tables and lookup-based trajectory generators that update every servo cycle. The 356-ball LBGA package provides 252 user I/O pins, which is enough to drive step/direction signals, opto-isolated digital inputs, and parallel ADC interfaces without an external I/O expander.
おすすめ
ASIC Prototyping and Emulation
The EP20K100CB356C8 is a practical platform for ASIC prototyping because its 4,160 logic elements, 12 EABs, and four PLLs allow engineers to map a mid-complexity ASIC (up to roughly 80,000 ASIC gates) onto a single FPGA for verification before tape-out. Embedded array blocks implement register files, FIFOs, and small dual-port RAMs that are common building blocks in ASIC designs. The 356-ball LBGA exposes enough user I/O to break out full 32-bit buses, JTAG scan chains, and multiple clock domains for ASIC pad-by-pad functional validation. Quartus II provides incremental compile flows that map specific ASIC blocks to specific EABs, preserving timing closure between successive prototype spins.
おすすめ
Glue Logic and Bus Bridging
The EP20K100CB356C8 excels at legacy bus-bridging and glue-logic tasks such as PCI-to-ISA bridges, VME-to-PCI adapters, and proprietary backplane interconnects where a custom ASIC is not justified. Its 100,000-gate capacity absorbs the address decoding, wait-state generation, and interrupt steering that surrounds legacy bus controllers. MultiVolt I/O is critical here: 5 V-tolerant inputs allow direct connection to legacy ISA or VME signals without external buffers, while 3.3 V outputs drive modern downstream ASICs. The 252 user I/O provide the wide parallel buses and handshake lines typical of bus-bridge designs without resorting to I/O multiplexing.
おすすめ
Legacy Design Maintenance and Upgrades
The EP20K100CB356C8 is most commonly used today to maintain installed APEX 20K designs in telecommunications, defense, and industrial systems where board-level redesign is not feasible. The 356-ball LBGA footprint and the Quartus II 13.0sp1 tool-chain allow field replacements using the original bitstream, and the device's mature silicon means long-term supply remains available from authorized and independent distributors. The EAB-based memory and PLL architecture behave identically across speed grades (C7, C8), so a one-to-one swap of C8 for C7 or B-1 preserves functional behavior. Designers maintaining APEX 20K boards should keep a frozen Quartus II project archive plus the original programming files to enable emergency rebuilds without re-synthesis.
おすすめ
DSP Co-Processor for Datapath Pipelines
The EP20K100CB356C8 functions as a DSP co-processor in mixed ASIC+FPGA signal-processing pipelines where the host processor cannot keep pace with sample-rate conversion, FIR/IIR filtering, or FFT preprocessing. EABs implement coefficient tables, delay lines, and circular buffers that the LUT fabric then multiplies and accumulates at full system clock rate. The four PLLs derive the multiple sample-rate clocks needed for polyphase interpolators and sigma-delta modulators. The 1.8 V core combined with 3.3 V MultiVolt I/O allows direct hand-off to downstream 3.3 V ADCs and DACs without level translation, which simplifies the analog/digital interface board design.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP20K100CB356C8 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP20K100CB356C7 | EP20K100CB356C7ES | EP20K100BC356-1 | EP20K100CB356C8N |
|---|---|---|---|---|---|
| Package | 356-LBGA | 356-LBGA - same | 356-LBGA - same | 356-LBGA - same | 356-LBGA - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel (Altera) | Intel |
| Speed Grade | C8 | C7 (faster) | C7 (faster, extended screening) | B-1 (slower) | C8 (same) |
| Family | APEX 20K | APEX 20K | APEX 20K | APEX 20K | APEX 20K |
| Logic Elements | 4,160 | 4,160 (same die) | 4,160 (same die) | 4,160 (same die) | 4,160 (same die) |
| Embedded Memory (EAB) | 24 Kbits (12 EABs) | 24 Kbits | 24 Kbits | 24 Kbits | 24 Kbits |
| PLLs | 4 | 4 | 4 | 4 | 4 |
| Max User I/O | 252 | 252 | 252 | 252 | 252 |
主な差別化要因
- C8 speed grade is widely available on the legacy market （vs EP20K100CB356C7)
- Same-die compatibility across all C-grade speed bins （vs EP20K100BC356-1)
- Pb-free C8N variant supports lead-free assembly （vs EP20K100CB356C8N)
設計ノート
The APEX 20K core is supplied from VCCINT (2.5 V) and the internal linear regulator generates the 1.8 V core rail. Decouple VCCINT with 100 µF bulk plus 0.1 µF and 0.01 µF ceramics per the family reference design. The PLL analog supply (VCC_PLL) requires a quiet dedicated 1.8 V rail with its own pi-filter (10 µF + ferrite + 10 µF); sharing VCC_PLL with digital VCCINT will inject jitter into the PLLs. Use separate ground returns for VCC_PLL and VCCINT and join them only at the package thermal pad.
The 356-ball LBGA uses 1.27 mm pitch; route signals on inner layers with microvia or via-in-pad if your fab supports it. Match all high-speed clock and DQS trace lengths to within ±50 mil to preserve timing margins. Keep the JTAG chain (TCK, TMS, TDI, TDO) on a dedicated layer with a 4.7 kΩ pull-up on TCK to VCCIO of the JTAG bank. Place the configuration EPROM (EPC2 or EPCS) within 50 mm of the FPGA to avoid configuration-clock reflections.
Do not apply VCCIO before VCCINT: the APEX 20K datasheet mandates VCCINT (2.5 V) reach 90% before VCCIO ramps, otherwise the I/O drivers can back-power the core through ESD clamps. The MSEL pins must be tied to a fixed configuration mode; leaving them floating causes the device to enter an undefined state. When migrating from C7 to C8 (or vice versa), the bitstream is NOT timing-equivalent: re-run TimeQuest in Quartus II to confirm hold-time closure, especially on DQS-based interfaces.
The 356-ball LBGA requires a 6-layer stack-up at minimum to fan out the inner balls without dog-bone congestion. Use a 1-oz copper outer layer and 0.5-oz inner layers with 0.2 mm via pad and 0.1 mm drill. The thermal pad (center balls) must be soldered to a 25 mm × 25 mm copper pour on the top layer and stitched to inner ground planes with a 4-via array per thermal ball. Without proper thermal pad attachment, the junction-to-ambient thermal resistance will rise above 30 °C/W and force derating in industrial-temperature applications.
コンプライアンス情報
APEX 20K family pre-dates widespread RoHS conversion; the C8N variant is the lead-free option. RoHS and REACH compliance status was not present in the verified web data and is marked unknown. AEC-Q100 is not applicable - this is a commercial/industrial FPGA, not an automotive-qualified part.
