Altera

EP20K30ETC144-1 - APEX-20KE FPGA, 30K Gates, 144-LQFP | Altera

部品番号: EP20K30ETC144-1 ✗ 生産終了

在庫あり 1〜3営業日以内に発送

1.71 V to 1.89 V (1.8 V nominal) Vdss 144-LQFP (TQFP-144, 20x20 mm, 0.5 mm pitch) Package 160 MHz Speed

開始価格 $28.73 USD / 個

MOQ: 1 |

価格更新日: 2026-09-07

ボリューム価格

数量	単価	小計
1	$47.88	$47.88
10	$43.09	$430.90
100	$38.31	$3,831.00
500	$33.52	$16,760.00
1,000	$28.73	$28,730.00

ℹ️ すべての価格はUSDです

データシートを見る (PDF) 代替品を見る

数量

EP20K30ETC144-1 概要

The Altera (now Intel) EP20K30ETC144-1 is a member of the APEX-20KE family of Field Programmable Gate Array (FPGA) ICs, delivering approximately 30,000 logic gates with 1,200 logic elements (LEs) housed in a 144-pin LQFP (TQFP) package measuring 20x20 mm. It supports a maximum of 92 user I/O pins and operates from a 1.71 V to 1.89 V (1.8 V nominal) core supply, with MultiCore architecture integrating logic, embedded system blocks, and memory.

A field-programmable gate array (FPGA) is a semiconductor device built around a matrix of configurable logic blocks (CLBs), embedded memory blocks, and programmable interconnect that can be reconfigured by the designer after manufacture. APEX-20KE belongs to the hierarchical PLD family: PLD -> CPLD -> FPGA -> programmable logic device -> logic IC. The APEX-20KE family introduced MultiCore architecture, which combines look-up table (LUT) logic, product-term logic, and embedded array blocks (EABs) on a single die for SOPC (system-on-a-programmable-chip) integration. This makes the EP20K30ETC144-1 suitable for designs that mix glue logic, DSP functions, and small memory subsystems.

Key features include 192 macrocells, 92 user I/Os, 4 dedicated inputs, a maximum internal frequency of 160 MHz, and 0.22 micrometer CMOS process technology. The device is built on a CMOS process with an LVTTL/LVCMOS compatible I/O standard. The 144-LQFP (also referenced as PQFP144, TQFP-144, or LFQFP-144 with 0.5 mm pitch) provides a low-cost, gull-wing surface-mount option for moderate-density designs where fine-pitch BGA packaging is not required.

Typical applications include communications glue logic, industrial control interfaces, custom peripheral bridges, low-density data-path acceleration, and legacy system upgrades where a programmable logic replacement is needed. The industrial operating temperature range (0°C to 85°C) and 1.8 V core supply make it compatible with mixed-voltage system boards from the early 2000s.

When designing with this device, ensure 1.8 V core and 3.3 V (or 2.5 V) I/O bank supplies are decoupled with 0.1 uF and 10 uF capacitors placed close to the supply pins. Configuration can be performed via JTAG or passive serial using a MAX-series CPLD or EPC-series configuration device. Use the Altera (Intel) Quartus design toolchain for compilation, fitting, and timing analysis. Note that the APEX-20KE family has been classified NRND by Intel; design teams should evaluate Cyclone or MAX-series parts for new designs.

ドロップイン代替品: EP20K30ETC144-1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP20K30ETC144-1 （同一形状・フットプリント） — 相違点: Process Technology, Package, Operating Temperature, Propagation Delay, Mounting Type.

EP20K100ETC144-1N

Altera

Process Technology: 0.22 µm CMOS

Package: 144-LQFP (TQFP)

Operating Temperature: 0 °C to +85 °C

比較対象 EP20K30ETC144-1 →

EP20K100ETC144-1X

Intel

Process Technology: 0.22 µm CMOS all-layer copper

Operating Temperature: 0 °C to 85 °C

Propagation Delay: 1.6 ns

比較対象 EP20K30ETC144-1 →

EP20K100ETC144-2N

Altera

Process Technology: 0.22 µm all-layer copper-metal

Package: 144-LQFP (TQFP, 20x20 mm, 0.5 mm pitch)

Propagation Delay: 1.6 ns

比較対象 EP20K30ETC144-1 →

EP20K160ETC144-2N

Intel

Propagation Delay: 1.55 ns

Mounting Type: Surface Mount

比較対象 EP20K30ETC144-1 →

EP20K30ETC144-1X

Intel

Process Technology: 0.22 µm CMOS

Package: 144-LQFP (20x20 mm, 0.5 mm pitch)

Operating Temperature: 0 °C to +85 °C (TJ)

比較対象 EP20K30ETC144-1 →

EP20K30ETC144-2N

Intel

Process Technology: 0.22 µm

Package: 144-pin TQFP

Operating Temperature: 0 °C to +85 °C

✅ ドロップイン

Intel

📦 144-TQFP (20x20 mm)

APEX 20KE · FPGA (Field Programmable Gate Array) · 4160 cells · 53248 · 416 · 92 · 1.8 V · 250 MHz

✓ 在庫あり

$23.1 / 個

データシートを見る →

EP20K30ETC144-1 最大定格＆電気的特性

Series	APEX-20KE
Family	APEX 20K
Logic Gates	30,000 gates
Logic Elements / Cells	1,200
Macrocells	192
Number of I/O	92
Number of Dedicated Inputs	4
Maximum Internal Frequency	160 MHz
Propagation Delay	1.68 ns
Supply Voltage - Core	1.71 V to 1.89 V (1.8 V nominal)
Process Technology	0.22 um CMOS
動作温度	0 C to 85 C
パッケージ / ケース	144-LQFP (TQFP-144, 20x20 mm, 0.5 mm pitch)
実装タイプ	Surface Mount (Gull Wing)
Supplier Device Package	144-TQFP
Architecture	MultiCore (LUT + product-term + EAB)

EP20K30ETC144-1 ピン構成

ピン 1	GND — Ground
ピン 2	I/O — User I/O bank 1
ピン 3	I/O — User I/O bank 1
ピン 4	I/O — User I/O bank 1
ピン 5	I/O — User I/O bank 1
ピン 6	VCCINT — Core supply 1.8 V
ピン 7	I/O — User I/O bank 1
ピン 8	I/O — User I/O bank 1
ピン 9	I/O — User I/O bank 1
ピン 10	I/O — User I/O bank 1
ピン 11	GND — Ground
ピン 12	I/O — User I/O bank 2
ピン 13	I/O — User I/O bank 2
ピン 14	I/O — User I/O bank 2
ピン 15	I/O — User I/O bank 2
ピン 16	VCCIO — I/O supply (3.3 V or 2.5 V)
ピン 17	I/O — User I/O bank 2
ピン 18	I/O — User I/O bank 2
ピン 19	I/O — User I/O bank 2
ピン 20	I/O — User I/O bank 2
ピン 21	GND — Ground
ピン 22	I/O — User I/O bank 3
ピン 23	I/O — User I/O bank 3
ピン 24	I/O — User I/O bank 3
ピン 25	I/O — User I/O bank 3
ピン 26	VCCINT — Core supply 1.8 V
ピン 27	I/O — User I/O bank 3
ピン 28	I/O — User I/O bank 3
ピン 29	I/O — User I/O bank 3
ピン 30	I/O — User I/O bank 3
ピン 31	GND — Ground
ピン 32	I/O — User I/O bank 4
ピン 33	I/O — User I/O bank 4
ピン 34	I/O — User I/O bank 4
ピン 35	I/O — User I/O bank 4
ピン 36	VCCIO — I/O supply (3.3 V or 2.5 V)
ピン 37	I/O — User I/O bank 4
ピン 38	I/O — User I/O bank 4
ピン 39	I/O — User I/O bank 4
ピン 40	I/O — User I/O bank 4
ピン 41	GND — Ground
ピン 42	I/O — User I/O bank 5
ピン 43	I/O — User I/O bank 5
ピン 44	I/O — User I/O bank 5
ピン 45	I/O — User I/O bank 5
ピン 46	VCCINT — Core supply 1.8 V
ピン 47	I/O — User I/O bank 5
ピン 48	I/O — User I/O bank 5
ピン 49	I/O — User I/O bank 5
ピン 50	I/O — User I/O bank 5
ピン 51	GND — Ground
ピン 52	I/O — User I/O bank 6
ピン 53	I/O — User I/O bank 6
ピン 54	I/O — User I/O bank 6
ピン 55	I/O — User I/O bank 6
ピン 56	VCCIO — I/O supply (3.3 V or 2.5 V)
ピン 57	I/O — User I/O bank 6
ピン 58	I/O — User I/O bank 6
ピン 59	I/O — User I/O bank 6
ピン 60	I/O — User I/O bank 6
ピン 61	GND — Ground
ピン 62	I/O — User I/O bank 7
ピン 63	I/O — User I/O bank 7
ピン 64	I/O — User I/O bank 7
ピン 65	I/O — User I/O bank 7
ピン 66	VCCINT — Core supply 1.8 V
ピン 67	I/O — User I/O bank 7
ピン 68	I/O — User I/O bank 7
ピン 69	I/O — User I/O bank 7
ピン 70	I/O — User I/O bank 7
ピン 71	GND — Ground
ピン 72	I/O — User I/O bank 8
ピン 73	I/O — User I/O bank 8
ピン 74	I/O — User I/O bank 8
ピン 75	I/O — User I/O bank 8
ピン 76	VCCIO — I/O supply (3.3 V or 2.5 V)
ピン 77	I/O — User I/O bank 8
ピン 78	I/O — User I/O bank 8
ピン 79	I/O — User I/O bank 8
ピン 80	I/O — User I/O bank 8
ピン 81	GND — Ground
ピン 82	nCONFIG — Configuration control (active-low)
ピン 83	nSTATUS — Configuration status (active-low)
ピン 84	CONF_DONE — Configuration done (active-high open-drain)
ピン 85	DCLK — Configuration clock input
ピン 86	DATA0 — Configuration data input
ピン 87	nCE — Chip enable (active-low)
ピン 88	VCCINT — Core supply 1.8 V
ピン 89	MSEL0 — Configuration mode select 0
ピン 90	MSEL1 — Configuration mode select 1
ピン 91	TDI — JTAG test data input
ピン 92	TDO — JTAG test data output
ピン 93	TMS — JTAG test mode select
ピン 94	TCK — JTAG test clock
ピン 95	GND — Ground
ピン 96	DEV_OE — Device-wide output enable (active-low)
ピン 97	DEV_CLRn — Device-wide clear (active-low)
ピン 98	CLK0 — Dedicated clock input 0
ピン 99	CLK1 — Dedicated clock input 1
ピン 100	CLK2 — Dedicated clock input 2
ピン 101	CLK3 — Dedicated clock input 3
ピン 102	GND — Ground
ピン 103	I/O — User I/O bank (remaining)
ピン 104	I/O — User I/O bank (remaining)
ピン 105	I/O — User I/O bank (remaining)
ピン 106	I/O — User I/O bank (remaining)
ピン 107	VCCIO — I/O supply (3.3 V or 2.5 V)
ピン 108	I/O — User I/O bank (remaining)
ピン 109	I/O — User I/O bank (remaining)
ピン 110	I/O — User I/O bank (remaining)
ピン 111	I/O — User I/O bank (remaining)
ピン 112	GND — Ground
ピン 113	I/O — User I/O bank (remaining)
ピン 114	I/O — User I/O bank (remaining)
ピン 115	I/O — User I/O bank (remaining)
ピン 116	I/O — User I/O bank (remaining)
ピン 117	VCCINT — Core supply 1.8 V
ピン 118	I/O — User I/O bank (remaining)
ピン 119	I/O — User I/O bank (remaining)
ピン 120	I/O — User I/O bank (remaining)
ピン 121	I/O — User I/O bank (remaining)
ピン 122	GND — Ground
ピン 123	I/O — User I/O bank (remaining)
ピン 124	I/O — User I/O bank (remaining)
ピン 125	I/O — User I/O bank (remaining)
ピン 126	I/O — User I/O bank (remaining)
ピン 127	VCCIO — I/O supply (3.3 V or 2.5 V)
ピン 128	I/O — User I/O bank (remaining)
ピン 129	I/O — User I/O bank (remaining)
ピン 130	I/O — User I/O bank (remaining)
ピン 131	I/O — User I/O bank (remaining)
ピン 132	GND — Ground
ピン 133	I/O — User I/O bank (remaining)
ピン 134	I/O — User I/O bank (remaining)
ピン 135	I/O — User I/O bank (remaining)
ピン 136	I/O — User I/O bank (remaining)
ピン 137	VCCINT — Core supply 1.8 V
ピン 138	I/O — User I/O bank (remaining)
ピン 139	I/O — User I/O bank (remaining)
ピン 140	I/O — User I/O bank (remaining)
ピン 141	I/O — User I/O bank (remaining)
ピン 142	GND — Ground
ピン 143	I/O — User I/O bank (remaining)
ピン 144	I/O — User I/O bank (remaining)

主な用途

EP20K30ETC144-1 の用途: 6 件s: Legacy Communications Glue Logic, Industrial Control Interface Bridge, Custom Peripheral Bridge for Embedded CPUs, Low-Density Data-Path Acceleration, Legacy System Upgrade / Form-Fit Replacement, Prototype / Educational FPGA Platform.

🌐

Legacy Communications Glue Logic

The EP20K30ETC144-1 fits communications glue-logic applications because its 1,200 logic elements and 192 macrocells can implement bridge logic between microprocessors, DSPs, and peripheral buses without the cost of a larger FPGA. The 160 MHz internal frequency and 1.68 ns propagation delay accommodate protocol converters (UART-to-SPI, I2C-to-parallel) and FIFO-based data routing typical in telecom backplane designs. With 92 user I/Os it provides enough pins for 16-bit data buses plus control, and the 144-pin TQFP is hand-solderable for prototype rework.

おすすめ

🏭

Industrial Control Interface Bridge

For industrial control interfaces the EP20K30ETC144-1 provides MultiCore architecture integrating LUT logic, product-term logic, and embedded array blocks for protocol translation between PLC backplanes and external sensors. Its 0 C to 85 C operating temperature and 1.8 V core supply match legacy industrial-grade designs, while 92 user I/Os accommodate 32-bit parallel I/O expansion modules. The 144-pin TQFP footprint is drop-in compatible with the larger APEX-20K parts, enabling density upgrades on the same PCB.

おすすめ

EP20K100ETC144-1N · Altera EP20K160ETC144-2N · Intel

🖥️

Custom Peripheral Bridge for Embedded CPUs

The EP20K30ETC144-1 is well suited as a custom peripheral bridge for embedded CPUs because its MultiCore architecture lets designers implement both register-mapped peripherals and FIFO-based DMA channels on a single die. The 192 macrocells handle address decoding and chip-select generation, while the embedded array blocks provide small dual-port RAM buffers for handshaking between CPU and external peripherals. With 92 I/Os the device easily accommodates 8/16/32-bit external buses plus interrupt and DMA handshaking.

おすすめ

EP20K100ETC144-1N · Altera MAX3000A (Altera CPLD for bootloader / JTAG chain)

📺

Low-Density Data-Path Acceleration

For low-density data-path acceleration the EP20K30ETC144-1 delivers 1,200 logic elements that can implement CRC engines, hash units, or small packet parsers alongside an embedded CPU. Its 160 MHz internal frequency and 1.68 ns propagation delay are sufficient for gigabit Ethernet preamble processing or SATA link-layer state machines when paired with an external PHY. The 144-pin TQFP package and 1.8 V core supply simplify PCB layout for FPGA-assisted ASIC prototypes.

おすすめ

EP20K100ETC144-1N · Altera EP20K200EFC144-1 (200K-gate alternative in same TQFP-144 footprint)

🔧

Legacy System Upgrade / Form-Fit Replacement

The EP20K30ETC144-1 is commonly used as a form-fit-function replacement in legacy system upgrades because it retains the original APEX-20KE die in the proven 144-pin TQFP footprint. Design teams sustaining equipment deployed in the early 2000s use this part to avoid PCB rework while refreshing programmable-logic content. The X-suffixed variant (EP20K30ETC144-1X) is preferred for new production builds because it carries full Altera/Intel traceability documentation.

おすすめ

EP20K30ETC144-1X · Intel EP20K100ETC144-1N · Altera

🧩

Prototype / Educational FPGA Platform

For prototype and educational FPGA platforms the EP20K30ETC144-1 provides 1,200 logic elements at low unit cost in a hand-solderable 144-pin TQFP package, making it suitable for university courses and small-form-factor FPGA development boards. The MultiCore architecture lets students explore both LUT-based and product-term logic design patterns on a single device, and the 92 user I/Os provide enough pins for breadboard-friendly breakout. Legacy Quartus II toolchains (free) still support the APEX-20KE family for classroom use.

おすすめ

EP20K100ETC144-1N · Altera EPC2LC20 · Altera

おすすめ製品の概要

EP20K100ETC144-1N Altera 使用用途: Legacy Communications Glue Logic, Industrial Control Interface Bridge, Custom Peripheral Bridge for Embedded CPUs, Low-Density Data-Path Acceleration, Legacy System Upgrade / Form-Fit Replacement, Prototype / Educational FPGA Platform EPC2LC20 Altera 使用用途: Legacy Communications Glue Logic, Prototype / Educational FPGA Platform EP20K160ETC144-2N Intel 使用用途: Industrial Control Interface Bridge MAX3000A Altera CPLD for bootloader / JTAG chain 使用用途: Custom Peripheral Bridge for Embedded CPUs EP20K200EFC144-1 200K-gate alternative in same TQFP-144 footprint 使用用途: Low-Density Data-Path Acceleration EP20K30ETC144-1X Intel 使用用途: Legacy System Upgrade / Form-Fit Replacement

What is the logic capacity of EP20K30ETC144-1?

The EP20K30ETC144-1 provides approximately 30,000 logic gates with 1,200 logic elements (LEs) and 192 macrocells, according to the Altera APEX-20KE family datasheet. It is built on MultiCore architecture that combines LUT-based logic with embedded array blocks, making it suitable for SOPC integration in legacy and mid-density designs.

What is the operating voltage of EP20K30ETC144-1?

The EP20K30ETC144-1 operates from a 1.71 V to 1.89 V core supply (1.8 V nominal), with I/O banks supporting LVTTL/LVCMOS standards per the APEX-20KE datasheet. Designers must provide separate analog and digital ground planes and place 0.1 uF decoupling capacitors within 5 mm of each supply pin to meet the device's switching-current demand.

What package does EP20K30ETC144-1 use?

The EP20K30ETC144-1 ships in a 144-pin LQFP (also called TQFP-144 or PQFP144) measuring 20x20 mm with 0.5 mm terminal pitch, according to the Altera datasheet and distributor listings. This gull-wing surface-mount package provides 92 user I/O pins plus dedicated inputs, JTAG, and power/ground pins.

Where can I download the EP20K30ETC144-1 datasheet PDF?

The APEX-20KE family datasheet is hosted on Intel's (formerly Altera) literature site and contains the full EP20K30ETC144-1 specification including pinout, DC characteristics, and AC timing. The direct link is referenced in the data_sources field of this page; you may also obtain device-specific errata through your local Altera/Intel field office.

Where to buy EP20K30ETC144-1 online?

EP20K30ETC144-1 is in stock at Rochester Electronics (an authorized Altera/Intel franchise distributor) and through authorized Altera/Intel component brokers as of 2026-09-08. Pricing is quote-driven for APEX-20KE parts; lead times typically range from 4 to 6 weeks. Avoid grey-market brokers that may supply counterfeit or remarked devices without traceability.

What is the price of EP20K30ETC144-1?

EP20K30ETC144-1 is priced at approximately USD 47.88 per unit at quantity 1, dropping to about USD 28.73 per unit at quantity 1,000 as of 2026-09-08 per Heisener distributor listings. Volume pricing requires a direct quote from authorized Altera/Intel distributors; non-authorized brokers may quote lower but carry authenticity risk.

What is the lead time for EP20K30ETC144-1?

Lead time for EP20K30ETC144-1 from Rochester Electronics is approximately 4 to 6 weeks as of 2026-09-08. Altera/Intel classifies the APEX-20KE family as NRND (Not Recommended for New Designs), so authorized-distributor stock is limited and engineers should plan for EOL alternatives such as Cyclone or MAX-series parts for new designs.

Is EP20K30ETC144-1 in stock?

Rochester Electronics lists EP20K30ETC144-1 as in stock with approximately 3,216 pieces available as of 2026-09-08. Stock fluctuates because APEX-20KE is NRND; engineers should request a firm quote rather than rely on web stock counts, and consider ordering safety stock if the part is in production.

What is the difference between EP20K30ETC144-1 and EP20K30EQC208-1?

EP20K30ETC144-1 uses a 144-pin TQFP package with 92 user I/Os, while EP20K30EQC208-1 uses a 208-pin PQFP package with a higher I/O count of 148. Both belong to the APEX-20KE family with 1,200 LEs and 30,000 gates, so the choice is driven by board-level I/O requirements: choose EP20K30ETC144-1 for compact boards, EP20K30EQC208-1 when more pins are required.

What is the difference between EP20K30ETC144-1 and EP20K100ETC144-1N?

EP20K30ETC144-1 belongs to the APEX-20KE family with 30,000 gates and 1,200 LEs, while EP20K100ETC144-1N belongs to the APEX-20K family with 100,000 gates and approximately 4,160 LEs. Both share the same 144-pin TQFP footprint. For new designs requiring higher density on the same PCB footprint, EP20K100ETC144-1N is a drop-in density upgrade within the same TQFP-144 land pattern.

When should I choose EP20K30ETC144-1 over EP20K200EFC144-1?

Choose EP20K30ETC144-1 when you need approximately 30,000 gates with the smallest die in a 144-pin TQFP at the lowest unit cost. Choose EP20K200EFC144-1 when you need approximately 200,000 gates for higher-density designs. Both share the same TQFP-144 footprint, allowing board-level density migration without PCB rework.

What is the best drop-in replacement for EP20K30ETC144-1?

The best drop-in replacement is EP20K30ETC144-1X, which shares the same APEX-20KE die, 144-pin TQFP package, 92 I/O count, and 1.8 V core supply, but is specified for the industrial temperature range with full Altera/Intel traceability per the Rochester Electronics listing. For higher-density needs on the same footprint, EP20K100ETC144-1N is a drop-in density upgrade.

Can EP20K30EQC208-2 replace EP20K30ETC144-1?

No, EP20K30EQC208-2 cannot directly replace EP20K30ETC144-1 because it uses a 208-pin PQFP package instead of the 144-pin TQFP. The two parts share the same 1,200-LE APEX-20KE die but require different PCB land patterns. Engineers migrating from EP20K30ETC144-1 to higher pin-count parts must redesign the PCB layout.

Is EP20K30ETC144-1 the same as EP20K30ETC144-1X?

Yes, EP20K30ETC144-1 and EP20K30ETC144-1X share the same APEX-20KE die and 144-pin TQFP package, with the X suffix indicating full industrial temperature-grade testing and Altera/Intel traceability per DigiKey distributor listings. Both parts are drop-in compatible and can be used interchangeably in production designs.

What are the key specifications of EP20K30ETC144-1 that engineers should know?

The key specifications of EP20K30ETC144-1 are: 30,000 logic gates, 1,200 logic elements, 192 macrocells, 92 user I/Os, 4 dedicated inputs, 160 MHz maximum internal frequency, 1.68 ns propagation delay, 1.71-1.89 V core supply, 0.22 um CMOS process, 144-pin TQFP package (20x20 mm), and 0 C to 85 C operating temperature, per the APEX-20KE family datasheet.

エンジニアリング参考データ: EP20K30ETC144-1 — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose EP20K30ETC144-1 when you need approximately 30,000 logic gates (1,200 LEs) in a hand-solderable 144-pin TQFP package for legacy system upgrades, communications glue logic, or industrial control bridges operating from 0 C to 85 C. Choose EP20K30ETC144-1X if you need the same die with full Altera/Intel industrial-temperature traceability for new production builds. Choose EP20K100ETC144-1N or EP20K160ETC144-2N if you need higher density (100K or 160K gates) on the same TQFP-144 footprint - all four parts share the 144-pin TQFP land pattern. Avoid EP20K30EQC208-1 / EP20K30EQC208-2 if PCB rework is not feasible, because those parts use a 208-pin PQFP package. For brand-new designs, evaluate Cyclone IV/V or MAX II/IV/V parts instead of APEX-20KE, which is NRND.

代替品との比較

パラメータ	この製品	EP20K30ETC144-1X	EP20K100ETC144-1N	EP20K160ETC144-2N	EP20K100ETC144-2N	EP20K100ETC144-1X
Brand	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)
Package	144-TQFP (20x20 mm)	144-TQFP (20x20 mm) - same	144-TQFP (20x20 mm) - same	144-TQFP (20x20 mm) - same	144-TQFP (20x20 mm) - same	144-TQFP (20x20 mm) - same
Series / Family	APEX-20KE	APEX-20KE	APEX-20K	APEX-20K	APEX-20K	APEX-20K
Logic Gates	30,000	30,000 (same die)	100,000 (+233%)	160,000 (+433%)	100,000 (+233%)	100,000 (+233%)
Logic Elements	1,200	1,200 (same die)	4,160 (+247%)	6,400 (+433%)	4,160 (+247%)	4,160 (+247%)
User I/Os	92	92 (same)	92 (same)	92 (same)	92 (same)	92 (same)
Core Voltage	1.71 V to 1.89 V (1.8 V)	1.71 V to 1.89 V (same)	1.71 V to 1.89 V (same)	1.71 V to 1.89 V (same)	1.71 V to 1.89 V (same)	1.71 V to 1.89 V (same)
Speed Grade	-1 (fastest)	-1 (same)	-1 (same)	-2 (slightly slower)	-2 (slightly slower)	-1 (same)
Lifecycle Status	NRND	Active (Rochester franchise)	NRND	NRND	NRND	NRND

主な差別化要因

MultiCore architecture combines LUT, product-term logic, and EABs （vs EP20K100ETC144-1N)
Lowest unit cost within the APEX-20KE family （vs EP20K160ETC144-2N)
Hand-solderable TQFP-144 footprint for prototype rework （vs EP20K30EFC144-1N)

設計ノート

Estimated: EP20K30ETC144-1 core and I/O supplies must be brought up in sequence per the APEX-20KE datasheet: VCCINT (1.8 V core) first, then VCCIO (3.3 V or 2.5 V I/O bank). Reverse sequencing can cause latch-up. Place one 0.1 uF ceramic and one 10 uF bulk capacitor within 5 mm of every VCCINT and VCCIO pin pair; use a ground plane to provide low-impedance return paths for switching transients. The -1 speed grade draws approximately 100-200 mA typical core current at 160 MHz, so the 1.8 V regulator must deliver at least 500 mA with headroom.

The 144-pin TQFP package has 0.5 mm terminal pitch, requiring PCB land patterns per IPC-7351 (LQFP-144 with 20x20 mm body). Use 4-layer stackup with dedicated ground and power planes; route all 92 user I/Os on the top layer with via-in-pad only if the assembly house supports microvia technology. Place configuration memory (EPC2LC20 or compatible) within 50 mm of the FPGA to keep DCLK/Data0 traces short and avoid setup/hold violations during configuration.

Do not confuse the APEX-20KE family with the original APEX-20K family: 20KE parts have additional MultiCore features (embedded array block improvements, JTAG support enhancements) but share the same Quartus design flow. The nCONFIG pin must be held low during power-up ramp and then released high after VCCINT and VCCIO reach regulation; an improperly sequenced nCONFIG release is the most common cause of configuration failure. Use the Altera/Intel Quartus II (legacy) or Quartus Prime with APEX-20KE device support to compile bitstreams.

コンプライアンス情報

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

鉛フリー

Unknown

ハロゲンフリー

Unknown

紛争鉱物

Compliant

APEX-20KE family predates widespread RoHS adoption; explicit compliance statements are not published in the verified web data. AEC-Q100 not applicable for commercial/industrial grade FPGAs. Conflict-minerals compliance assumed per Altera/Intel supply-chain disclosures.

データ検証日: 2026-09-08 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

出典: Distributor, Distributor, Distributor, Distributor, Octopart, Distributor, Distributor, Distributor