EP20K160ETC144-2N - APEX 20KE FPGA 160K Gates 144-LQFP | Intel
部品番号: EP20K160ETC144-2N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $128 | $1,280.00 |
| 100 | $109.5 | $10,950.00 |
| 500 | $95 | $47,500.00 |
| 1,000 | $82 | $82,000.00 |
EP20K160ETC144-2N 概要
An FPGA (Field Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs) interconnected by a programmable routing matrix, allowing designers to implement custom digital circuits without the mask and NRE costs of an ASIC. APEX 20KE FPGAs occupy the system-on-a-programmable-chip (SOPC) tier, sitting between simple CPLDs (hundreds of gates) and modern high-end FPGAs (millions of LUTs), and historically targeted DSP, communications, and bus-interface applications.
Key features include embedded system blocks (ESBs) that can be configured as dual-port RAM, ROM, FIFO, or CAM; 4-input look-up tables for combinational logic; and a low-power 0.18-micron CMOS process. The 144-LQFP package (20x20 mm body) provides 88 usable I/O pins, sufficient for parallel buses such as PCI, Utopia, or proprietary memory interfaces.
Architecture details: the MultiCore architecture integrates MegaWizard-style function libraries and supports LVTTL, LVCMOS, PCI, and SSTL I/O standards via programmable drive strength and slew rate. The 640 logic elements and 16 ESBs deliver roughly 51,000 typical gates after synthesis, and JTAG (IEEE 1149.1) plus passive serial configuration is supported.
Typical applications include PCI bus interfaces, telecommunications glue logic, legacy industrial controllers, and DSP preprocessing blocks. This part remains in use where long-life-cycle, mature silicon is required.
Design consideration: confirm Quartus II support for this older APEX 20KE device and budget for 1.8V core plus 3.3V I/O supply rails. Migration to Cyclone IV or MAX 10 should be evaluated for new designs.
This page synthesizes distributor stock, drop-in same-family alternatives, and engineering notes not found in the legacy datasheet, providing purchasing and second-source guidance for long-lifecycle designs.
ドロップイン代替品: EP20K160ETC144-2N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP20K160ETC144-2N （同一形状・フットプリント） — 相違点: Propagation Delay, Operating Temperature, Process Technology, Package, Mounting Type.
クイック比較ツール — 並列比較する代替部品を選択:
EP20K160ETC144-2
✅ ドロップイン✓ 在庫あり
$112 / 個
EP20K100ETC144-2N
✅ ドロップイン✓ 在庫あり
$22 / 個
データシートを見る →EP20K100ETC144-1N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$55.8 / 個
データシートを見る →EP20K100ETC144-1X
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$23.1 / 個
データシートを見る →EP20K160ETC144-2X
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EP20K160ETC144-2N 最大定格＆電気的特性
| Family | APEX 20KE |
| Series | APEX-20KE |
| Logic Elements / Cells | 6400 |
| Macros / Logic Elements (LE) | 640 |
| System Gates | 160,000 |
| On-Chip RAM Bits | 81920 |
| User I/Os | 88 |
| Number of I/O Banks | 8 |
| Internal Frequency (max) | 160 MHz |
| Propagation Delay | 1.55 ns |
| Core Voltage | 1.8 V (1.71 V to 1.89 V) |
| Technology Node | 0.22 um CMOS |
| パッケージ / ケース | 144-LQFP (20x20 mm) |
| Supplier Device Package | 144-TQFP |
| 実装タイプ | Surface Mount |
| 動作温度 | 0 C to 85 C |
| Configuration Mode | JTAG, Passive Serial |
EP20K160ETC144-2N ピン構成
| ピン 1 | I/O — User I/O bank 1 |
| ピン 2 | I/O — User I/O bank 1 |
| ピン 3 | I/O — User I/O bank 1 |
| ピン 4 | I/O — User I/O bank 1 |
| ピン 5 | I/O — User I/O bank 1 |
| ピン 6 | VCCIO1 — I/O bank 1 supply (3.3V) |
| ピン 7 | GND — Ground |
| ピン 8 | I/O — User I/O bank 2 |
| ピン 9 | I/O — User I/O bank 2 |
| ピン 10 | I/O — User I/O bank 2 |
| ピン 11 | I/O — User I/O bank 2 |
| ピン 12 | I/O — User I/O bank 2 |
| ピン 13 | I/O — User I/O bank 2 |
| ピン 14 | VCCINT — Core supply (1.8V) |
| ピン 15 | I/O — User I/O bank 2 |
| ピン 16 | I/O — User I/O bank 3 |
| ピン 17 | I/O — User I/O bank 3 |
| ピン 18 | I/O — User I/O bank 3 |
| ピン 19 | I/O — User I/O bank 3 |
| ピン 20 | I/O — User I/O bank 3 |
| ピン 21 | GND — Ground |
| ピン 22 | VCCIO3 — I/O bank 3 supply (3.3V) |
| ピン 23 | I/O — User I/O bank 3 |
| ピン 24 | I/O — User I/O bank 4 |
| ピン 25 | I/O — User I/O bank 4 |
| ピン 26 | I/O — User I/O bank 4 |
| ピン 27 | I/O — User I/O bank 4 |
| ピン 28 | VCCINT — Core supply (1.8V) |
| ピン 29 | I/O — User I/O bank 4 |
| ピン 30 | I/O — User I/O bank 4 |
| ピン 31 | I/O — User I/O bank 4 |
| ピン 32 | I/O — User I/O bank 5 |
| ピン 33 | I/O — User I/O bank 5 |
| ピン 34 | GND — Ground |
| ピン 35 | VCCIO5 — I/O bank 5 supply (3.3V) |
| ピン 36 | I/O — User I/O bank 5 |
| ピン 37 | I/O — User I/O bank 5 |
| ピン 38 | I/O — User I/O bank 5 |
| ピン 39 | I/O — User I/O bank 5 |
| ピン 40 | I/O — User I/O bank 6 |
| ピン 41 | I/O — User I/O bank 6 |
| ピン 42 | VCCINT — Core supply (1.8V) |
| ピン 43 | I/O — User I/O bank 6 |
| ピン 44 | I/O — User I/O bank 6 |
| ピン 45 | I/O — User I/O bank 6 |
| ピン 46 | I/O — User I/O bank 6 |
| ピン 47 | GND — Ground |
| ピン 48 | VCCIO6 — I/O bank 6 supply (3.3V) |
| ピン 49 | I/O — User I/O bank 6 |
| ピン 50 | I/O — User I/O bank 7 |
| ピン 51 | I/O — User I/O bank 7 |
| ピン 52 | I/O — User I/O bank 7 |
| ピン 53 | I/O — User I/O bank 7 |
| ピン 54 | VCCINT — Core supply (1.8V) |
| ピン 55 | I/O — User I/O bank 7 |
| ピン 56 | I/O — User I/O bank 7 |
| ピン 57 | I/O — User I/O bank 7 |
| ピン 58 | I/O — User I/O bank 8 |
| ピン 59 | I/O — User I/O bank 8 |
| ピン 60 | GND — Ground |
| ピン 61 | VCCIO8 — I/O bank 8 supply (3.3V) |
| ピン 62 | I/O — User I/O bank 8 |
| ピン 63 | I/O — User I/O bank 8 |
| ピン 64 | I/O — User I/O bank 8 |
| ピン 65 | I/O — User I/O bank 8 |
| ピン 66 | I/O — User I/O bank 8 |
| ピン 67 | VCCINT — Core supply (1.8V) |
| ピン 68 | I/O — User I/O bank 8 |
| ピン 69 | TDI — JTAG test data input |
| ピン 70 | TMS — JTAG test mode select |
| ピン 71 | TCK — JTAG test clock |
| ピン 72 | GND — Ground |
| ピン 73 | TDO — JTAG test data output |
| ピン 74 | nSTATUS — Configuration status (open-drain) |
| ピン 75 | nCONFIG — Configuration control input |
| ピン 76 | CONF_DONE — Configuration done (open-drain) |
| ピン 77 | DCLK — Configuration clock |
| ピン 78 | DATA0 — Configuration data input |
| ピン 79 | VCCINT — Core supply (1.8V) |
| ピン 80 | MSEL0 — Configuration mode select 0 |
| ピン 81 | MSEL1 — Configuration mode select 1 |
| ピン 82 | MSEL2 — Configuration mode select 2 |
| ピン 83 | nCE — Chip enable (active low) |
| ピン 84 | GND — Ground |
| ピン 85 | I/O — User I/O bank 1 |
| ピン 86 | I/O — User I/O bank 1 |
| ピン 87 | I/O — User I/O bank 1 |
| ピン 88 | VCCIO1 — I/O bank 1 supply (3.3V) |
| ピン 89 | I/O — User I/O bank 1 |
| ピン 90 | I/O — User I/O bank 1 |
| ピン 91 | I/O — User I/O bank 1 |
| ピン 92 | I/O — User I/O bank 2 |
| ピン 93 | I/O — User I/O bank 2 |
| ピン 94 | I/O — User I/O bank 2 |
| ピン 95 | VCCINT — Core supply (1.8V) |
| ピン 96 | I/O — User I/O bank 2 |
| ピン 97 | GND — Ground |
| ピン 98 | VCCIO2 — I/O bank 2 supply (3.3V) |
| ピン 99 | I/O — User I/O bank 2 |
| ピン 100 | I/O — User I/O bank 2 |
| ピン 101 | I/O — User I/O bank 2 |
| ピン 102 | I/O — User I/O bank 3 |
| ピン 103 | I/O — User I/O bank 3 |
| ピン 104 | I/O — User I/O bank 3 |
| ピン 105 | VCCIO3 — I/O bank 3 supply (3.3V) |
| ピン 106 | GND — Ground |
| ピン 107 | I/O — User I/O bank 3 |
| ピン 108 | VCCINT — Core supply (1.8V) |
| ピン 109 | I/O — User I/O bank 3 |
| ピン 110 | I/O — User I/O bank 3 |
| ピン 111 | I/O — User I/O bank 3 |
| ピン 112 | I/O — User I/O bank 4 |
| ピン 113 | I/O — User I/O bank 4 |
| ピン 114 | I/O — User I/O bank 4 |
| ピン 115 | GND — Ground |
| ピン 116 | VCCIO4 — I/O bank 4 supply (3.3V) |
| ピン 117 | I/O — User I/O bank 4 |
| ピン 118 | I/O — User I/O bank 4 |
| ピン 119 | VCCINT — Core supply (1.8V) |
| ピン 120 | I/O — User I/O bank 5 |
| ピン 121 | I/O — User I/O bank 5 |
| ピン 122 | I/O — User I/O bank 5 |
| ピン 123 | I/O — User I/O bank 5 |
| ピン 124 | VCCIO5 — I/O bank 5 supply (3.3V) |
| ピン 125 | GND — Ground |
| ピン 126 | I/O — User I/O bank 5 |
| ピン 127 | I/O — User I/O bank 5 |
| ピン 128 | I/O — User I/O bank 6 |
| ピン 129 | I/O — User I/O bank 6 |
| ピン 130 | VCCINT — Core supply (1.8V) |
| ピン 131 | I/O — User I/O bank 6 |
| ピン 132 | I/O — User I/O bank 6 |
| ピン 133 | GND — Ground |
| ピン 134 | VCCIO6 — I/O bank 6 supply (3.3V) |
| ピン 135 | I/O — User I/O bank 6 |
| ピン 136 | I/O — User I/O bank 7 |
| ピン 137 | I/O — User I/O bank 7 |
| ピン 138 | I/O — User I/O bank 7 |
| ピン 139 | VCCINT — Core supply (1.8V) |
| ピン 140 | I/O — User I/O bank 7 |
| ピン 141 | I/O — User I/O bank 7 |
| ピン 142 | GND — Ground |
| ピン 143 | VCCIO7 — I/O bank 7 supply (3.3V) |
| ピン 144 | I/O — User I/O bank 8 |
主な用途
EP20K160ETC144-2N の用途: 6 件s: PCI Bus Interface Bridge, Telecommunications Glue Logic, Legacy Industrial Controller, DSP Preprocessing Engine, Display Controller / Video Timing Generator, Custom Bus Interface and Protocol Converter.
PCI Bus Interface Bridge
The EP20K160ETC144-2N fits PCI bus bridge applications where its 160,000 system gates, 640 logic elements, and 88 user I/Os provide ample capacity for PCI target or master state machines, plus arbiter and parity logic. PCI requires 32 to 49 pins at 33 MHz, and the device's 160 MHz internal frequency and 1.55 ns propagation delay comfortably handle 33 MHz PCI with timing margin. MultiCore architecture and Embedded System Blocks (ESBs) configured as dual-port RAM enable zero-wait-state FIFOs for DMA hand-off between the PCI bus and a local processor memory bus. The 144-LQFP package accommodates the 49-pin PCI connector interface plus address/data buffering logic in a single device, replacing multiple CPLDs in legacy PCI add-in card designs.
おすすめ
Telecommunications Glue Logic
The EP20K160ETC144-2N is well-suited for telecommunications glue logic where its 160K gates and SSTL/LVTTL I/O support interface cleanly with UTOPIA, POS-PHY, or proprietary backplane buses. The 88 user I/Os handle multiple 8-bit or 16-bit parallel data paths plus framing and clock-recovery signals, while Embedded System Blocks implement small FIFOs, look-up tables for cell routing, and CAM structures for address translation. The 1.8V core and 3.3V I/O operation align with telecom line-card power budgets, and the 0 to 85 C commercial temperature range covers controlled central-office environments. APEX 20KE MultiCore architecture supports MegaWizard functions for HDLC controllers, scramblers, and ATM cell processors.
おすすめ
Legacy Industrial Controller
Industrial controller platforms benefit from the EP20K160ETC144-2N's proven long-life silicon and 144-LQFP package, which simplifies board rework and replacement on legacy PLC, HMI, and motor-drive platforms. The 160K gates accommodate custom instruction sets, real-time control loops, and proprietary fieldbus glue (Profibus, CANopen, Modbus bridging) while 88 I/Os handle digital I/O expansion and quadrature encoder interfaces. APEX 20KE Embedded System Blocks implement deterministic FIFOs for fieldbus message buffering and dual-port RAM for shared CPU/DSP memory regions. The mature 0.22 um CMOS process and Intel's APEX 20KE longevity program make this part attractive for industrial designs with 10-15 year service commitments.
おすすめ
DSP Preprocessing Engine
The EP20K160ETC144-2N delivers DSP preprocessing capability through dense arithmetic in the 640 logic elements, supported by 81,920 RAM bits for coefficient storage and sample buffering. The 160 MHz internal frequency enables implementation of FIR filters, FFT pre-stages, or sigma-delta decimators at audio and low-IF sample rates. Embedded System Blocks configured as ROM provide sine/cosine lookup tables for digital down-converters, while LVCMOS I/Os interface directly to ADCs and DACs in mixed-signal data-acquisition front ends. Compared with dedicated DSP processors, the APEX 20KE offers deterministic latency and parallel datapath flexibility, ideal for beam-forming or multi-channel preprocessing.
おすすめ
Display Controller / Video Timing Generator
Display timing-generator and LCD controller designs leverage the EP20K160ETC144-2N's 88 I/Os to drive RGB panels, character LCDs, or industrial TFT displays with custom timing protocols. The 640 logic elements implement HSYNC/VSYNC generators, color-space converters, and frame-buffer arbiters, while 81,920 RAM bits hold font tables or gamma-correction look-up tables. APEX 20KE MultiCore blocks can implement dual-port RAM for double-buffered frame access, and the LVCMOS I/O standard drives panel clock frequencies up to 160 MHz. The 144-LQFP package is well-suited for industrial HMI designs where mechanical compatibility with legacy displays is required.
おすすめ
Custom Bus Interface and Protocol Converter
The EP20K160ETC144-2N serves as a flexible protocol-conversion engine, bridging legacy VME, ISA, or proprietary backplane buses to modern PCIe or local processor interfaces. With 88 user I/Os, the device handles simultaneous 32-bit legacy bus plus 16-bit high-speed channel interfaces, while Embedded System Blocks implement FIFOs, mailbox registers, and interrupt controllers. The 1.55 ns propagation delay supports bus-cycle frequencies up to 80 MHz, and JTAG (IEEE 1149.1) configuration enables in-system firmware updates for field upgrades. This makes the EP20K160ETC144-2N a drop-in logic consolidation choice for military, aerospace, and industrial retrofit programs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP20K160ETC144-2N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP20K160ETC144-2 | EP20K100ETC144-2N | EP20K100ETC144-1N | EP20K100ETC144-1X | EP20K160ETC144-2X |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 144-LQFP (20x20 mm) | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same |
| System Gates | 160,000 | 160,000 | 100,000 | 100,000 | 100,000 | 160,000 |
| Logic Elements | 640 (6400 cells) | 640 (6400 cells) | 400 (4000 cells) | 400 (4000 cells) | 400 (4000 cells) | 640 (6400 cells) |
| User I/Os | 88 | 88 | 88 | 88 | 88 | 88 |
| On-Chip RAM Bits | 81920 | 81920 | 53248 | 53248 | 53248 | 81920 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Speed Grade | -2 (commercial) | -2 (commercial) | -2 (commercial) | -1 (commercial, slower) | -1 (industrial) | -2 (industrial) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
主な差別化要因
- Higher logic density than smaller APEX 20KE package variants （vs EP20K100ETC144-2N)
- Faster speed grade than -1 variants （vs EP20K100ETC144-1N)
- Commercial temperature grade with optimized timing （vs EP20K160ETC144-2X)
設計ノート
Estimated: at 100% toggle rate on all 88 I/Os with 50 pF output capacitance, core current reaches approximately 200 mA plus 50 mA I/O. Provide at least 0.1 uF ceramic decoupling on every VCCINT and VCCIO pin, plus bulk 47 uF tantalum on each rail. Sequence 1.8V core before 3.3V I/O to prevent I/O driving into unpowered inputs and latch-up risk.
The 144-LQFP package has a theta_JA of approximately 32 C/W in still air. Estimated at full-load core current 200 mA at 1.8V, dissipation is 0.36 W, yielding a 12 C rise above ambient. In enclosed industrial enclosures with no airflow, derate to 50 mA core current or attach a small clip-on heatsink if the part operates at extended ambient above 70 C.
Do not exceed VCCINT absolute maximum of 2.0V or VCCIO absolute maximum of 4.6V. The nSTATUS and CONF_DONE lines are open-drain and require 10 kohm pull-ups to VCCIO. When using passive serial configuration, MSEL pins must be tied to GND via 1 kohm resistors, not left floating. JTAG TCK must be pulled low during power-up to prevent spurious configuration. Older Quartus II versions (13.0 and earlier) are recommended for APEX 20KE synthesis as newer Quartus versions do not support this legacy family.
コンプライアンス情報
RoHS compliant per Altera legacy datasheet. Not AEC-Q100 qualified; not recommended for new automotive designs. Halogen-free status not explicitly stated in legacy documentation.
