EP2AGX190FF35I5G - Arria II GX FPGA, 181K LE, 1152-FBGA | Intel
部品番号: EP2AGX190FF35I5G ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1750 | $17,500.00 |
| 100 | $1620 | $162,000.00 |
| 500 | $1480 | $740,000.00 |
| 1,000 | $1350 | $1,350,000.00 |
EP2AGX190FF35I5G 概要
What is an FPGA? An FPGA (Field Programmable Gate Array) is a semiconductor device whose digital logic, interconnect, and I/O behaviour can be reconfigured after manufacturing. FPGAs sit in the programmable logic category between fixed-function ASICs and software-driven processors, providing hardware-level parallelism for DSP, packet processing, and high-speed serial I/O. Within Intel's portfolio, the Arria II GX family targets mid-range applications that require transceivers and moderate logic density at lower power than Stratix but higher capability than Cyclone.
The EP2AGX190FF35I5G integrates up to 12 embedded transceivers supporting multi-gigabit serial protocols, dedicated on-chip memory blocks, and hard PCIe, Ethernet MAC, and DDR2/DDR3 memory controller IP blocks. The 8-bit Adaptive Logic Module (ALM) architecture is backward-compatible with 4-input LUT designs, simplifying migration from older Altera families. The flip-chip BGA package enables the high I/O count and signal integrity required for parallel memory buses and multiple SERDES lanes.
Typical applications include high-speed serial interface bridging, telecom baseband processing, video broadcast equipment, military/aerospace signal processing, and ASIC prototyping. The combination of transceiver-rich architecture and substantial logic resources also suits medical imaging and industrial vision systems where deterministic latency matters.
When designing with this device, allocate PCB layer stack-up for the FC-FBGA fan-out, observe the in-package decoupling capacitor guidelines in the Arria II GX handbook, and validate transceiver channel performance against the IBIS-AMI models. Use the Quartus II design suite (version 13.0 or later) for synthesis, place-and-route, and timing closure.
This page synthesizes distributor pricing, drop-in alternative MPNs from the same Arria II GX family, and design considerations not found in the bare datasheet, providing actionable engineering context for sourcing and design decisions.
ドロップイン代替品: EP2AGX190FF35I5G — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP2AGX190FF35I5G （同一形状・フットプリント） — 相違点: Package, Speed Grade, Operating Temperature, Mounting Type, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
EP2AGX190FF35I3G
✅ ドロップイン✓ 在庫あり
$1840 / 個
データシートを見る →EP2AGX190FF35I5
✅ ドロップイン✓ 在庫あり
$1700 / 個
データシートを見る →EP2AGX190FF35I3N
✅ ドロップイン✓ 在庫あり
$1190 / 個
データシートを見る →EP2AGX190FF35C6G
✅ ドロップイン✓ 在庫あり
$188 / 個
データシートを見る →EP2AGX190FF35C5G
✅ ドロップイン✓ 在庫あり
$1245 / 個
データシートを見る →EP2AGX190FF35C4G
✅ ドロップイン✓ 在庫あり
$2350 / 個
データシートを見る →EP2AGX190FF35I5G 最大定格＆電気的特性
| Family | Arria II GX |
| Logic Elements | 181,165 |
| Embedded Memory Bits | 10,177,536 |
| Total RAM Bits | 10,177,536 |
| User I/O Count | 612 |
| Number of Transceivers | 12 |
| Process Technology | 40 nm |
| Core Voltage | 0.9 V |
| Package Type | 1152-BBGA, FC-FBGA |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +100C (Industrial) |
| メモリタイプ | Embedded SRAM |
| ALM Architecture | 8-bit Adaptive Logic Module |
EP2AGX190FF35I5G 1152-bbga, fc-fbga ピン配置ガイド
EP2AGX190FF35I5G (1152-bbga, fc-fbga パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP2AGX190FF35I5G.
詳細は データシート をご参照ください。
主な用途
EP2AGX190FF35I5G の用途: 6 件s: Telecom Baseband Processing, High-Speed Serial Interface Bridging, Video Broadcast Equipment, Military and Aerospace Signal Processing, ASIC Prototyping and Emulation, Medical Imaging Systems.
Telecom Baseband Processing
The EP2AGX190FF35I5G fits telecom baseband processing because of its 181,165 logic elements, 12 multi-gigabit transceivers, and dedicated hard IP for CPRI, OBSAI, and Serial RapidIO. Place the device between baseband ASICs and the RF front-end, using SERDES lanes to backhaul digitized samples at line rates up to 3.75 Gbps per channel. Industrial temperature rating ensures reliable operation in outdoor base stations and remote radio heads where ambient swings are common.
おすすめ
High-Speed Serial Interface Bridging
The 12 multi-gigabit transceivers make the EP2AGX190FF35I5G well suited as a protocol bridge between PCIe Gen2, XAUI, Serial RapidIO, and custom serial links. With 612 user I/O plus 12 SERDES lanes, a single device can replace multiple smaller FPGAs in fan-out cards. Industrial temperature rating also lets the same design operate in defense and avionics protocol-conversion racks without redesign.
おすすめ
Video Broadcast Equipment
The EP2AGX190FF35I5G drives broadcast video systems such as SDI routers, multiviewers, and format converters because of its 9.7 Mbit on-chip memory, 181,165 logic elements, and plentiful LVDS-capable I/O. Embed clock domain crossing and frame buffering in the M9K blocks to minimize external SDRAM pressure. Industrial temperature rating supports centralized head-end installations where rack cooling may be limited.
おすすめ
Military and Aerospace Signal Processing
The EP2AGX190FF35I5G suits defense applications such as radar digitizers, electronic warfare subsystems, and secure communications because of its industrial temperature rating, 40 nm low-power process, and certified reliability flow. The 1152-ball FC-FBGA withstands high-vibration mounting when properly underfilled, and Altera/Intel's military pedigree includes long-term program support. Designers can implement real-time FFT, channelization, and crypto offload entirely on-chip.
おすすめ
ASIC Prototyping and Emulation
With 181,165 logic elements and abundant on-chip memory, the EP2AGX190FF35I5G emulates mid-complexity ASICs, especially designs dominated by bus fabrics, FIFOs, and custom peripherals. The 8-bit ALM architecture is backward-compatible with 4-input LUT designs, simplifying migration from older ASIC prototypes. Industrial temperature rating also lets prototype boards sit beside production hardware in accelerated life-test chambers.
おすすめ
Medical Imaging Systems
The EP2AGX190FF35I5G is well matched to medical imaging front-ends such as ultrasound beamformers, CT reconstruction pipelines, and endoscopy video processors. Its 12 transceivers aggregate raw data from high-speed ADCs, while 9.7 Mbit on-chip memory buffers line scan data before downstream processing. Industrial temperature rating also accommodates the wider thermal envelope of cart-based and portable diagnostic equipment.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP2AGX190FF35I5G — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP2AGX190FF35I3G | EP2AGX190FF35I5 | EP2AGX190FF35I3N | EP2AGX190FF35C6G | EP2AGX190FF35C5G | EP2AGX190FF35C4G |
|---|---|---|---|---|---|---|---|
| Package | 1152-BBGA, FC-FBGA | 1152-BBGA, FC-FBGA - same | 1152-BBGA, FC-FBGA - same | 1152-BBGA, FC-FBGA - same | 1152-BBGA, FC-FBGA - same | 1152-BBGA, FC-FBGA - same | 1152-BBGA, FC-FBGA - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 181,165 | 181,165 - same | 181,165 - same | 181,165 - same | 181,165 - same | 181,165 - same | 181,165 - same |
| Embedded Memory (bits) | 10,177,536 | 10,177,536 - same | 10,177,536 - same | 10,177,536 - same | 10,177,536 - same | 10,177,536 - same | 10,177,536 - same |
| User I/O | 612 | 612 - same | 612 - same | 612 - same | 612 - same | 612 - same | 612 - same |
| Speed Grade | I5 | I3 (faster) | I5 - same | I3 (faster, Pb-free N rev) | C6 (faster, commercial) | C5 (commercial) | C4 (commercial) |
| Operating Temperature | -40C to +100C (Industrial) | -40C to +100C (Industrial) | -40C to +100C (Industrial) | -40C to +100C (Industrial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
| Pb-free / RoHS | Pb-free (G suffix) | Pb-free (G suffix) | SnPb (no G suffix) | Pb-free (N rev) | Pb-free (G suffix) | Pb-free (G suffix) | Pb-free (G suffix) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND | NRND |
| Process Technology | 40 nm | 40 nm - same | 40 nm - same | 40 nm - same | 40 nm - same | 40 nm - same | 40 nm - same |
主な差別化要因
- Highest user I/O count in the FF35 family （vs EP2AGX190EF29I5G)
- Industrial temperature rating vs commercial-only alternatives （vs EP2AGX190FF35C5G)
- Faster speed grade available as drop-in （vs EP2AGX190FF35I3G)
設計ノート
The 1152-ball FC-FBGA package dissipates significant heat at full utilization of 181,165 logic elements plus 12 transceivers. Estimate: at 0.9 V core with typical logic toggling, internal dissipation can exceed 5 W, plus transceiver power of 100-300 mW per lane. Mount a thermal management solution (heat spreader, heatsink, or forced airflow) per Arria II GX Device Handbook thermal guidelines; otherwise junction temperature can overshoot the +100C industrial limit.
The 1152-ball FC-FBGA requires a high-layer-count PCB (typically 12-16 layers) with microvia-in-pad or stacked-microvia construction for breakout. Route differential SERDES pairs with 100 ohm differential impedance and length-matched within 150 mil per the Arria II GX transceiver layout guidelines. Provide continuous ground planes beneath the BGA for return-path integrity and to control SSO noise on the 612 user I/O.
Do not assume pin-compatibility between FF35 (1152-ball) and EF29 (780-ball) packages - they share the same die but have completely different pinouts. Verify the exact order code suffix carefully when sourcing: 'I' = industrial temp, 'C' = commercial, the trailing number (3/4/5/6/7) = speed grade (higher is faster), 'G' = Pb-free, 'N' = Pb-free newer revision. Mixing up speed grades causes timing closure failures; mixing up packages causes layout rework.
Estimated: total power budget at full utilization is approximately 8-12 W. The device requires multiple supply rails (0.9 V core, 1.1 V/1.2 V/1.5 V/2.5 V/3.0 V for transceiver PLL and I/O groups, plus 1.5 V/1.8 V DDR2/DDR3 reference). Use Altera's PowerPlay Early Power Estimator spreadsheet to size regulators before schematic capture. Decoupling must follow the per-bank capacitor count listed in the Arria II GX pin connection guidelines.
Place reference clocks near their associated transceiver banks and route them with controlled 50 ohm single-ended impedance; AC-couple the SERDES lines per the protocol-specific reference design. Keep JTAG and configuration pins (nCONFIG, nSTATUS, CONF_DONE, MSEL) accessible for in-system programming via the JTAG header or EPCS configuration device. Use the Quartus II pin planner with the FF35 FF1152 package file to validate pin assignments before layout.
コンプライアンス情報
G suffix in the order code indicates Pb-free lead finish per JEDEC J-STD-609; RoHS and REACH compliance was not present in the verified web data and is marked unknown. AEC-Q100 is not applicable to FPGAs. Confirm compliance with Intel's product declaration documents before regulated designs.
