Intel

EP2S60F672C5 - Stratix II FPGA 60K LEs 672-FBGA | Intel

Name: EP2S60F672C5 - Stratix II FPGA 60K LEs 672-FBGA | Intel
Brand: Intel
SKU: EP2S60F672C5
Price: 410.85 USD
Availability: InStock

部品番号: EP2S60F672C5 ✗ 生産終了

在庫あり 1〜3営業日以内に発送

1.2 V Vdss LVDS, LVTTL, SSTL, HSTL, PCI-X Rds(on) 672-ball FC-FBGA (35 × 35 mm, 1 mm pitch) Package Up to 609.76 MHz Speed

開始価格 $410.85 USD / 個

MOQ: 1 |

価格更新日: 2026-09-08

ボリューム価格

数量	単価	小計
1	$547.8	$547.80
5	$520.41	$2,602.05
10	$493.02	$4,930.20
25	$465.63	$11,640.75
100	$410.85	$41,085.00

ℹ️ すべての価格はUSDです

データシートを見る (PDF) 代替品を見る

数量

EP2S60F672C5 概要

The Intel EP2S60F672C5 is a Stratix II family Field-Programmable Gate Array (FPGA) delivering 60,440 logic elements, 2,544,192 bits of embedded memory, and 492 user I/Os in a 672-ball FineLine BGA (FBGA) package. Manufactured on a 90 nm CMOS process, this device operates at a core voltage of 1.2 V and supports internal clock rates up to 609.76 MHz per the FPGAkey parametric listing, providing the high-density programmable fabric required for ASIC prototyping, high-speed signal processing, and telecom infrastructure.

A Field-Programmable Gate Array (FPGA) is a type of integrated circuit containing an array of configurable logic blocks (CLBs), programmable interconnect, and dedicated hardware blocks such as memory, DSP slices, and high-speed transceivers. FPGAs sit in the broader semiconductor taxonomy as programmable logic devices, distinct from fixed-function ASICs because their logic function is defined post-manufacture via a configuration bitstream. Stratix II devices are positioned at the high-performance end of the FPGA market and were widely adopted for ASIC prototyping and high-throughput DSP.

Key features of the EP2S60F672C5 include 24,176 CLBs (configurable logic blocks) per the FindIC specification listing, 12 dedicated DSP blocks for hardware-accelerated multiplication, up to 36 embedded RAM blocks (M4K/M-RAM), and 4 phase-locked loops (PLLs) for clock management. The device also incorporates 8 high-speed transceiver channels on selected die revisions and supports LVDS, LVTTL, SSTL, and HSTL I/O standards. The 672-pin FC-FBGA package measures 35 mm × 35 mm with 1 mm ball pitch, enabling high-density board integration while maintaining signal integrity.

Architecturally, the Stratix II family introduced the adaptive logic module (ALM) concept, replacing traditional 4-input LUTs with 8-input fracturable LUTs that improve logic packing efficiency by 25–40%. Combined with the dedicated DSP blocks and TriMatrix memory, the EP2S60F672C5 supports sustained DSP throughput exceeding 300 GMACs at the rated core frequency, making it suitable for video processing, baseband modulation, and high-channel-count instrumentation.

Typical applications for the EP2S60F672C5 include ASIC and SoC prototyping, software-defined radio (SDR) baseband processing, military/aerospace signal processing, high-end medical imaging front-ends, and high-throughput wireline communication. Engineers continue to deploy this part in long-lifecycle industrial and defense platforms where the mature Quartus II toolchain and proven silicon reliability outweigh the benefits of newer families.

A key design consideration is that the EP2S60F672C5 operates in the commercial temperature range (0°C to +85°C) - the I4 and I5 suffixes denote industrial and extended temperature grades respectively. Designers should also note that Stratix II devices require a 1.2 V core supply with separate VCCIO bank voltages, and the configuration scheme (typically fast passive parallel or JTAG) must be selected during PCB layout.

This page synthesizes distributor pricing, parametric specifications, drop-in alternatives, and practical design considerations not found in the manufacturer datasheet alone.

ドロップイン代替品: EP2S60F672C5 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP2S60F672C5 （同一形状・フットプリント） — 相違点: Speed Grade, Package, Operating Temperature, RoHS Status, DSP Blocks.

EP2S15F672C4

Altera

Speed Grade: 4

Package: 672-ball FineLine BGA (FBGA)

Operating Temperature: Commercial (0C to +85C, 'C' suffix)

比較対象 EP2S60F672C5 →

EP2S60F672C3

Altera

Speed Grade: C3

Package: 672-BBGA, FC-FBGA, 35 x 35 mm, 1.0 mm pitch

Operating Temperature: 0C to +85C (commercial)

比較対象 EP2S60F672C5 →

EP2S60F672C4

Altera

Speed Grade: C4

Package: 672-BBGA, FCBGA

Operating Temperature: 0C to +85C (commercial)

比較対象 EP2S60F672C5 →

EP2S60F672C4N

Intel

Speed Grade: C4 (commercial)

Package: 672-pin FC-FBGA

Operating Temperature: 0C to +85C (commercial)

比較対象 EP2S60F672C5 →

EP2S60F672C5N

Altera

Speed Grade: C5 (commercial)

Package: 672-ball FC-FBGA

RoHS Status: Non-compliant (contains lead, per Altera/Intel EOL notice)

比較対象 EP2S60F672C5 →

EP2S60F672C5NGA

Intel

Speed Grade: C5

Operating Temperature: 0C to +85C (commercial, NGA variant)

RoHS Status: Compliant

比較対象 EP2S60F672C5 →

EP2S60F672I4

Intel

Speed Grade: -4

RoHS Status: Compliant

比較対象 EP2S60F672C5 →

✅ ドロップイン

Intel

📦 672-ball FC-FBGA

Stratix II · Stratix II FPGA · 60,440 · 3,022 · 2,544,192 · 492 · 90 nm CMOS · 1.2 V

✓ 在庫あり

$1050 / 個

データシートを見る →

EP2S60F672C5 最大定格＆電気的特性

Family	Stratix II
Device Family	Stratix II FPGA
Logic Elements	60,440
Configurable Logic Blocks (CLBs)	24,176
Total RAM Bits	2,544,192 bits
Maximum User I/Os	492
Operating Frequency	Up to 609.76 MHz
Core Voltage	1.2 V
Process Technology	90 nm CMOS
パッケージ	672-ball FC-FBGA (35 × 35 mm, 1 mm pitch)
実装タイプ	Surface Mount
Operating Temperature Grade	Commercial (C5 suffix)
動作温度範囲	0°C to +85°C
Number of PLLs	4
DSP Blocks	12 (dedicated 18 × 18 multipliers)
I/O Standards	LVDS, LVTTL, SSTL, HSTL, PCI-X
Configuration Scheme	Fast Passive Parallel, JTAG, Active Serial
RoHS ステータス	Non-RoHS (legacy product, pre-RoHS production runs)

EP2S60F672C5 ピン構成

ピン 1	I/O Bank 1 — User I/O pin (function varies by pin assignment)
ピン 168	GND — Ground reference
ピン 336	VCCINT — Core voltage 1.2 V supply
ピン 504	VCCIO — I/O bank voltage reference
ピン 672	I/O Bank 8 — User I/O pin (function varies by pin assignment)

主な用途

EP2S60F672C5 の用途: 6 件s: ASIC and SoC Prototyping, Software-Defined Radio Baseband, Video Processing and Image Pipelines, Telecom Wireline Infrastructure, Military and Aerospace Signal Processing, High-End Test and Measurement Instrumentation.

🖥️

ASIC and SoC Prototyping

The EP2S60F672C5's 60,440 logic elements and 2,544,192 bits of embedded RAM provide sufficient capacity to prototype mid-complexity ASIC and SoC designs before tape-out. Engineers map RTL designs into the Stratix II ALM architecture and verify functionality at hardware speeds, eliminating costly respins. The 492 user I/Os accommodate realistic stimulus and observation pads for full-system bring-up. Compared to simulation, hardware prototyping runs orders of magnitude faster and catches timing bugs that RTL simulation misses.

おすすめ

🌐

Software-Defined Radio Baseband

The EP2S60F672C5's 12 dedicated DSP blocks deliver hardware-accelerated multiplication and accumulation, enabling real-time baseband processing for software-defined radio (SDR) platforms. Combined with the 609.76 MHz internal clock rate and 24,176 CLBs, the device can implement FFTs, channelizers, and digital downconverters at sample rates exceeding 100 MSPS. The LVDS I/O support simplifies interface to high-speed ADCs and DACs common in SDR front-ends.

おすすめ

EP2S60F672C5N · Altera EP2S180F1020C5 · Intel

📺

Video Processing and Image Pipelines

The EP2S60F672C5 is well-suited to high-resolution video processing, including scaling, deinterlacing, color space conversion, and real-time video analytics. The 2,544,192 bits of embedded RAM support line buffers and frame buffers for 1080p and beyond, while the 492 I/Os accommodate parallel video buses such as BT.1120 and CameraLink interfaces. The dedicated DSP blocks enable real-time pixel processing without CPU offload overhead.

おすすめ

EP2S60F672I4 · Intel EP2S130F1508C5 · Altera

🌐

Telecom Wireline Infrastructure

The EP2S60F672C5's high logic density and dedicated DSP resources support line-card processing in central-office and aggregation telecom platforms. The Stratix II device handles channelized T1/E1 processing, framer/mapper functions, and packet classification at line rate, while the embedded M-RAM blocks provide deep packet buffering. The commercial temperature range and mature 90 nm silicon make it reliable for 24/7 telecom deployments.

おすすめ

EP2S60F672C4 · Altera EP2S90F1020C5 · Intel

✈️

Military and Aerospace Signal Processing

Defense and aerospace platforms continue to use the EP2S60F672C5 in long-lifecycle radar, electronic-warfare, and secure-communications systems because of its proven reliability and available industrial temperature variants (I4 suffix). The 60,440 logic elements enable real-time beamforming, pulse compression, and adaptive filtering in radar front-ends. Designers should source parts through AS6081-certified brokers to mitigate counterfeit risk on legacy silicon.

おすすめ

EP2S60F672I4 · Intel EP2S60F672I4N · Intel

🔧

High-End Test and Measurement Instrumentation

The EP2S60F672C5 supports digital oscilloscope, logic analyzer, and protocol analyzer front-end processing, where its 492 user I/Os and high-speed LVDS capability are essential for sampling at multi-GSPS rates. Real-time triggering, pattern matching, and protocol decoding all leverage the device's 24,176 CLBs and dedicated DSP blocks. The mature Quartus II toolchain ensures reproducible design implementation across multiple product revisions.

おすすめ

EP2S60F484C5 · Altera EP2S30F672C5 · Intel

おすすめ製品の概要

EP2S60F1020C5 Intel 使用用途: ASIC and SoC Prototyping EP2S130F1508C5 Altera 使用用途: ASIC and SoC Prototyping, Video Processing and Image Pipelines EP2S60F672C5N Altera 使用用途: Software-Defined Radio Baseband EP2S180F1020C5 Intel 使用用途: Software-Defined Radio Baseband EP2S60F672I4 Intel 使用用途: Video Processing and Image Pipelines, Military and Aerospace Signal Processing EP2S60F672C4 Altera 使用用途: Telecom Wireline Infrastructure EP2S90F1020C5 Intel 使用用途: Telecom Wireline Infrastructure EP2S60F672I4N Intel 使用用途: Military and Aerospace Signal Processing EP2S60F484C5 Altera 使用用途: High-End Test and Measurement Instrumentation EP2S30F672C5 Intel 使用用途: High-End Test and Measurement Instrumentation

What is the EP2S60F672C5 and what family does it belong to?

The EP2S60F672C5 is a member of Intel's Stratix II family of high-performance Field-Programmable Gate Arrays (FPGAs), built on a 90 nm CMOS process. According to the Intel/Altera Stratix II datasheet family, it delivers 60,440 logic elements, 24,176 CLBs, and 2,544,192 bits of embedded memory in a 672-ball FC-FBGA package. The 'C5' suffix indicates the commercial speed grade and 0°C to +85°C operating temperature range.

How many user I/Os does the EP2S60F672C5 provide?

The EP2S60F672C5 provides 492 user I/Os distributed across multiple I/O banks, supporting LVDS, LVTTL, SSTL, HSTL, and PCI-X signaling standards per the Stratix II device handbook. The 672-ball FC-FBGA package is the highest-density BGA offered for this die, enabling 492 user I/Os versus 364 on the 484-ball variant and 334 on the 1020-pin variant.

What core voltage does the EP2S60F672C5 require?

The EP2S60F672C5 requires a 1.2 V core supply (VCCINT) plus separate VCCIO bank voltages per I/O standard used. Per the Stratix II datasheet, VCCINT must be regulated within ±5% tolerance to maintain timing closure; designers typically use a dedicated linear or switching regulator with ±3% accuracy. The 1.2 V core is derived from the FPGA's internal 90 nm CMOS process and is shared across all Stratix II densities in the same speed grade.

Where can I download the EP2S60F672C5 datasheet PDF?

The official EP2S60F672C5 datasheet can be downloaded from the Intel Stratix II support page at intel.com/content/www/us/en/programmable/products/fpga/stratix-series/stratix-ii/support.html, which hosts the complete Stratix II Device Handbook, pin connection guidelines, and Quartus II device support files. Legacy Altera-dated copies are also mirrored on third-party sites such as Datasheets.com, FindIC, and FPGAkey, but the canonical PDF remains the Intel/Altera hosted version.

Is the EP2S60F672C5 still in production or has it been discontinued?

The EP2S60F672C5 is an obsolete/end-of-life part. Intel (which acquired Altera in 2015) officially discontinued the Stratix II family, and new silicon is no longer manufactured. According to the DigiKey listing and reseller inventories, remaining stock is available only through authorized distributors or the secondary/open market. Long-lifecycle defense, aerospace, and industrial customers continue to source parts via franchised brokers.

What is the operating temperature range of the EP2S60F672C5?

The 'C5' suffix in EP2S60F672C5 denotes the commercial temperature grade, supporting an operating junction temperature of 0°C to +85°C per the Stratix II device handbook. Industrial and extended-temperature variants are identified by 'I4' (-40°C to +100°C) and 'I5' (-40°C to +125°C) suffixes respectively - these are pin-compatible drop-in alternatives where the same 672-ball FC-FBGA footprint is retained.

How much embedded memory does the EP2S60F672C5 contain?

The EP2S60F672C5 integrates 2,544,192 bits of embedded RAM organized into TriMatrix memory blocks (M512, M4K, and M-RAM blocks). According to the Stratix II datasheet, the EP2S60 variant provides approximately 1.5 Mbits of M4K RAM plus dedicated M-RAM blocks for deep buffering, ideal for packet storage in telecom and line-buffer applications in video processing.

What is the difference between EP2S60F672C5 and EP2S60F672C4?

The EP2S60F672C5 and EP2S60F672C4 differ only in the speed grade. The C5 suffix indicates a faster speed bin than C4, allowing higher Fmax on internal logic and DSP blocks at the same VCCINT. Both share identical logic capacity (60,440 LEs), the same 672-ball FC-FBGA package, and the same commercial temperature range. The C5 can always be substituted for C4 with timing margin to spare; the C4 substituted for C5 may violate timing closure at maximum clock rates.

What is the difference between EP2S60F672C5 and EP2S60F672C3?

The EP2S60F672C5 is the fastest speed grade in the Stratix II family for commercial temperatures, while the C3 suffix denotes a slower speed bin. Both use the same 60,440 LE die and the same 672-ball FC-FBGA package - they are fully pin-compatible drop-in alternatives. The ETEI comparison guide confirms that pinout, package, and electrical interface are identical; only Fmax differs.

What is the current price of EP2S60F672C5?

As of 2026-09-09, the EP2S60F672C5 is listed at approximately US $547.80 per unit at qty 1, with volume pricing around US $410.85 at qty 100, based on SeekIC and aggregated distributor listings. Because the part is obsolete and no longer in production, pricing fluctuates significantly based on lot date code and remaining inventory. Engineers should request a current quote rather than rely on historical pricing.

Where can I buy EP2S60F672C5 in stock today?

As of 2026-09-09, the EP2S60F672C5 can be sourced through franchised distributors carrying legacy Altera/Intel inventory including DigiKey, Mouser, and Avnet, plus open-market suppliers such as Lisleapex, IC-1101, Avaq, Veswin, and Alter Semiconductor. For long-lifecycle defense and aerospace programs, franchised brokers with AS6081 certification are recommended. Stock levels fluctuate weekly - check the live distributor inventory before placing orders.

What is the lead time for EP2S60F672C5?

Lead time for the obsolete EP2S60F672C5 varies from immediate shipment (when in stock at authorized distributors) to 8-12 weeks for special orders from open-market suppliers. Because no new silicon is being produced, lead times are inventory-driven and may extend further as remaining stock depletes. Engineering teams should qualify a second-source or pin-compatible Stratix II variant (such as EP2S60F672C4N) for risk mitigation.

Can the EP2S60F672C5 be replaced with EP2S60F672C5N?

Yes, the EP2S60F672C5N is the same Stratix II die and same 672-ball FC-FBGA package with the addition of lead-free/RoHS-compliant terminal finish (the 'N' suffix indicates lead-free per Altera/Intel nomenclature). Per the Stratix II datasheet, both parts share identical logic capacity, I/O count, and speed grade - they are drop-in pin-to-pin compatible. Choose the N variant for new designs requiring RoHS compliance.

What is the best drop-in replacement for EP2S60F672C5?

The best drop-in replacement for the EP2S60F672C5 is the EP2S60F672C5N, which uses the same die and 672-ball FC-FBGA package but adds lead-free RoHS-compliant terminal finish. For industrial temperature applications, the EP2S60F672I4N offers the same logic capacity in the same package with -40°C to +100°C support. Both alternatives share the same Stratix II architecture, Quartus II toolchain support, and bitstream compatibility.

EP2S60F672C5 vs EP2S60F1020C5 - which is better for high-I/O designs?

The EP2S60F1020C5 has the same 60,440 LE logic capacity as the EP2S60F672C5 but is housed in a larger 1020-pin package that supports 718 user I/Os versus 492 on the F672 variant. For high-I/O designs that require more than 492 user pins, the EP2S60F1020C5 is the correct choice. For designs where 492 I/Os are sufficient, the smaller EP2S60F672C5 package saves PCB area and reduces BGA routing complexity.

エンジニアリング参考データ: EP2S60F672C5 — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose the EP2S60F672C5 when you need the highest speed grade in the Stratix II family for ASIC/SoC prototyping or signal-processing applications at maximum Fmax. The C5 speed bin provides the most timing margin but commands the highest price; if your design closes timing comfortably, the EP2S60F672C4 or C3 deliver identical logic capacity at lower cost. Choose the EP2S60F672C5N for new commercial products requiring RoHS compliance - it is electrically identical to the C5 with lead-free terminal finish only. For industrial or defense applications requiring -40°C to +100°C support, select the EP2S60F672I4 instead. Because all five alternatives share the same 672-ball FC-FBGA footprint, PCB layout is reusable across variants - only the bitstream and lot-date code differ.

代替品との比較

パラメータ	この製品	EP2S60F672C5N	EP2S60F672C4	EP2S60F672C3	EP2S60F672C4N	EP2S60F672I4
Brand	Intel	Intel	Intel	Intel	Intel	Intel
Package	672-ball FC-FBGA	672-ball FC-FBGA - same	672-ball FC-FBGA - same	672-ball FC-FBGA - same	672-ball FC-FBGA - same	672-ball FC-FBGA - same
Logic Elements	60,440	60,440	60,440	60,440	60,440	60,440
User I/Os	492	492	492	492	492	492
Speed Grade	C5 (fastest commercial)	C5	C4	C3 (slowest)	C4	I4
Temperature Grade	Commercial (0°C to +85°C)	Commercial	Commercial	Commercial	Commercial	Industrial (-40°C to +100°C)
Lead-Free / RoHS	Non-RoHS	RoHS-compliant (N suffix)	Non-RoHS	Non-RoHS	RoHS-compliant (N suffix)	Non-RoHS
Process / Core Voltage	90 nm / 1.2 V	90 nm / 1.2 V	90 nm / 1.2 V	90 nm / 1.2 V	90 nm / 1.2 V	90 nm / 1.2 V

主な差別化要因

Highest speed grade in Stratix II family （vs EP2S60F672C4)
Lead-free RoHS compliance option （vs EP2S60F672C5)
Industrial temperature grade option （vs EP2S60F672C5)

設計ノート

The Stratix II EP2S60F672C5 requires a regulated 1.2 V core supply (VCCINT) with ±5% tolerance and separate VCCIO bank voltages per I/O standard used. Power sequencing requirements: VCCINT must ramp before or simultaneously with VCCIO to avoid latch-up; all VCC rails must reach steady state within 100 ms. Estimated: at maximum toggle activity, the EP2S60 consumes 8-12 W from VCCINT; designers should budget at least 15 W for core supply headroom and provide adequate bulk decoupling.

The 672-ball FC-FBGA package uses 1 mm ball pitch and requires microvia (HDI) PCB technology for breakout routing. At least 6 PCB layers are recommended: a dedicated ground plane beneath the BGA, two signal layers for breakouts, two power planes for VCCINT and VCCIO, and a top layer for component placement. Use a 4-layer stack-up at minimum - this requires blind/buried vias and increases PCB cost. Maintain continuous ground reference beneath all high-speed LVDS traces.

Do not confuse speed grade suffix letters: C5 is the fastest commercial bin, C4 and C3 are progressively slower, and I4/5 are industrial temperature bins. Using C3 in a design that requires C5 timing may fail timing closure. Configuration mode selection (FPP, AS, JTAG) is committed in the Quartus II project - changing it post-compile requires recompilation. For obsolete parts, always verify lot date codes and source from franchised distributors to avoid counterfeit risk.