ラストタイムバイのお知らせ: EP2SGX90FF1152 は生産終了が近づいています。最終注文日: お問い合わせ. 利用可能な代替部品を見る →
Altera

EP2SGX90FF1152 - 90K LE Stratix II GX FPGA, 1152-BGA | Altera

部品番号: EP2SGX90FF1152 ⚠ ラストタイムバイ
在庫あり 1〜3営業日以内に発送
1.2 V Vdss 1152-ball FC-FBGA (Flip-Chip) Package 4,520,448 Memory
開始価格 $1425 USD / 個
MOQ: 1 |
価格更新日: 2026-09-08
ボリューム価格
数量 単価 小計
1 $1850 $1,850.00
10 $1750 $17,500.00
100 $1650 $165,000.00
500 $1525 $762,500.00
1,000 $1425 $1,425,000.00
ℹ️ すべての価格はUSDです

EP2SGX90FF1152 概要

The Altera (Intel) EP2SGX90FF1152 is a high-density Stratix II GX Field Programmable Gate Array (FPGA) integrating 90,960 logic elements, 4,520,448 bits of embedded memory, and 558 user I/Os with up to 20 multi-gigabit transceivers in a 1152-ball flip-chip BGA (FC-FBGA) package. As a member of the Stratix II GX family, this device combines high-performance logic fabric with embedded 6.375 Gbps transceivers, making it suited for high-speed serial I/O and DSP-intensive applications.

A Field Programmable Gate Array (FPGA) is a semiconductor integrated circuit based on a matrix of configurable logic blocks (CLBs) connected via programmable interconnect. Within the IC hierarchy, an FPGA sits below Application-Specific Integrated Circuits (ASICs) but above general-purpose microcontrollers in terms of performance and flexibility. The Stratix II GX family specifically targets high-speed serial connectivity by embedding dedicated transceiver hard IP blocks alongside the programmable fabric.

Key features of the EP2SGX90FF1152 include 4,548 Logic Array Blocks (LABs), 4,520,448 RAM bits, embedded multiplier blocks (18x18), and adaptive logic modules (ALMs) per LAB. The device supports multiple I/O standards including LVDS, LVCMOS, LVTTL, and HSTL/SSTL for memory interfacing. Transceivers operate up to 6.375 Gbps, supporting protocols such as PCI Express, Serial RapidIO, XAUI, and Gigabit Ethernet without external PHY devices.

Architecturally, the Stratix II GX employs a true 8-input fracturable ALM structure that improves logic packing density over the previous Stratix generation. Embedded transceivers use hard PCS (Physical Coding Sublayer) blocks with on-chip PLLs and clock-data recovery, reducing FPGA fabric usage for serial protocols. The 1.2 V core voltage with dedicated transceiver supply rails is typical for the 90 nm process node used in this family.

Typical applications include high-end telecommunications line cards, high-speed data acquisition systems, digital video broadcasting equipment, and wireline backplane designs. The combination of transceivers, abundant memory, and high logic capacity also suits it for ASIC prototyping and signal processing subsystems.

When designing with this FPGA, ensure your PCB BGA layout supports the 1152-ball flip-chip package with proper microvia stack-up and matched-length transceiver routing. Decoupling must follow Altera's Stratix II GX pin connection guidelines, and configuration scheme selection (AS, PS, JTAG) should be finalized before PCB layout finalization.

This page consolidates distributor pricing, drop-in same-package alternatives from the Stratix II GX family, and practical design considerations beyond the datasheet to help engineers select and source this mature FPGA for long-lifecycle designs.

ドロップイン代替品: EP2SGX90FF1152 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP2SGX90FF1152 (同一形状・フットプリント) — 相違点: Package, Operating Temperature, Speed Grade, Family, Transceivers.

Intel
Operating Temperature: 0C to +85C (Commercial)
Speed Grade: EF
Family: Stratix II GX
比較対象 EP2SGX90FF1152 →
Intel
Package: 1152-BBGA / FC-FBGA-1152
Operating Temperature: Commercial (0C to +85C)
Speed Grade: C4
比較対象 EP2SGX90FF1152 →
Intel
Package: 1152-ball FC-FBGA
Operating Temperature: 0C to +85C (Commercial)
Speed Grade: 5
比較対象 EP2SGX90FF1152 →
Intel
Package: 1152-BBGA (FBGA-1152, MS-034AAR-1)
Operating Temperature: -40C to +100C (Industrial)
Family: Stratix II GX
比較対象 EP2SGX90FF1152 →
Altera
Package: 1152-BBGA, FCBGA (FF1152)
Operating Temperature: 0C to +85C (commercial, C3)
Speed Grade: C3
比較対象 EP2SGX90FF1152 →

クイック比較ツール — 並列比較する代替部品を選択:

EP2SGX90EF1152C4N

✅ ドロップイン
Intel
📦 1152-ball FC-FBGA
Stratix II GX · 90,960 · 4,548 · 4,520,448 bits · 558 · 1.2 V · 90 nm

✓ 在庫あり

$695 / 個

データシートを見る →

EP2SGX90EF1152C5N

✅ ドロップイン
Intel
📦 1152-ball FC-FBGA
Stratix II GX · FPGA - Field Programmable Gate Array · 90,960 · 4,548 · 4,520,448 · 558 · 1.2 V

✓ 在庫あり

$1380 / 個

データシートを見る →

EP2SGX90EF1152I4N

✅ ドロップイン
Intel
📦 1152-ball FC-FBGA
Stratix II GX · 90,960 · 4,520,448 · 4,548 · 90,960 · 4,520,448 · 558 · 12

✓ 在庫あり

$1550 / 個

データシートを見る →

EP2SGX90EF1152C3N

✅ ドロップイン
Intel
📦 1152-ball FC-FBGA
Stratix II GX · Stratix II GX · 90960 · 4548 · 4520448 · 558 · 90 nm

✓ 在庫あり

$1280 / 個

データシートを見る →

EP2SGX90EF1152I5N

✅ ドロップイン
Intel
📦 1152-ball FC-FBGA
Stratix II GX · EP2SGX90 · 90,960 · 90,960 · 90 nm CMOS · 1.2 V · 609.76 MHz · 4.006 ns

✓ 在庫あり

$1320 / 個

データシートを見る →

EP2SGX90FF1152C3

✅ ドロップイン
Altera
📦 1152-ball FC-FBGA
Stratix II GX · 90960 · 4520448 bits (4.5 Mbit TriMatrix) · 4548 · 558 · 0C to +85C (commercial, C3) · 1152-BBGA, FCBGA (FF1152)

✓ 在庫あり

$320 / 個

データシートを見る →

EP2SGX90FF1152 最大定格&電気的特性

Series Stratix II GX
Family FPGA
Logic Elements (LE) 90,960
Logic Array Blocks (LABs) 4,548
Embedded Memory (RAM bits) 4,520,448
User I/Os 558
Transceivers Up to 20 channels
Transceiver Data Rate Up to 6.375 Gbps
Core Voltage 1.2 V
Process Node 90 nm
パッケージ 1152-ball FC-FBGA (Flip-Chip)
実装タイプ Surface Mount
RoHS ステータス Compliant
Lead-Free Yes

EP2SGX90FF1152 1152-ball fc-fbga (flip-chip) ピン配置ガイド

EP2SGX90FF1152 (1152-ball fc-fbga (flip-chip) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。

EP2SGX90FF1152 の 1152-ball fc-fbga (flip-chip) パッケージピン配置図

詳細なピン配置データはありません: EP2SGX90FF1152.

詳細は データシート をご参照ください。

主な用途

EP2SGX90FF1152 の用途: 6 件s: High-Speed Telecommunications Line Cards, ASIC Prototyping and Emulation, Digital Video Broadcasting Equipment, Wireline Backplane Aggregation, High-Speed Data Acquisition Systems, Military and Aerospace Signal Processing.

🌐

High-Speed Telecommunications Line Cards

The EP2SGX90FF1152's 20 embedded transceivers at up to 6.375 Gbps make it ideal for telecom line cards handling multi-protocol serial traffic. Its 90,960 logic elements and 4,520,448 RAM bits enable on-chip packet processing and buffering. Placed as the central fabric between framer/phy devices and network processor ASICs, it eliminates external glue logic. Trade-off: 90 nm process yields higher power per channel than modern 28 nm Stratix V, but lifecycle maturity suits telecom refresh cycles.

🖥️

ASIC Prototyping and Emulation

The EP2SGX90FF1152's high logic capacity (90,960 LEs) and abundant interconnect make it well-suited to ASIC prototyping platforms. Engineers can partition large ASIC RTL into multiple FPGAs via the Stratix II GX native multi-FPGA partitioning flow. The 4,520,448 embedded RAM bits provide ample trace memory for debug. Unlike ASICs, the prototype is fully re-programmable, enabling fast iteration. Trade-off: ASIC frequency is 3-5x faster than FPGA prototypes, so timing closure requires careful synthesis constraints.

📺

Digital Video Broadcasting Equipment

The EP2SGX90FF1152 supports HD-SDI and 3G-SDI serial video interfaces via its embedded transceivers at 1.485 Gbps and 2.97 Gbps respectively. Its DSP blocks accelerate video processing functions such as scaling, de-interlacing, and color space conversion. The 558 user I/Os allow direct connection to DDR2 memory and video ADCs/DACs. Placed as the central video pipeline processor, it eliminates multiple ASSPs. Trade-off: video processing latency is deterministic but higher than purpose-built video SoCs.

🌐

Wireline Backplane Aggregation

The EP2SGX90FF1152's transceivers support XAUI (4x3.125 Gbps), Serial RapidIO, and PCIe Gen1/Gen2 for wireline backplane aggregation across ATCA or AdvancedMC shelves. The hard PCS implements 8b/10b encoding without consuming fabric logic, freeing LEs for switching and queuing functions. 4,520,448 RAM bits provide packet buffering at line rate. Trade-off: backplane routing requires careful signal integrity design; consult the Stratix II GX board design guidelines.

📡

High-Speed Data Acquisition Systems

The EP2SGX90FF1152's transceivers connect directly to high-speed ADCs and DACs via JESD204B (subclass support depends on soft IP) or LVDS interfaces. The embedded 18x18 multipliers and DSP blocks accelerate FFT, FIR, and digital down-conversion in software-defined radio pipelines. 558 I/Os allow direct parallel LVDS ADC connection up to 1 Gsps. Placed between the analog front-end and host processor, it performs real-time DSP. Trade-off: 90 nm static power is higher than modern 28/20 nm FPGAs.

✈️

Military and Aerospace Signal Processing

The EP2SGX90FF1152 (industrial temperature grade variants) is suitable for military and aerospace signal processing subsystems including radar, electronic warfare, and satellite communications. Its transceivers handle high-speed data links to RF converters, and abundant logic supports beamforming and channelization algorithms. Long lifecycle support makes it suited to programs with 10-15 year deployment horizons. Trade-off: full MIL-PRF screening is not available; commercial/industrial grade only.

What is the EP2SGX90FF1152?
The EP2SGX90FF1152 is an Altera (now Intel) Stratix II GX FPGA with 90,960 logic elements, 4,520,448 RAM bits, 558 user I/Os, and up to 20 embedded multi-gigabit transceivers, housed in a 1152-ball FC-FBGA flip-chip BGA package. It belongs to the Stratix II GX family of high-speed transceivers on 90 nm process node.
How much does the EP2SGX90FF1152 cost?
The EP2SGX90FF1152 is priced approximately $1,850 USD per unit at qty-1 and around $1,425 USD per unit at qty-1000, as of 2026-09-09 per distributor listings on Jotrin and DigiKey. Pricing reflects its mature lifecycle status and limited remaining supply. Request a formal quote for volume pricing.
Where to buy EP2SGX90FF1152 online?
The EP2SGX90FF1152 can be purchased from authorized distributors including DigiKey, Mouser, Arrow Electronics, and Jotrin Electronics as of 2026-09-09. Because the part is in Last Time Buy status, supply is limited and lead times may extend. XAIPART also offers sourcing for this mature FPGA.
What is the lead time for EP2SGX90FF1152?
Lead time for the EP2SGX90FF1152 is typically 8-16 weeks as of 2026-09-09, due to its Last Time Buy lifecycle status. Distributor stock is limited; contact franchised distributors for current availability. Long-term production designs should consider migrating to Stratix IV GX or Stratix V GX families.
Is EP2SGX90FF1152 still in production?
The EP2SGX90FF1152 is in Last Time Buy (LTB) status as of 2026-09-09 per Intel/Altera's product discontinuation notices. Last orders must be placed before the final buy date. The Stratix II GX family is mature; new designs should target Stratix V or Cyclone V GX.
What is the difference between EP2SGX90FF1152 and EP2SGX90EF1152C4N?
The EP2SGX90FF1152 is the Last Time Buy variant in the standard speed grade, while the EP2SGX90EF1152C4N is a C4 speed grade part also in 1152-BGA with enhanced features. Both share the same 90,960 LE, 4,520,448 RAM, and 558 I/O counts per the Stratix II GX datasheet, but differ in speed bin and ordering code suffix.
What is the difference between EP2SGX90FF1152 and EP2SGX130GF40I4N?
The EP2SGX90FF1152 has 90,960 logic elements in a 1152-ball BGA, while the EP2SGX130GF40I4N offers 130,000 logic elements in a smaller 40mm 1508-ball BGA. The 130-device is in the Stratix II GX family but with higher density. They are not pin-to-pin compatible despite both being Stratix II GX.
Can EP2SGX130GF40I4N replace EP2SGX90FF1152?
No, the EP2SGX130GF40I4N cannot replace the EP2SGX90FF1152 as a drop-in because they use different BGA packages (1508-ball vs 1152-ball) with different ball maps. Both are Stratix II GX family members, but PCB rework is required. Migration from 90K to 130K density requires board redesign.
When should I choose EP2SGX90FF1152 over newer Stratix families?
Choose the EP2SGX90FF1152 when maintaining a legacy Stratix II GX design for which tooling, firmware, and qualification costs make migration prohibitive. For new designs, choose Stratix V GX, Cyclone V GX, or newer Intel Agilex FPGAs. The EP2SGX90FF1152 is best suited to long-lifecycle industrial or military programs.
Is EP2SGX90FF1152 suitable for new designs?
The EP2SGX90FF1152 is not recommended for new designs as of 2026-09-09 because it is in Last Time Buy lifecycle status. For new designs, select from active families: Cyclone V GX (low power), Arria V GX (mid-range), or Stratix V GX (high-performance). Use EP2SGX90FF1152 only for legacy maintenance.
Where to download EP2SGX90FF1152 datasheet PDF?
The Stratix II GX device handbook containing EP2SGX90FF1152 specifications can be downloaded from the Intel Altera website. Per the manufacturer datasheet, the device handbook covers transceiver definitions, internal architecture, configuration, JTAG boundary-scan, DC operating conditions, AC timing, and ordering information.
Where to find EP2SGX90FF1152 pinout and ball map?
The EP2SGX90FF1152 pinout and 1152-ball FC-FBGA ball map is documented in the Stratix II GX Device Handbook, specifically in the pin-out tables and package specifications section. The datasheet also lists transceiver channel assignments and pin connection guidelines for unused pins.
What is the maximum transceiver speed of EP2SGX90FF1152?
The EP2SGX90FF1152 transceivers support data rates up to 6.375 Gbps per channel. This enables protocols such as PCI Express Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), Serial RapidIO, XAUI (3.125 Gbps), and Gigabit Ethernet. Hard PCS blocks implement 8b/10b encoding and clock-data recovery on-chip.
What is the difference between Stratix II and Stratix II GX FPGAs?
Stratix II GX FPGAs extend the Stratix II family with embedded multi-gigabit transceivers (up to 6.375 Gbps in EP2SGX90) and dedicated PCS hard IP. Standard Stratix II devices lack transceivers and rely on external PHY chips for serial protocols. Stratix II GX is therefore preferred for high-speed serial I/O designs.
What is the best Stratix II GX equivalent from Intel for new designs?
For new designs as of 2026-09-09, the best Intel equivalents are Stratix V GX (5SGXMA7) for high-performance transceiver applications and Cyclone V GX (5CGXFC7) for cost-optimized designs. Both provide higher logic density, lower power, and modern transceivers up to 12.5 Gbps (Stratix V) or 3.125 Gbps (Cyclone V).

エンジニアリング参考データ: EP2SGX90FF1152 — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose EP2SGX90FF1152 for new Stratix II GX designs requiring the default speed grade and commercial temperature. Choose EP2SGX90EF1152C4N if you need tighter timing margin for high-speed designs (the most common drop-in alternative). Choose EP2SGX90EF1152C5N for the fastest speed grade; choose EP2SGX90EF1152C3N if you have timing margin and want to optimize cost. Choose EP2SGX90EF1152I4N or EP2SGX90EF1152I5N for industrial temperature operation. All six variants share the identical 1152-ball FC-FBGA footprint and pinout, allowing a single PCB design to accept any bin. For new designs in 2026, consider migrating to active families such as Cyclone V GX or Stratix V GX instead, as the entire Stratix II GX family is in Last Time Buy.

代替品との比較

パラメータ この製品 EP2SGX90EF1152C4N EP2SGX90EF1152C5N EP2SGX90EF1152I4N EP2SGX90EF1152C3N EP2SGX90EF1152I5N
Package 1152-ball FC-FBGA 1152-ball FC-FBGA - same 1152-ball FC-FBGA - same 1152-ball FC-FBGA - same 1152-ball FC-FBGA - same 1152-ball FC-FBGA - same
Brand Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel)
Logic Elements 90,960 90,960 90,960 90,960 90,960 90,960
Embedded Memory (RAM bits) 4,520,448 4,520,448 4,520,448 4,520,448 4,520,448 4,520,448
User I/Os 558 558 558 558 558 558
Speed Grade unspecified (default) C4 (mid) C5 (fast) I4 (industrial) C3 (slow) I5 (industrial fast)
Temperature Grade unspecified (default commercial) Commercial Commercial Industrial Commercial Industrial
Lifecycle Status Last Time Buy Last Time Buy Last Time Buy Last Time Buy Last Time Buy Last Time Buy
Transceiver Channels Up to 20 Up to 20 Up to 20 Up to 20 Up to 20 Up to 20
Transceiver Max Data Rate 6.375 Gbps 6.375 Gbps 6.375 Gbps 6.375 Gbps 6.375 Gbps 6.375 Gbps

主な差別化要因

  • Drop-in compatible speed grade and temperature options (vs EP2SGX90EF1152C4N)
  • Industrial temperature range availability in same package (vs EP2SGX90EF1152I4N)
  • Six available drop-in speed/temperature bins for supply flexibility (vs EP2SGX90EF1152C5N)

設計ノート

The 1152-ball FC-FBGA package requires high-density PCB interconnect with microvia stack-up (typically 8-12 layers). Use 0.4mm or 0.5mm pitch BGA escape routing with via-in-pad or dog-bone fanout. Maintain 50 ohm controlled impedance for transceiver channels and matched-length routing within the tolerances specified in the Stratix II GX Device Handbook. Decoupling requires dozens of 0.1 uF and 10 uF ceramic capacitors placed as close to power balls as possible to suppress transient current demand during logic switching.

Estimated: Stratix II GX devices at 90 nm have core current of several amps at 1.2 V plus separate transceiver and I/O supply rails. Use a multi-rail power distribution network with bulk decoupling on each rail and follow Altera's power distribution network (PDN) design guidelines. Include power-on-reset sequencing to ensure proper rail ramp order and avoid latch-up. Estimated total power dissipation under typical utilization can reach 10-20 W, requiring thermal management.

Transceiver channels operating at 6.375 Gbps require pre-emphasis and equalization configuration. Use the Altera Quartus II Transceiver Toolkit to characterize channel performance and tune pre-emphasis, VOD (voltage output differential), and receiver CTLE settings. Reference clock jitter must be below the value specified in the Stratix II GX datasheet for the chosen protocol. Maintain 100 ohm differential impedance on transceiver pairs with matched P/N lengths within 150 mil.

Do not leave unused transceiver channels floating - tie per the Stratix II GX pin connection guidelines. Configuration mode (AS/PS/JTAG) must be selected via MSEL pins and matches the chosen configuration device (e.g., EPCS64). Avoid using I/O standards without checking voltage compatibility with bank VCCIO supplies. When migrating from other FPGA families, recompile all RTL in Quartus II; do not assume bitstream compatibility.

コンプライアンス情報

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Applicable
鉛フリー
Yes
ハロゲンフリー
Unknown
紛争鉱物
Compliant

RoHS compliant per Altera/Intel product page. AEC-Q100 not applicable for FPGAs. Halogen-free status not explicitly stated in the verified web data.

データ検証日: 2026-09-09 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

関連検索

EP2SGX90FF1152 datasheet EP2SGX90FF1152 price EP2SGX90FF1152 buy EP2SGX90FF1152 alternative EP2SGX90FF1152 drop-in replacement Stratix II GX 1152 BGA FPGA Altera Stratix II GX 90K logic elements EP2SGX90FF1152 last time buy EP2SGX90FF1152 vs EP2SGX90EF1152C4N FPGA 6.375 Gbps transceiver EP2SGX90FF1152 pinout ball map where to buy EP2SGX90FF1152

関連部品&用語

Altera Intel EP2SGX90FF1152 EP2SGX90EF1152C4N EP2SGX90EF1152C5N EP2SGX90EF1152I4N EP2SGX90EF1152C3N EP2SGX90EF1152I5N Stratix II GX FPGA Field Programmable Gate Array Logic Array Block LAB Adaptive Logic Module ALM FC-FBGA Flip-Chip BGA Multi-Gigabit Transceiver PCI Express Serial RapidIO XAUI Quartus II RoHS Last Time Buy industrial temperature grade
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