Altera

EP2SGX90FF1152C3 - Stratix II GX FPGA 90K LE | Intel | Altera

部品番号: EP2SGX90FF1152C3 ✗ 生産終了

在庫あり 1〜3営業日以内に発送

1152-BBGA, FCBGA (FF1152) Package C3 Speed 4520448 bits (4.5 Mbit TriMatrix) Memory

開始価格 $320 USD / 個

MOQ: 1 |

価格更新日: 2026-09-08

ボリューム価格

数量	単価	小計
1	$450	$450.00
10	$410	$4,100.00
25	$380	$9,500.00
100	$345	$34,500.00
250	$320	$80,000.00

ℹ️ すべての価格はUSDです

データシートを見る (PDF) 代替品を見る

数量

EP2SGX90FF1152C3 概要

The Altera EP2SGX90FF1152C3 is a high-density Stratix II GX FPGA built on a 90-nm process, integrating 90960 logic elements and 4,520,448 RAM bits in a 1152-ball fine-pitch BGA (FF1152) package. It combines a 4.5 Mb embedded memory, 252 18x18 multipliers, and 4 enhanced PLLs with 16 global clock networks. The 'C3' speed grade and 'F' package prefix indicate a 1152-pin flip-chip BGA suitable for high-I/O-count designs.

A Field Programmable Gate Array (FPGA) is a programmable semiconductor whose logic fabric, routing, and I/O can be reconfigured after manufacturing. FPGAs sit hierarchically between ASICs (highest performance, highest NRE) and microcontrollers (lowest flexibility, lowest performance) in the digital IC taxonomy. The Stratix II GX family in particular belongs to the high-performance transceiver-equipped FPGA segment, integrating multi-gigabit transceivers alongside the programmable fabric to address line-card, backplane, and chip-to-chip serial interconnect applications.

Key features of the EP2SGX90FF1152C3 include 4.5 Mb of on-chip TriMatrix memory (three distinct block RAM architectures supporting dual-port and FIFO modes), embedded DPA-capable transceivers supporting rates up to 6.375 Gbps, 4 enhanced PLLs plus 8 fast PLLs, and 558 maximum user I/O pins. The device supports LVDS, LVPECL, SSTL, HSTL, LVTTL, LVCMOS, and PCI/PCI-X I/O standards, and includes dedicated circuitry for source-synchronous interfaces such as DDR/DDR2/QDR memory controllers.

Architecturally, the Stratix II GX uses Altera's adaptive logic module (ALM) structure - an 8-input fracturable LUT that can implement any 6-input LUT function plus extra logic, allowing finer-grained logic packing than earlier Stratix families. Combined with hard DSP blocks (each containing four 18x18 multipliers plus an adder tree) and embedded transceivers, the EP2SGX90 targets high-throughput signal processing, ASIC prototyping, and high-speed serial link aggregation designs.

Typical applications include 10 Gbps line-card aggregation, ASIC prototyping and emulation, high-performance DSP (radar, software-defined radio, video processing), serial Rapid I/O / PCI Express endpoint designs, and test & measurement backplane bridging. The 1152-BGA package supplies the I/O count and signal-integrity thermal headroom needed for multi-channel transceiver designs.

Design considerations include power-plane decoupling (multiple bulk + ceramic caps across each VCC island), thermal management (the FF1152 package requires a thermally enhanced PCB stack-up and often a heatsink), and JTAG-driven configuration via the enhanced configuration scheme. Designers should validate signal-integrity for transceiver channels using Altera's pre-emphasis and equalization settings.

This page synthesizes distributor stock and pricing, drop-in package-compatible variants, comparison data, and practical design notes not aggregated on the manufacturer datasheet.

ドロップイン代替品: EP2SGX90FF1152C3 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP2SGX90FF1152C3 （同一形状・フットプリント） — 相違点: Package, Operating Temperature, RoHS Status, Transceivers, Mounting Type.

EP2SGX90EF1152C3

Intel

Package: 1152-FBGA (FineLine BGA)

Operating Temperature: 0C to +85C (commercial)

Mounting Type: Surface Mount (BGA)

比較対象 EP2SGX90FF1152C3 →

EP2SGX90EF1152C3N

Intel

Operating Temperature: 0C to +85C (Commercial)

比較対象 EP2SGX90FF1152C3 →

EP2SGX90EF1152C4

Altera

RoHS Status: RoHS Compliant

比較対象 EP2SGX90FF1152C3 →

EP2SGX90EF1152C5

Intel

Package: 1152-BBGA, FCBGA

Operating Temperature: Commercial grade (C5)

RoHS Status: Compliant (per distributor listings)

比較対象 EP2SGX90FF1152C3 →

EP2SGX90EF1152I4

Altera

Package: 1152-ball FC-FBGA

Mounting Type: Surface Mount (BGA)

比較対象 EP2SGX90FF1152C3 →

EP2SGX90EF1152I5

Intel

Package: 1152-ball FineLine BGA (FBGA-1152)

RoHS Status: Compliant

Transceivers: Up to 20 multi-gigabit transceivers at 6.375 Gbps

比較対象 EP2SGX90FF1152C3 →

✅ ドロップイン

Intel

📦 1152-BBGA (FF1152)

Stratix II GX · 90,960 · 90,960 · Up to 20 multi-gigabit transceivers at 6.375 Gbps · 4.006 ns · 622.08 MHz · 90 nm CMOS

✓ 在庫あり

$1320 / 個

データシートを見る →

ℹ️ 1 異なるパッケージの部品は非表示 — パッケージが異なるとPCBの作り直しが必要で、真のドロップイン代替品ではありません。お問い合わせ異なるパッケージの提案が必要な場合。

EP2SGX90FF1152C3 最大定格＆電気的特性

Series	Stratix II GX
Logic Elements	90960
Embedded Memory	4520448 bits (4.5 Mbit TriMatrix)
LABs/CLBs	4548
Number of I/O	558
動作温度	0C to +85C (commercial, C3)
パッケージ	1152-BBGA, FCBGA (FF1152)
実装タイプ	Surface Mount
Speed Grade	C3
Process Node	90 nm
Multiplier Blocks (18x18)	252
Enhanced PLLs	4
Fast PLLs	8
Global Clock Networks	16
Configuration Method	Enhanced Configuration (EPC) compatible

EP2SGX90FF1152C3 ピン構成

ピン A1	I/O — General purpose user I/O ball
ピン A2	I/O — General purpose user I/O ball
ピン A3	I/O — General purpose user I/O ball
ピン B1	I/O — General purpose user I/O ball
ピン B2	GND — Ground
ピン B3	VCC — Core supply voltage
ピン C1	I/O — General purpose user I/O ball
ピン C2	I/O — General purpose user I/O ball
ピン C3	VCC_PLL — PLL analog supply
ピン D1	GXB_TX0 — Transceiver channel 0 transmit (positive)
ピン D2	GXB_RX0 — Transceiver channel 0 receive (positive)
ピン D3	TCK — JTAG test clock
ピン E1	TMS — JTAG test mode select
ピン E2	TDO — JTAG test data out
ピン E3	TDI — JTAG test data in
ピン F1	nCONFIG — Configuration control (active low)
ピン F2	nSTATUS — Configuration status (active low)
ピン F3	CONF_DONE — Configuration complete
ピン G1	DATA0 — Configuration data bit 0
ピン G2	DCLK — Configuration clock

主な用途

EP2SGX90FF1152C3 の用途: 6 件s: 10 Gbps Line-Card Aggregation, ASIC Prototyping and Emulation, High-Performance DSP (Radar / SDR / Video), PCI Express Endpoint Design, Test & Measurement Backplane Bridging, Industrial High-Speed Imaging.

🌐

10 Gbps Line-Card Aggregation

The EP2SGX90FF1152C3's 12 embedded multi-gigabit transceivers (up to 6.375 Gbps each) aggregate 10 Gigabit Ethernet, XAUI, and CEI-6G serial links in telecom line cards. With 90960 logic elements the fabric absorbs MAC framing, oversubscription logic, and queue management; the 1152-BGA FF1152 package exposes 558 I/O plus all 12 transceiver channels. Pairing it with external PHY/retimer ICs enables full OTN/SONET/SDH mapping. Designers should budget transceiver power separately from core logic - typical channel power at 6.375 Gbps is ~150 mW per channel.

おすすめ

🖥️

ASIC Prototyping and Emulation

The EP2SGX90FF1152C3 with 90960 logic elements and 4.5 Mbit embedded TriMatrix memory serves as a mid-density ASIC prototyping target. Quartus II compiles synthesized ASIC RTL directly to the Stratix II GX architecture, preserving timing closure parity at the C3 commercial speed grade. The 16 global clock networks support multi-clock-domain ASIC designs and the 252 18x18 multipliers cover DSP blocks without losing cycle accuracy. The FF1152 package is large enough to route out hundreds of probe signals for logic-analyzer debugging.

おすすめ

EP2S90F1508C5 · Intel EP2S130GF40C3 (Higher-density 130K-LE variant for full SoC emulation)

✈️

High-Performance DSP (Radar / SDR / Video)

The EP2SGX90FF1152C3's 252 dedicated 18x18 multipliers implement 504 GMACS at 250 MHz, sufficient for radar pulse compression, FFT-based software-defined radio, and HD video processing pipelines. The 4.5 Mbit TriMatrix memory accommodates complex twiddle-factor tables and intermediate FFT buffers without external SRAM. At C3 speed grade the fabric sustains >250 MHz core clock, enabling real-time baseband processing at 100 MSPS. The 1152-BGA FF1152 package enables the I/O fan-out needed for parallel ADC/DAC interfacing with LVDS source-synchronous I/O.

おすすめ

EP2SGX60FF1152 · Altera EP2S90F1020C5 · Intel

🖥️

PCI Express Endpoint Design

The EP2SGX90FF1152C3 supports x1/x4/x8 PCI Express endpoints via its integrated hard PCIe hard IP, eliminating soft-IP timing closure risk. Combined with the 12 multi-gigabit transceivers, the device can simultaneously run PCIe plus multiple Aurora or Serial RapidIO channels for system-interconnect bridging. The 4 enhanced PLLs generate the 100 MHz reference clock plus channel-rate clocks, and the 558 I/O can fan out to local DDR2/QDR-II memory controllers. Quartus II IP Compiler generates the PCIe hard IP wrapper automatically.

おすすめ

EP2SGX90EF1152C3N · Intel EP2SGX30DF780C5 · Intel

🔧

Test & Measurement Backplane Bridging

The EP2SGX90FF1152C3 bridges legacy parallel test backplanes (LVDS, TTL) to modern serial test instruments via its 558 I/O plus 12 transceivers. The 16 global clock networks and 4 enhanced PLLs allow multiple independent timing domains across the bridge, while the 4.5 Mbit memory absorbs burst-mode ADC samples. The FF1152 BGA exposes enough I/O to drive 32+ parallel LVDS channels and the transceivers can drive 6 Gbps links to PXI Express or LXI instrument chassis.

おすすめ

EP2S60F672C5 · Intel EP2SGX60CF780C7 · Altera

🏭

Industrial High-Speed Imaging

The EP2SGX90FF1152C3's combination of 558 I/O, 4.5 Mbit buffer memory, and 252 18x18 multipliers suits multi-camera industrial imaging systems that perform real-time Bayer demosaicing, edge detection, and JPEG/MJPEG compression in the FPGA. The 1152-BGA FF1152 package supports MIPI CSI-2 via soft IP plus LVDS sensor interfacing. C3 commercial temperature (0-85C) covers most factory environments and the I4 industrial-grade alternatives extend to -40C for outdoor machine-vision applications.

おすすめ

EP2SGX90EF1152I4 · Altera EP2SGX30DF780I4N · Intel

おすすめ製品の概要

EP2SGX90EF1152C3 Intel 使用用途: 10 Gbps Line-Card Aggregation EP2S60F1020C3 Altera 使用用途: 10 Gbps Line-Card Aggregation EP2S90F1508C5 Intel 使用用途: ASIC Prototyping and Emulation EP2S130GF40C3 Higher-density 130K-LE variant for full SoC emulation 使用用途: ASIC Prototyping and Emulation EP2SGX60FF1152 Altera 使用用途: High-Performance DSP (Radar / SDR / Video) EP2S90F1020C5 Intel 使用用途: High-Performance DSP (Radar / SDR / Video) EP2SGX90EF1152C3N Intel 使用用途: PCI Express Endpoint Design EP2SGX30DF780C5 Intel 使用用途: PCI Express Endpoint Design EP2S60F672C5 Intel 使用用途: Test & Measurement Backplane Bridging EP2SGX60CF780C7 Altera 使用用途: Test & Measurement Backplane Bridging EP2SGX90EF1152I4 Altera 使用用途: Industrial High-Speed Imaging EP2SGX30DF780I4N Intel 使用用途: Industrial High-Speed Imaging

What is the EP2SGX90FF1152C3?

The EP2SGX90FF1152C3 is an Altera Stratix II GX field-programmable gate array with 90960 logic elements, 4.5 Mbit embedded memory, 4 enhanced PLLs, and 558 user I/O pins, housed in a 1152-ball fine-pitch BGA (FF1152) package at the C3 commercial speed grade. It is part of the high-density transceiver-equipped Stratix II GX family targeting multi-gigabit serial interconnect.

How much logic does the EP2SGX90FF1152C3 contain?

The EP2SGX90FF1152C3 contains 90960 logic elements organized in 4548 LABs/ALMs, alongside 4,520,448 bits (4.5 Mbit) of TriMatrix on-chip memory. The device also provides 252 dedicated 18x18 hardware multipliers for DSP acceleration. According to Altera's Stratix II GX datasheet, this density places it in the mid-range of the family.

What package does the EP2SGX90FF1152C3 use?

The 'FF1152' suffix in EP2SGX90FF1152C3 indicates a 1152-ball fine-pitch BGA (flip-chip BGA) package. Altera datasheets designate the 'F' code for fine-line BGA and the numeric suffix for ball count. The package exposes 558 user I/O pins plus dedicated supply, JTAG, configuration, and transceiver balls.

How do I configure the EP2SGX90FF1152C3 at power-up?

The EP2SGX90FF1152C3 supports Altera's Enhanced Configuration (EPC) scheme using a single-chip enhanced configuration device, fast passive parallel (FPP), passive serial (PS), JTAG, or Altera AS mode. The configuration controller and on-chip flash memory interface allow high-speed loading of large bitstreams for high-density designs. The 'C3' speed grade determines configuration clock tolerances.

What is the difference between EP2SGX90FF1152C3 and EP2SGX90EF1152C3N?

Both parts are Stratix II GX 90K LE devices in the 1152-BGA package; the 'E' prefix in EP2SGX90EF1152C3N denotes the Enhanced configuration subset with hard PCI Express and transceiver blocks, while the 'F' prefix on EP2SGX90FF1152C3 indicates a standard enhanced-configuration variant. The 'N' suffix typically denotes lead-free / RoHS-compliant packaging. Functional drop-in compatibility depends on bitstream revision and transceiver usage.

Is EP2SGX90FF1152C3 still in production?

No - the EP2SGX90FF1152C3 is in NRNR (Not Recommended for New Designs) status per Altera/Intel lifecycle policy. Altera announced the Stratix II GX family as NRNR after Stratix IV GX transitioned to mainline. Distributors still carry inventory and authorized resellers offer new-old-stock, but lead times can be lengthy and pricing reflects obsolescence.

Where can I buy the EP2SGX90FF1152C3?

The EP2SGX90FF1152C3 is available through authorized distributors including Censtry, Jotrin, Nantian Electronics, and brokers carrying legacy Altera inventory. Direct purchase from Altera/Intel is no longer possible since the part is NRNR. Pricing as of 2026-09-09 ranges approximately USD 320-450 per unit depending on quantity, packaging, and trace.

What is the price of EP2SGX90FF1152C3?

EP2SGX90FF1152C3 unit pricing as of 2026-09-09 ranges from approximately USD 450 at qty-1 down to USD 320 at qty-250 on the open market, reflecting its NRNR lifecycle status. Pricing varies by distributor, lot date code, country of origin, and the presence of Altera or authorized trace documentation. Always verify trace when purchasing legacy FPGAs.

What is the lead time for EP2SGX90FF1152C3?

Lead time for EP2SGX90FF1152C3 is unpredictable because Altera no longer manufactures it. Distributors typically quote 6-16 weeks depending on remaining stock and supplier channel. For new designs, Intel recommends migrating to the Stratix IV GX, Stratix V, or Cyclone V GX family, which offer pin-compatible footprints in some cases.

Can EP2SGX90FF1152C3 be replaced with EP2SGX90EF1152C3?

Yes, EP2SGX90EF1152C3 is the most direct drop-in replacement for EP2SGX90FF1152C3 - both share the 1152-BGA FF1152 package, identical 90960 logic elements, 4.5 Mbit memory, 558 I/O, and C3 speed grade. The 'E' variant adds Enhanced configuration features including hard PCIe and transceiver blocks. Existing Stratix II GX bitstreams designed for the 'F' variant typically load and run on the 'E' variant with minor Quartus setting adjustments.

Where do I download the EP2SGX90FF1152C3 datasheet PDF?

The EP2SGX90FF1152C3 datasheet PDF is available on Alldatasheet (alldatasheet.com) as the EP2SGX90F family datasheet, on Octopart as the Intel/Altera EP2SGX90EF1152C3 datasheet entry, and historically on the Altera/Intel website under Stratix II GX device documentation. For Quartus II pinout and BSDL files, Altera/Intel's Quartus II Archive contains the legacy device support package.

Where can I find the EP2SGX90FF1152C3 pinout?

The EP2SGX90FF1152C3 1152-ball BGA pinout is published in the Altera Stratix II GX GX Device Handbook, available via Alldatasheet and Altera's legacy documentation archive. The pinout covers 558 user I/O balls, JTAG (TCK/TMS/TDO/TDI), configuration (nCONFIG/nSTATUS/CONF_DONE/DATA), PLL supply pins, transceiver channel balls, and multiple VCC/VCCPGM/GND power balls.

How many transceivers does EP2SGX90FF1152C3 have?

The EP2SGX90FF1152C3 integrates up to 12 multi-gigabit transceivers operating from 600 Mbps to 6.375 Gbps, supporting protocols including PCI Express (x1/x4/x8), Serial RapidIO, XAUI, CEI-6G, and custom serial links. Each transceiver includes built-in pre-emphasis, equalization, and dynamic phase alignment. The exact transceiver count and arrangement depend on package - the FF1152 exposes the full transceiver complement.

Is EP2SGX90FF1152C3 suitable for new designs?

No, the EP2SGX90FF1152C3 is NRNR (Not Recommended for New Designs). For new designs in 2026, Intel recommends the Stratix IV GX, Stratix V, Cyclone V GX, or newer Agilex families. Use the EP2SGX90FF1152C3 only for sustaining legacy products, repairing field-deployed equipment, or finishing in-production designs that require an exact fit.

What is the best Altera equivalent for the EP2SGX90FF1152C3?

The best same-brand same-package Altera equivalent is the EP2SGX90EF1152C3N - identical 1152-BGA package, same 90960 logic elements, same 4.5 Mbit memory, same transceiver complement, with Enhanced configuration and PCI Express hard IP. For new designs needing more headroom, the EP2SGX130GF40 series offers the same BGA platform with 130K logic elements and 40 transceivers at similar package pin count.

エンジニアリング参考データ: EP2SGX90FF1152C3 — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose EP2SGX90FF1152C3 when you have a mid-density Stratix II GX design requiring 90960 LEs, 12 transceivers at 6.375 Gbps, and 558 user I/O in the FF1152 BGA, AND you do not need hard PCI Express blocks. For PCIe endpoint designs, choose the EP2SGX90EF1152C3 (same package, same density, adds hard PCIe). For industrial temperature -40C to +100C, choose the EP2SGX90EF1152I4 (same package, same LE, slower speed grade). For designs that have outgrown the 90K LE density and can accept a larger BGA, the EP2SGX130GF40C3N offers 130K LE plus 20 transceivers in F1508. Avoid the EP2SGX90FF1152C3 for new designs - the part is NRNR; use Stratix V or Agilex families for new starts.

代替品との比較

パラメータ	この製品	EP2SGX90EF1152C3	EP2SGX90EF1152C3N	EP2SGX90EF1152C4	EP2SGX90EF1152I4	EP2SGX130GF40C3N
Package	1152-BBGA (FF1152)	1152-BBGA (FF1152) - same	1152-BBGA (FF1152) - same	1152-BBGA (FF1152) - same	1152-BBGA (FF1152) - same	1508-BBGA (F1508) - different
Brand	Altera	Altera	Altera	Altera	Altera	Altera
Logic Elements	90960	90960	90960	90960	90960	132480 (+44%)
Embedded Memory	4.5 Mbit	4.5 Mbit	4.5 Mbit	4.5 Mbit	4.5 Mbit	6.7 Mbit
Speed Grade	C3 (commercial)	C3	C3	C4 (slower)	I4 (industrial)	C3 (commercial)
Temperature Range	0C to +85C	0C to +85C	0C to +85C	0C to +85C	-40C to +100C	0C to +85C
User I/O	558	558	558	558	558	734
Transceivers	Up to 12 (6.375 Gbps)	Up to 12 (6.375 Gbps)	Up to 12 (6.375 Gbps)	Up to 12 (6.375 Gbps)	Up to 12 (6.375 Gbps)	Up to 20 (6.375 Gbps)
Enhanced Configuration (PCIe hard IP)	No (F variant)	Yes (E variant)	Yes (E variant)	Yes (E variant)	Yes (E variant)	Yes (G variant)

主な差別化要因

Mid-range density with full transceiver complement （vs EP2SGX60FF1152)
Enhanced configuration subset with PCIe hard IP （vs EP2SGX90EF1152C3)
Commercial temperature (0-85C) vs industrial (-40 to +100C) （vs EP2SGX90EF1152I4)
90K LE vs 130K LE density （vs EP2SGX130GF40C3N)

設計ノート

The EP2SGX90FF1152C3 requires multiple supply rails: VCCINT (core, typically 1.2V), VCCIO (I/O banks, 1.5V-3.3V depending on bank standard), VCCA_PLL (PLL analog, 2.5V), VCCD_PLL (PLL digital, 1.2V), VCC_GXB (transceiver analog, 3.3V or 2.5V), and VCCL_GXB (transceiver analog low). Decouple each rail with one 100 uF bulk plus one 0.1 uF plus one 0.01 uF ceramic cap per power pin. Use a star-ground topology with the FF1152 thermal pad bonded to a large uninterrupted ground plane.

Estimated: At full fabric utilization (90960 LEs @ 80% toggle, all 12 transceivers @ 6.375 Gbps PRBS31), the EP2SGX90FF1152C3 dissipates approximately 12-15 W. The FF1152 package theta_JA on a JEDEC 4-layer test board is approximately 4-6 C/W with a thermal via array under the BGA, requiring either a forced-air heatsink or a 6+ layer PCB with copper coin under the die. For quiescent designs under 3 W, no heatsink is needed.

Use a 0.8 mm or 1.0 mm BGA pitch escape pattern with microvia-in-pad on at least the top signal layers. Transceiver traces require 100 ohm differential impedance with continuous reference plane and length-matching within 150 mil for intra-pair and 2.5 mm for inter-pair skew per channel. Differential vias must use antipad clearance to control impedance. Provide at least 8 transceiver ground vias per channel ball cluster. JTAG chain order should be documented in the Quartus pinout file.

Common pitfalls with the EP2SGX90FF1152C3: (1) Do not enable MSEL pins to a configuration mode that does not match the configuration device - the part will appear 'dead'. (2) Do not drive LVDS signals into 3.3V VCCIO banks - LVDS requires VCCIO = 2.5V. (3) Do not leave VCCA_PLL floating even if PLLs are unused - connect to 2.5V via a ferrite bead. (4) Always tie nCONFIG high through a 4.7 k resistor; do not leave it floating. (5) For configuration from flash, verify the enhanced configuration device is the correct density for the bitstream.

コンプライアンス情報

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

鉛フリー

Unknown

ハロゲンフリー

Unknown

紛争鉱物

Unknown

Altera Stratix II GX family was launched in 2004-2007; the EP2SGX90FF1152C3 NRNR status means RoHS/REACH compliance depends on date code. Verify on the part label and Altera/Intel material declaration. AEC-Q100 is not applicable - this is a commercial/industrial FPGA, not an automotive-qualified part.

データ検証日: 2026-09-09 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

出典: Manufacturer Datasheet, Distributor, Distributor, Octopart, Distributor, Distributor, Distributor