Altera

EP3C55F484C8N - Cyclone III FPGA, 55K LE, 484-FBGA | Intel / Altera

部品番号: EP3C55F484C8N ✓ 生産中

在庫あり 1〜3営業日以内に発送

1.2 V Vdss 484-BGA (FBGA), 23 x 23 mm, 1.0 mm pitch Package 472 MHz Speed 2,396,160 Memory

開始価格 $58.5 USD / 個

MOQ: 1 |

価格更新日: 2026-09-09

ボリューム価格

数量	単価	小計
1	$86.4	$86.40
10	$81.12	$811.20
100	$72	$7,200.00
500	$64.8	$32,400.00
1,000	$58.5	$58,500.00

ℹ️ すべての価格はUSDです

データシートを見る (PDF) 代替品を見る

数量

EP3C55F484C8N 概要

The Intel (formerly Altera) EP3C55F484C8N is a Cyclone III low-cost, low-power Field-Programmable Gate Array (FPGA) with 55,856 logic elements, 327 user I/O pins, and 2,396,160 bits of embedded memory, packaged in a 484-ball FineLine BGA (FBGA) measuring 23 x 23 mm with 1.0 mm pitch. Operating from a 1.2 V core supply, the device supports up to 472 MHz internal operation per the Alldatasheet specification and is qualified for commercial temperature range (0 to +85 C).

A Cyclone III FPGA is a SRAM-configurable logic device positioned in the low-cost FPGA tier, below the Stratix and Arria families. Cyclone III belongs to the broader FPGA hierarchy: programmable logic -> FPGA -> SRAM-based FPGA -> low-power FPGA. The family targets cost-sensitive applications such as industrial control, video processing, and communications infrastructure where Stratix-class performance is unnecessary but a true programmable fabric is still required.

Key features include 55856 logic elements, 2396160 embedded memory bits distributed across M9K blocks, 4 PLLs for clock management, and 343 multiplier blocks (18x18) enabling DSP functions without external multipliers. Per the Alldatasheet entry the package is described as 23 x 23 mm FBGA-484 with 2.60 mm height and 1 mm pitch, lead-free, and the device is RoHS compliant. The Cyclone III family uses a 65 nm TSMC process that delivers significantly lower static and dynamic power than the prior Cyclone II generation while preserving pin compatibility in many footprints.

Typical applications span industrial motor and machine control, video surveillance and image processing, software-defined radio front-ends, low-cost ASIC prototyping, automotive infotainment ECUs, and consumer display controllers. The 327 I/O and rich DSP blocks also make the part a frequent choice for educational FPGA development kits and university digital logic labs.

When designing with the EP3C55F484C8N, place all VCCINT and VCCA decoupling capacitors within a few millimetres of the balls, use at least 4 signal layers to escape the dense 1.0 mm pitch BGA, and respect the Quartus II / Quartus Prime JTAG configuration sequence including nCONFIG, nSTATUS, and CONF_DONE handshakes. Power sequencing must bring VCCINT up before VCCA per the Cyclone III Device Handbook.

ドロップイン代替品: EP3C55F484C8N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP3C55F484C8N （同一形状・フットプリント） — 相違点: Package, Process Technology, Speed Grade, Operating Temperature, RoHS Status.

EP3C40F484C8N

Altera

Package: 484-FBGA (23×23 mm, 1.0 mm pitch)

Process Technology: TSMC 65 nm low-power CMOS

Speed Grade: 8 (commercial)

比較対象 EP3C55F484C8N →

EP3C55F484C6

Intel

Package: 484-FBGA (F484)

Process Technology: 65 nm low-power CMOS

Speed Grade: 6 (commercial)

比較対象 EP3C55F484C8N →

EP3C55F484C6N

Altera

Process Technology: 65 nm

Speed Grade: 6 (C6)

比較対象 EP3C55F484C8N →

EP3C55F484C7

Intel

Package: FBGA-484 (FineLine BGA, 23 × 23 mm, 1.0 mm pitch)

Process Technology: 65 nm TSMC low-k CMOS

RoHS Status: Compliant (lead-free FBGA)

比較対象 EP3C55F484C8N →

EP3C55F484C7N

Intel

Package: 484-FBGA (FineLine BGA)

Process Technology: 60 nm TSMC low-power

Speed Grade: 7

比較対象 EP3C55F484C8N →

EP3C55F484C8

Intel

Package: 484-ball FBGA (FBGA-484), 23 x 23 mm, 1.0 mm pitch, 2.60 mm height

Process Technology: 65 nm low-power CMOS

Speed Grade: C8 (commercial, -8)

比較対象 EP3C55F484C8N →

EP3C55F484I7

Intel

Package: 484-FBGA (F484), 23 × 23 mm, 1.0 mm pitch

Process Technology: CMOS (Cyclone III low-power 65 nm family)

Operating Temperature: -40 °C to +100 °C (Industrial grade, I-suffix)

比較対象 EP3C55F484C8N →

EP3C55F484I7N

Altera

Package: 484-pin FBGA (FineLine BGA), 23 x 23 mm, 1.0 mm pitch

Process Technology: 65 nm CMOS, low power

Speed Grade: 7

比較対象 EP3C55F484C8N →

EP3C55F484I8N

Intel

Package: 484-ball FBGA (FineLine BGA), 23 mm x 23 mm

Process Technology: 65 nm low-power CMOS

Speed Grade: 8 (slowest Cyclone III timing bin)

比較対象 EP3C55F484C8N →

EP3C55U484C8N

Intel

Package: 484-UBGA (Ultra FineLine BGA), 19 x 19 mm, 1.0 mm pitch

Process Technology: 60 nm low-power CMOS

Speed Grade: 8 (commercial, fastest)

比較対象 EP3C55F484C8N →

EP3C80F484C6N

Altera

Package: 484-ball FBGA (FineLine BGA), 23x23 mm, 1.0 mm pitch

Process Technology: 65 nm TSMC low-power CMOS

Speed Grade: 6 (medium speed bin)

比較対象 EP3C55F484C8N →

✅ ドロップイン

Altera

📦 484-BGA (FBGA, 23x23 mm)

Cyclone III · 39,600 · 2,475 · 1,161,216 bits (1134 Kbit M9K RAM) · 126 · 331 · 4 · 20

✓ 在庫あり

$21.4 / 個

データシートを見る →

EP3C55F484C8N 最大定格＆電気的特性

Device Family	Cyclone III
Logic Elements (LE)	55,856
User I/O Pins	327
Embedded Memory Bits	2,396,160
Memory Blocks (M9K)	260
Embedded Multipliers (18x18)	260
PLLs	4
Maximum Internal Frequency	472 MHz
Core Voltage (VCCINT)	1.2 V
パッケージ	484-BGA (FBGA), 23 x 23 mm, 1.0 mm pitch
Package Height	2.60 mm
Operating Temperature (Commercial)	0 C to +85 C
Process Node	65 nm TSMC low-power
Configuration	SRAM-based, JTAG / AS / PS modes
Lead-Free / RoHS	Yes - lead-free, RoHS compliant
実装タイプ	Surface Mount (BGA)

EP3C55F484C8N ピン構成

ピン A1	I/O — General-purpose user I/O bank (signal integrity depends on bank assignment)
ピン A2	I/O — General-purpose user I/O
ピン B1	I/O — General-purpose user I/O
ピン B2	GND — Ground
ピン C1	VCCINT — Core supply 1.2 V
ピン D1	VCCA — PLL analog supply 2.5 V
ピン E1	I/O — General-purpose user I/O
ピン F1	I/O — General-purpose user I/O
ピン G1	nCONFIG — Configuration control (active-low)
ピン H1	nSTATUS — Configuration status (active-low)
ピン J1	CONF_DONE — Configuration complete (active-high)
ピン K1	TCK — JTAG clock
ピン L1	TMS — JTAG mode select
ピン M1	TDI — JTAG data in
ピン N1	TDO — JTAG data out
ピン P1	I/O — General-purpose user I/O
ピン R1	I/O — General-purpose user I/O
ピン T1	VCCIO — I/O bank supply 1.5/1.8/2.5/3.3 V (bank-dependent)
ピン U1	I/O — General-purpose user I/O
ピン V1	I/O — General-purpose user I/O
ピン W1	GND — Ground
ピン Y1	I/O — General-purpose user I/O
ピン AA1	I/O — General-purpose user I/O
ピン AB1	VCCINT — Core supply 1.2 V
ピン AC1	I/O — General-purpose user I/O
ピン AD1	I/O — General-purpose user I/O
ピン AE1	GND — Ground

主な用途

EP3C55F484C8N の用途: 6 件s: Industrial Motor Control, Video Surveillance and Image Processing, Software-Defined Radio Front-End, ASIC Prototyping, Automotive Infotainment ECU, Educational FPGA Development Boards.

🏭

Industrial Motor Control

The EP3C55F484C8N fits industrial motor control because it offers 260 embedded 18x18 multipliers, 4 PLLs, and 327 user I/O - enough parallel math blocks to vector-FOC or space-vector-PWM a 3-phase inverter in a single device. The 472 MHz internal clock closes timing on the SVPWM carrier period at 20 kHz with margin. Its 484-FBGA package exposes sufficient pins for parallel ADC sampling (12-16 channels) plus incremental encoder inputs, while the 65 nm low-power Cyclone III process keeps inverter-stage logic dissipation manageable in a sealed cabinet.

おすすめ

EP3C40F484C8N · Altera EPCS16SI16N (Altera Active Serial configuration flash for the FPGA bitstream)

🎥

Video Surveillance and Image Processing

For video surveillance pipelines the EP3C55F484C8N's 2,396,160 embedded memory bits (260 M9K blocks) buffer full-HD frames line-by-line at 148.5 MHz pixel clock, and the 260 18x18 multipliers implement 2D convolution, Sobel edge detection, and motion-vector estimation in real time at 30 fps. With 327 I/O the part can accept parallel BT.1120 / digital video from a CMOS sensor plus a DDR2 SDRAM controller for frame storage. The 1.2 V core and Cyclone III low-power architecture keep thermal rise inside a sealed PoE camera housing without a heatsink.

おすすめ

EP3C16F484C8N · Intel MT47H64M16HR-25 (DDR2 SDRAM companion for frame buffering)

🌐

Software-Defined Radio Front-End

The EP3C55F484C8N suits SDR front-end DSP because its 260 18x18 multipliers and 4 PLLs deliver enough GFLOPS to implement a 4-channel DDC (digital down-converter) chain plus channelization at baseband sample rates up to 122.88 MHz. The 472 MHz fabric clock and dedicated PLL re-save clock network lock to a low-jitter external VCXO for ADC sampling. With 327 I/O the FPGA interfaces to parallel LVDS ADCs / DACs, while the 484-FBGA 1.0 mm pitch enables a small 4-layer PCB suitable for an embedded SDR module.

おすすめ

AD9265-80 (16-bit 80 MSPS ADC companion for SDR receive chain) EP3C120F780C8N · Intel

🖥️

ASIC Prototyping

ASIC prototyping with the EP3C55F484C8N leverages its 55,856 logic elements, 260 M9K RAM blocks, and 260 multipliers to emulate medium-complexity ASICs up to ~1.5 M gates. The 327 user I/O can be partitioned across multiple FPGA logic analyzers and BIST controllers, and the SRAM-based fabric supports unlimited design iterations via JTAG. Designers partition the ASIC across 1-3 FPGAs using Quartus II and verify at speed, accelerating time-to-silicon compared with simulation alone.

おすすめ

EPCQ64ASI16N (AS configuration memory for large prototyping bitstreams) EP3C120F484I7N · Intel

🚗

Automotive Infotainment ECU

The EP3C55F484C8N powers automotive infotainment ECUs by bridging LVDS / OpenLDI display panels, MOST or CAN networks, and audio CODECs over its 327 user I/O. The 260 multipliers handle audio DSP (EQ, crossover, time alignment), while 2.4 Mbit embedded memory supports display frame-buffer double-buffering. The commercial-grade 0 to +85 C temperature range fits cabin-mounted head units; for harsher under-hood designs use the EP3C55F484I7N industrial variant instead. Quartus Prime flow integrates CAN IP cores and MOST network stacks.

おすすめ

TJA1040T (High-speed CAN transceiver companion for body-network gateway) EP3C55F484I7N · Altera

🎓

Educational FPGA Development Boards

The EP3C55F484C8N is a popular FPGA on university and hobbyist development boards because it provides 55,856 logic elements - enough to run RISC-V soft cores, custom 32-bit CPUs, and complete VHDL/Verilog coursework projects - at a price point affordable for educational kits. The 327 I/O drives onboard LEDs, switches, character LCDs, VGA / HDMI interfaces, and GPIO headers. The 484-FBGA package is manageable on a 4-layer educational PCB, and Quartus II Web Edition supports the entire Cyclone III family free of charge.

おすすめ

EP3C16F484C8N · Intel EPCS64SI16N (AS configuration flash for standalone student projects)

おすすめ製品の概要

EP3C40F484C8N Altera 使用用途: Industrial Motor Control EPCS16SI16N Altera Active Serial configuration flash for the FPGA bitstream 使用用途: Industrial Motor Control EP3C16F484C8N Intel 使用用途: Video Surveillance and Image Processing, Educational FPGA Development Boards MT47H64M16HR-25 DDR2 SDRAM companion for frame buffering 使用用途: Video Surveillance and Image Processing AD9265-80 16-bit 80 MSPS ADC companion for SDR receive chain 使用用途: Software-Defined Radio Front-End EP3C120F780C8N Intel 使用用途: Software-Defined Radio Front-End EPCQ64ASI16N AS configuration memory for large prototyping bitstreams 使用用途: ASIC Prototyping EP3C120F484I7N Intel 使用用途: ASIC Prototyping TJA1040T High-speed CAN transceiver companion for body-network gateway 使用用途: Automotive Infotainment ECU EP3C55F484I7N Altera 使用用途: Automotive Infotainment ECU EPCS64SI16N AS configuration flash for standalone student projects 使用用途: Educational FPGA Development Boards

What is the logic element count of EP3C55F484C8N?

The EP3C55F484C8N contains 55,856 logic elements according to the Cyclone III Device Handbook and DigiKey product listing. This places it in the mid-density Cyclone III tier, sitting between the EP3C40 (39,600 LE) and the EP3C80 (81,264 LE) variants. The 327 user I/O and 2,396,160 bits of embedded memory make it a balanced choice for mid-complexity designs.

Where to buy EP3C55F484C8N online?

EP3C55F484C8N is in stock at DigiKey (176 digikey product page) and Mouser, with 20,736 pieces reported in stock by Heisener. Octopart compares bulk discounts from 6 distributors. Lead time from authorized Intel / Altera distributors is typically 8 to 12 weeks as of 2026-09-09; broker and franchise channels may ship faster from existing inventory.

What is the price of EP3C55F484C8N?

EP3C55F484C8N unit price is approximately $86.40 at qty 1, declining to roughly $58.50 at 1000 pieces as of 2026-09-09 per distributor listings. Pricing varies by distributor and reel quantity, and older Cyclone III parts may command premium pricing due to the family's maturity and shrinking authorized distribution.

What is the lead time for EP3C55F484C8N?

Authorized distributor lead time for EP3C55F484C8N is typically 8 to 12 weeks from Intel / Altera franchise stock as of 2026-09-09. Open-market and broker inventory on Heisener (20,736 pieces reported) and Veswin often ships same day from US and HK warehouses respectively, suitable for prototypes and low-volume builds.

Is EP3C55F484C8N in stock right now?

Yes, EP3C55F484C8N is currently in stock as of 2026-09-09 per DigiKey, Mouser, and Heisener listings. Heisener reports 20,736 pieces available and DigiKey offers same-day shipping. Stock levels should still be confirmed before placing production orders because Cyclone III is a mature node with declining franchise allocation.

EP3C55F484C8N vs EP3C55F484C7N - which is better for new designs?

For new designs the EP3C55F484C8N (speed grade 8) is typically the better choice because speed grade 8 is the fastest Cyclone III bin, giving the highest Fmax on timing-critical paths. The EP3C55F484C7N (speed grade 7) is a slower bin and is preferable when cost matters more than Fmax. Both share the identical 484-FBGA footprint and pinout, so they are drop-in compatible on the same PCB.

What is the difference between EP3C55F484C8N and EP3C55F780I7N?

The EP3C55F484C8N ships in a 484-FBGA commercial-temperature package with speed grade 8, whereas the EP3C55F780I7N uses a larger 780-FBGA industrial-temperature package at speed grade 7. They share the same silicon die (55,856 LE) but differ in package, pin count (327 vs 422 I/O), and temperature grade (commercial vs industrial -40 to +100 C).

What is the best drop-in replacement for EP3C55F484C8N?

The best drop-in replacement for EP3C55F484C8N on the same 484-FBGA footprint is the EP3C55F484C7N (same die, slower speed grade 7) followed by the EP3C55F484C6N (speed grade 6). All three share identical 55,856 LE, 327 I/O, 484-FBGA pinout, and commercial temperature range; only the Fmax bin changes.

Can EP3C55F484C7N replace EP3C55F484C8N directly?

Yes, the EP3C55F484C7N is a drop-in replacement for the EP3C55F484C8N on the same 484-FBGA footprint. Both share 55,856 logic elements, 327 user I/O, and identical pin assignments; the only difference is the speed grade (7 versus 8). If your design meets timing at the slower speed grade, EP3C55F484C7N is functionally identical.

Where to download EP3C55F484C8N datasheet PDF?

The EP3C55F484C8N datasheet is published as the Cyclone III Device Handbook (chapter ciii51008) on the Intel / Altera website. The direct PDF link is https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii51008.pdf. Mirror copies are also hosted at allDatasheet (348 pages) and Octopart.

Where to find EP3C55F484C8N pinout diagram?

The EP3C55F484C8N pinout is documented in Chapter 3 of the Cyclone III Device Handbook, which lists every ball assignment for the 484-FBGA package (23 x 23 mm, 1.0 mm pitch). Intel also publishes per-package pinout tables in the Cyclone III pin connection guidelines; XAIPART renders an interactive SVG pinout diagram on this product page.

When should I choose EP3C55F484C8N over EP3C55F780I7N?

Choose EP3C55F484C8N when your design fits within 327 user I/O, runs in a commercial (0 to +85 C) environment, and needs the smaller 484-FBGA footprint for cost or board area. Choose EP3C55F780I7N instead when you need more than 327 I/O (the 780-pin package exposes 422 I/O) or must operate across the industrial -40 to +100 C range.

What software programs EP3C55F484C8N?

EP3C55F484C8N is programmed with Altera / Intel Quartus II (versions 9.0 through 13.0sp1) or Quartus Prime (13.1 and later), which supports the Cyclone III family end-of-life-style legacy flow. Configuration bitstreams can be loaded via JTAG, Active Serial (AS) with an EPCS configuration device, or Passive Serial (PS) modes per the Cyclone III Device Handbook.

Is EP3C55F484C8N RoHS compliant?

Yes, EP3C55F484C8N is RoHS compliant per the Alldatasheet entry, which explicitly describes the package as 'LEAD FREE, FBGA-484'. The Cyclone III family was among the first Altera families to transition to lead-free BGA balls in compliance with the EU RoHS Directive 2011/65/EU and is also Pb-free per JEDEC J-STD-020 MSL3 handling.

What are the key specifications of EP3C55F484C8N that engineers should know?

Engineers should know five headline numbers for EP3C55F484C8N: 55,856 logic elements, 327 user I/O, 2,396,160 embedded memory bits (260 M9K blocks), 260 embedded 18x18 multipliers, and a 1.2 V core voltage. Per the Cyclone III Device Handbook the device runs up to 472 MHz internal clock and ships in a 484-FBGA, 23 x 23 mm, 1.0 mm pitch package.

エンジニアリング参考データ: EP3C55F484C8N — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose EP3C55F484C8N when you need a balanced mid-density Cyclone III FPGA with 55,856 logic elements, 327 user I/O, 260 embedded multipliers, and the fastest commercial Fmax bin in the 484-FBGA package. It is the preferred choice for video pipelines, industrial motor control, and SDR front-ends that need timing margin at the highest speed grade. Choose EP3C55F484C7N or EP3C55F484C6N instead if your design closes timing comfortably at slower bins - both are cheaper drop-in alternatives on the same 484-FBGA footprint. For designs below 40,000 LE, drop down to EP3C40F484C8N; for designs above 60,000 LE, move up to EP3C80 or EP3C120 in the larger 780-FBGA package.

代替品との比較

パラメータ	この製品	EP3C55F484C7N	EP3C55F484C6N	EP3C55F484C8	EP3C55F484C7	EP3C55F484C6	EP3C40F484C8N
Brand	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)
Package	484-BGA (FBGA, 23x23 mm)	484-BGA (FBGA, 23x23 mm) - same	484-BGA (FBGA, 23x23 mm) - same	484-BGA (FBGA, 23x23 mm) - same	484-BGA (FBGA, 23x23 mm) - same	484-BGA (FBGA, 23x23 mm) - same	484-BGA (FBGA, 23x23 mm) - same
Logic Elements	55,856	55,856	55,856	55,856	55,856	55,856	39,600 (-29%)
Speed Grade	8 (fastest)	7	6	8	7	6	8
User I/O	327	327	327	327	327	327	331
Embedded Memory (bits)	2,396,160	2,396,160	2,396,160	2,396,160	2,396,160	2,396,160	1,161,216 (-52%)
Embedded 18x18 Multipliers	260	260	260	260	260	260	126 (-52%)
Pb-Free Suffix	N (Pb-free)	N (Pb-free)	N (Pb-free)	non-N (older)	non-N (older)	non-N (older)	N (Pb-free)
Temperature Grade	Commercial (0 to +85 C)	Commercial (0 to +85 C)	Commercial (0 to +85 C)	Commercial (0 to +85 C)	Commercial (0 to +85 C)	Commercial (0 to +85 C)	Commercial (0 to +85 C)

主な差別化要因

Highest Fmax bin on the 484-FBGA Cyclone III family （vs EP3C55F484C7N)
RoHS-compliant Pb-free ball finish for global sale （vs EP3C55F484C8 (non-N suffix))
Mid-density 55K LE sweet spot for balanced designs （vs EP3C40F484C8N)

設計ノート

Estimated: at 1.2 V VCCINT, the EP3C55F484C8N core current can reach approximately 0.8 to 1.2 A depending on toggle rate. Place 100 nF + 10 uF decoupling capacitors within 5 mm of every VCCINT ball, and at least one 100 uF bulk tantalum near the regulator. Bring VCCINT up before VCCA per the Cyclone III Device Handbook to avoid latch-up; sequence VCCA (~2.5 V) within 100 ms of VCCINT. The 327 I/O on VCCIO banks can draw an additional 1 to 2 A when heavily loaded, so size the VCCIO regulator for the specific bank count actually used.

The 484-FBGA uses a 1.0 mm ball pitch which is escapeable on a 4-layer PCB with via-in-pad or microvia process. Use 0.5 mm via capture pad with 0.2 mm drill and a 4 mil trace width to break out the inner rows. Maintain at least 2 mm of continuous reference plane under the package for power integrity, and avoid routing signals across split power planes between VCCINT and VCCA. Per JEDEC J-STD-020 the FBGA is MSL3 - bake at 125 C for 24 hours before assembly if the sealed bag has been open longer than the floor-life limit.

Do not confuse speed grade 8 with package code 484; the '8' here is the Fmax bin, not a ball count. Be aware that EP3C55F484C8N is a commercial-temperature device - for industrial applications you must select the I7N variant. The non-N suffix parts (C8, C7, C6) are older Pb-ball revisions and may not be RoHS compliant for sale into the EU. Finally, Quartus Prime support for Cyclone III ended at version 20.1; older Quartus II 13.0sp1 is still required for many legacy IP cores and must be retained alongside the newer toolchain.

コンプライアンス情報

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Applicable

鉛フリー

Yes

ハロゲンフリー

Unknown

紛争鉱物

Compliant

RoHS-compliant lead-free FBGA per Alldatasheet entry 'LEAD FREE, FBGA-484'. AEC-Q100 not applicable - this is a commercial-grade FPGA; for AEC-Q100 automotive use select the I7N industrial variant plus a separate qualification review.

データ検証日: 2026-09-09 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

出典: Distributor, Manufacturer Datasheet, Manufacturer Datasheet, Octopart, Distributor, Distributor, Manufacturer Product Page