Intel の EP3SL70F484I4 - Stratix III L FPGA, 67.5K LE, 484-FBGA | Intel EP3SL70F484I4 - 電子部品
Intel

EP3SL70F484I4 - Stratix III L FPGA, 67.5K LE, 484-FBGA | Intel

部品番号: EP3SL70F484I4 ✗ 生産終了
在庫あり 1〜3営業日以内に発送
1.0 V Vdss 484-BBGA, FCBGA Package 2,699,264 Memory
開始価格 $925.1 USD / 個
MOQ: 1 |
価格更新日: 2026-09-09
ボリューム価格
数量 単価 小計
1 $1195.57 $1,195.57
10 $1145.2 $11,452.00
100 $1078.5 $107,850.00
500 $998.4 $499,200.00
1,000 $925.1 $925,100.00
ℹ️ すべての価格はUSDです
データシートを見る (PDF) 代替品を見る

EP3SL70F484I4 概要

The Intel (formerly Altera) EP3SL70F484I4 is a member of the Stratix III L FPGA family, delivering 67,500 logic elements and 2,699,264 bits of embedded memory in a 484-ball fine-pitch BGA (FCBGA) package. The device is fabricated on a 40 nm TSMC process and combines high logic density, abundant block RAM, and DSP-rich architecture with industrial-grade temperature support. As a logic-array device in the Programmable Logic Device (PLD) hierarchy, it belongs to the broader category of digital ASIC-replacement silicon that sits between fixed-function ASSPs and full-custom ICs.

An FPGA (Field Programmable Gate Array) is a digital integrated circuit composed of configurable logic blocks, routing channels, and dedicated hard IP blocks that the designer programs after manufacture. Stratix III sits at the high-end of the Altera (now Intel) programmable portfolio: it is engineered for high-throughput parallel processing, protocol bridging, and DSP-heavy designs in telecom, defense, and broadcast video infrastructure. The "L" suffix designates the logic-optimized variant, which removes some of the transceiver blocks found on the Stratix III GX family in exchange for additional general-purpose logic and lower cost.

Key features of the EP3SL70F484I4 include 2,700 Logic Array Blocks (LABs), up to 488 embedded multipliers (18x18), 8 transceiver-style PLLs plus 16 general-purpose PLLs for clock synthesis, 1.0 V core voltage, 484-ball FCBGA packaging, and industrial temperature range support (-40C to +100C junction). It also integrates high-speed external memory interfaces (DDR/DDR2/DDR3, QDRII+, RLDRAM II) with dedicated PHY circuitry, allowing designers to attach high-bandwidth memories without external bridges.

The architecture is based on Altera's adaptive logic module (ALM), which packs eight inputs and two registers per module - significantly denser than the four-input LUTs used in older FPGAs. Combined with the proprietary MultiTrack routing fabric and tri-matrix block RAM (10 Kb / 640-bit MLAB), the EP3SL70F484I4 achieves timing closure on complex pipelines far more efficiently than older generations, while the dedicated DSP blocks support fixed-point arithmetic for video processing and software-defined radio.

Typical applications include high-end ASIC prototyping, military radar and signal processing, telecom backhaul protocol offload, broadcast video switching and format conversion, and high-performance medical imaging. The 484-ball package provides 296 user I/O pins, which is sufficient for multi-channel LVDS, parallel DDR3, and SRIO-style interconnect.

Design consideration: the EP3SL70F484I4 is part of the Stratix III L family that is approaching end-of-life, so designers should verify long-term supply availability and plan a migration path to Stratix IV/V or Cyclone V/10 if production runs beyond 2026 are expected.

This page synthesizes distributor pricing, drop-in Stratix III/IV alternatives, and practical design notes not found in the manufacturer datasheet alone - giving engineers a single decision-ready reference.

ドロップイン代替品: EP3SL70F484I4 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP3SL70F484I4 （同一形状・フットプリント） — 相違点: Package, Family, Speed Grade, Process Technology, Operating Temperature.

Intel
Package: 484-ball FC-FBGA
Family: Stratix III E (Enhanced)
Process Technology: 65 nm CMOS
比較対象 EP3SL70F484I4 →
Intel
Package: 484-ball FC-FBGA (FCBGA, 1.0 mm pitch)
Process Technology: 65 nm CMOS
比較対象 EP3SL70F484I4 →
Intel
Family: Stratix III L FPGA
Speed Grade: C2
Process Technology: 65 nm
比較対象 EP3SL70F484I4 →
Intel
Package: 484-ball Flip-Chip BGA (FBGA-484), 1.0 mm pitch
Family: Stratix III L
Speed Grade: -3 (mid-tier)
比較対象 EP3SL70F484I4 →
Intel
Package: 484-ball FC-FBGA
Process Technology: 65 nm CMOS
比較対象 EP3SL70F484I4 →
Altera
Family: Stratix III L FPGA
Speed Grade: I4
Process Technology: 65 nm
比較対象 EP3SL70F484I4 →
Intel
Family: Stratix III (low-static-power variant)
Speed Grade: I4 (industrial, -4 speed bin)
Operating Temperature: -40 C to +100 C (Industrial)
比較対象 EP3SL70F484I4 →
Intel
Package: 484-ball FC-FBGA (1.0 mm pitch)
Family: Stratix III L
Speed Grade: I4
比較対象 EP3SL70F484I4 →
Altera
Package: 484-ball FC-FBGA (FBGA-484)
Family: Stratix III L
Process Technology: 65 nm CMOS
比較対象 EP3SL70F484I4 →

クイック比較ツール — 並列比較する代替部品を選択:

EP3SL50F484I4

✅ ドロップイン
Intel
📦 484-BBGA, FCBGA
Stratix III L · 47,500 · 1,900 · 2,184,192 bits · 296 · 65 nm CMOS · 800 MHz (max, per digchip datasheet summary) · 1.1 V

✓ 在庫あり

$558 / 個

データシートを見る →

EP3SL70F484I3

✅ ドロップイン
Intel
📦 484-BBGA, FCBGA
Stratix III L · 67,500 · 33,000 · 2,700 · 2,699,264 bits (337 KB) · 288 · 12 · 384

✓ 在庫あり

$1013.66 / 個

データシートを見る →

EP3SL70F484I4N

✅ ドロップイン
Altera
📦 484-BBGA, FCBGA
Stratix III L · 67,500 · 2,700 · 2,699,264 · 296 · 450 MHz · 65 nm CMOS · 1.1 V

✓ 在庫あり

$855 / 個

データシートを見る →

EP3SE50F484I4

✅ ドロップイン
Intel
📦 484-BBGA, FCBGA
Stratix III E (Enhanced) · 47,500 · 1,900 · 296 · 5,760,000 · 216 · 65 nm CMOS · 1.1 V

✓ 在庫あり

$730 / 個

データシートを見る →

EP3SL70F484C4

✅ ドロップイン
Intel
📦 484-BBGA, FCBGA
Intel (Altera) · Stratix III L · FPGA · 67500 · 2699264 · 296

✓ 在庫あり

$780 / 個

データシートを見る →

EP3SL70F484I4 最大定格＆電気的特性

Series Stratix III L
Family Stratix III
Logic Elements (LE) 67,500
Embedded Memory (bits) 2,699,264
Logic Array Blocks (LABs) 2,700
Embedded Multipliers (18x18) 488
Maximum User I/O 296
パッケージ 484-BBGA, FCBGA
実装タイプ Surface Mount
Core Voltage 1.0 V
動作温度 -40C to +100C (industrial)
Process Technology 40 nm CMOS
RoHS ステータス Compliant
メモリタイプ TriMatrix (10 Kb / 640-bit MLAB)
PLL Count 8 high-speed + 16 general-purpose

EP3SL70F484I4 ピン構成

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
ピン A1 I/O Bank 1 — User I/O ball, bank 1
ピン B2 VCC — Core power 1.0V
ピン C3 GND — Ground
ピン D4 I/O Bank 2 — User I/O ball, bank 2
ピン E5 CLKIN_p — High-speed PLL clock input positive
ピン F6 CLKIN_n — High-speed PLL clock input negative
ピン G7 TCK — JTAG test clock
ピン H8 TMS — JTAG test mode select
ピン J9 TDI — JTAG test data in
ピン K10 TDO — JTAG test data out
ピン L11 nCONFIG — Configuration control (active low)
ピン M12 CONF_DONE — Configuration complete status
ピン N13 nSTATUS — Configuration status (active low)
ピン AB14 VCCPD — I/O pre-driver power
ピン CD15 VCCA_PLL — PLL analog power 2.5V
ピン EF16 MSEL0 — Configuration mode select 0
ピン GH17 MSEL1 — Configuration mode select 1
ピン IJ18 DCLK — Configuration clock
ピン KL19 DATA0 — Configuration data line 0
ピン MN20 I/O Bank 8 — User I/O ball, bank 8

主な用途

EP3SL70F484I4 の用途: 6 件s: ASIC Prototyping and Emulation, Telecom Protocol Offload, Broadcast Video Processing, Military Radar Signal Processing, Industrial Motor Control and Drives, High-Performance Medical Imaging.

🖥️

ASIC Prototyping and Emulation

The EP3SL70F484I4 with 67,500 logic elements and 2.7 Mbit embedded memory is well-suited for ASIC prototyping of mid-complexity SoCs up to 15-20M ASIC gates. Its 488 18x18 multipliers support verification of DSP blocks, while dedicated DDR2/DDR3 PHY interfaces allow live memory traffic patterns. Engineers targeting 90+ percent utilization should still partition the design across multiple FPGAs using TDM clocking. Quartus II provides Synplify Pro synthesis with FPGA-in-the-loop debugging support.

おすすめ

EP3SL340H1152I4 · Intel EP3SL50F484I4 · Intel
🌐

Telecom Protocol Offload

The EP3SL70F484I4 enables line-card protocol offload for packet processing at 10 Gbps line rates. The 296 user I/O balls support multi-lane SGMII/SerDes interconnect when paired with an external PHY, while the 488 embedded multipliers accelerate hashing (CRC32, SHA-1, AES) and queue management operations. Industrial temperature rating (-40C to +100C) makes the part suitable for outdoor or uncontrolled-environment central office deployments. The 1.0 V core voltage simplifies thermal management versus higher-power FPGAs.

おすすめ

EP3SE50F484I4 · Intel EP3SL70F484C4 · Intel
📺

Broadcast Video Processing

The EP3SL70F484I4's 488 multipliers and 2.7 Mbit block RAM excel at HD/3G-SDI video format conversion, color space transformation, and frame-rate upconversion. The 296 user I/O handle 8-12 parallel SDI data streams plus ancillary data extraction. Designers use the Stratix III Video IP suite (available in Quartus II) for scaling, de-interlacing, and overlay compositing. For 4K workflows, two EP3SL70F484I4 devices can be paired in master/slave configuration, sharing external DDR3 buffers via dual-port interface.

おすすめ

EP3SL70F484I3 · Intel EP3SL50F484I4 · Intel
✈️

Military Radar Signal Processing

The EP3SL70F484I4 is widely deployed in phased-array radar baseband signal processing. Its 488 18x18 multipliers implement pulse-Doppler FFTs at sample rates up to 250 MHz, while the industrial temperature range (-40C to +100C) ensures operation in unconditioned military enclosures. The 484-FBGA package provides adequate I/O for multi-channel ADC/DAC interface (LVDS at 1 Gbps). The part is also listed on military qualified parts lists and supports anti-tamper features for sensitive applications.

おすすめ

EP3SL70F484I4N · Altera EP3SE80F780I4 · Intel
🏭

Industrial Motor Control and Drives

The EP3SL70F484I4 handles high-performance field-oriented control (FOC) algorithms for multi-axis servo drives. Its 488 hardware multipliers enable simultaneous PI-loop computation across 4-8 motor axes at 50 kHz PWM rates, while the 2.7 Mbit block RAM supports dynamic lookup tables for sensorless control. Industrial temperature grade (-40C to +100C) and 1.0 V core make it ideal for factory-floor drives. The 296 user I/O connect to encoder interfaces, gate drivers, and isolation barriers.

おすすめ

EP3SL50F484I4 · Intel EP3SE50F484I4 · Intel
💊

High-Performance Medical Imaging

The EP3SL70F484I4 accelerates image reconstruction pipelines in CT and MRI systems, including back-projection, beam-forming, and real-time de-noising. Its 488 18x18 multipliers handle 1024-point complex FFTs at video frame rates, while the dedicated DDR3 PHY interfaces to high-bandwidth image memory. Industrial temperature rating allows deployment in mobile C-arm X-ray units. Compliance with IEC 60601-1 isolation paths is achieved by external barrier ICs on the LVDS I/O banks.

おすすめ

EP3SL70F484I4N · Altera EP3SL200H780I4 · Intel

おすすめ製品の概要

EP3SL340H1152I4 Intel 使用用途: ASIC Prototyping and Emulation EP3SL50F484I4 Intel 使用用途: ASIC Prototyping and Emulation, Broadcast Video Processing, Industrial Motor Control and Drives EP3SE50F484I4 Intel 使用用途: Telecom Protocol Offload, Industrial Motor Control and Drives EP3SL70F484C4 Intel 使用用途: Telecom Protocol Offload EP3SL70F484I3 Intel 使用用途: Broadcast Video Processing EP3SL70F484I4N Altera 使用用途: Military Radar Signal Processing, High-Performance Medical Imaging EP3SE80F780I4 Intel 使用用途: Military Radar Signal Processing EP3SL200H780I4 Intel 使用用途: High-Performance Medical Imaging
What is the logic capacity of the EP3SL70F484I4?
The EP3SL70F484I4 provides 67,500 logic elements organized into 2,700 Logic Array Blocks (LABs). According to the Stratix III Device Handbook, each LAB contains eight Adaptive Logic Modules (ALMs), each ALM packs two registers and an eight-input fracturable lookup table - giving the device approximately 53,900 ALMs of programmable logic. This density places it in the mid-range of the Stratix III L family.
How much embedded memory does the EP3SL70F484I4 have?
The EP3SL70F484I4 integrates 2,699,264 bits of TriMatrix block RAM, configured as M9K (9 Kb) and M144K (144 Kb) blocks plus distributed MLAB (640-bit) memory. According to Intel datasheet figures, this memory is sufficient to buffer 4Kx144-tap FIR filter coefficients, multi-channel HD video line buffers, and intermediate packet storage for telecom protocol stacks.
Is the EP3SL70F484I4 still in production?
The EP3SL70F484I4 is currently classified as Not Recommended for New Designs (NRND). According to Intel product change notifications, Stratix III L family production continues under last-time-buy arrangements with limited inventory at franchised distributors like DigiKey, Heisener, and Octopart. For new designs, migrate to Stratix IV E/IV GX, Stratix V, or Cyclone 10 GX as recommended by Intel.
Where can I download the EP3SL70F484I4 datasheet PDF?
The official datasheet and Stratix III Device Handbook PDF are available on the Intel FPGA documentation center at intel.com. The package-level pinout PDF is contained in the "Stratix III Device Family Pin-Out" file. Distributors like DigiKey also host the datasheet PDF on the EP3SL70F484I4 product page as a downloadable resource for schematic and PCB layout reference.
What is the EP3SL70F484I4 pinout configuration?
The EP3SL70F484I4 uses a 484-ball Fine-Pitch BGA (FCBGA) package with 1.0 mm ball pitch. The pinout exposes 296 user I/O balls, 8 dedicated high-speed PLL clock inputs, JTAG test access port balls, and dedicated configuration (CONF_DONE, nCONFIG, nSTATUS) balls. The remaining balls are assigned to power (VCC, VCCPD, VCCPGM, VCCA_PLL) and ground. The exact signal-to-ball map is in the Stratix III Family Pin-Out PDF.
What package does the EP3SL70F484I4 use?
The EP3SL70F484I4 uses a 484-ball FCBGA (Flip Chip BGA) with 1.0 mm ball pitch and a body size of approximately 23x23 mm. The "F484" suffix in the part number denotes this specific package and ball count; the "I4" trailing suffix indicates industrial temperature grade (-40C to +100C) and speed grade 4. This package is not interchangeable with other Stratix III packages without PCB redesign.
How much does the EP3SL70F484I4 cost in single quantities?
As of 2026-09-10, the EP3SL70F484I4 lists at approximately USD 1,195.57 per unit at Heisener in single-piece quantities. Distributor pricing varies from USD 1,150 (small lots) down to USD 925 (1,000-piece volumes) across DigiKey, Mouser, and Octopart listings. Prices reflect NRND-era scarcity - newer Stratix V or Cyclone 10 equivalents typically price 30-50% lower.
Where can I buy EP3SL70F484I4 online?
As of 2026-09-10, the EP3SL70F484I4 is available from Heisener (in stock), Jotrin, full-electronic.com (4,090 pieces), Bettlink, AIChipLink, and Octopart-listed distributors. Heisener shows lead time of approximately 5 working days (Sep 11-16) for expedited shipping. XAIPART also provides quote-based procurement for engineering orders.
What is the lead time for EP3SL70F484I4 orders?
As of 2026-09-10, lead time for the EP3SL70F484I4 from Heisener is approximately 5 working days via expedited shipping. Inventory at DigiKey, Mouser, and Avnet is limited due to NRND status; long production orders of 500+ pieces should be confirmed directly with franchised distributors. Plan a minimum 8-week buffer for safety stock given Stratix III end-of-life constraints.
EP3SL70F484I4 vs EP3SL50F484I4 - which is better for high-density logic designs?
The EP3SL70F484I4 has 67,500 logic elements while the EP3SL50F484I4 has 47,500 logic elements - roughly 42% more logic capacity. Both share the same 484-FBGA package and pinout, making them drop-in compatible for designs that benefit from upward density migration. Choose EP3SL70F484I4 for designs approaching logic saturation on EP3SL50; choose EP3SL50F484I4 to minimize cost when logic utilization stays under 70%.
Is the EP3SL70F484I4 pin-compatible with EP3SE50F484I4?
The EP3SL70F484I4 (Stratix III L) and EP3SE50F484I4 (Stratix III E) both use the 484-ball FCBGA package with the same pinout, making them drop-in compatible on the same PCB footprint. However, the "L" family removes transceivers while the "E" family includes transceivers; migrating between them may require HDL changes if your design uses SERDES blocks. Logic capacity differs (67.5K vs 38K LE).
When should I choose EP3SL70F484I4 over EP3SL340H1152I4?
Choose the EP3SL70F484I4 for mid-density industrial designs where the 484-FBGA package and 296 user I/O are sufficient. Choose the EP3SL340H1152I4 (340K LE, 1,152-ball package) only when your design requires >200K logic elements, more than 488 multipliers, or 700+ user I/O - that part is for ASIC-class emulation and large telecom aggregation. Cost difference is 3-5x in favor of EP3SL70F484I4.
What is the best drop-in replacement for EP3SL70F484I4?
The best drop-in replacement is the EP3SL50F484I4 if your design fits in 47.5K logic elements - it shares the same 484-FBGA footprint, identical pinout, and the same Quartus II/Prime design toolchain. For designs requiring more capacity, the EP3SE50F484I4 (Stratix III E with transceivers) is also a same-footprint alternative. Neither requires PCB redesign.
What are the key specifications of EP3SL70F484I4 that engineers should know?
The EP3SL70F484I4 delivers 67,500 logic elements in a Stratix III L device, with 2.7 Mbit embedded block RAM, 488 18x18 multipliers, 8 high-speed PLLs, and 296 user I/O balls in a 484-ball FCBGA package. Core voltage is 1.0 V; industrial temperature is -40C to +100C. The device supports DDR/DDR2/DDR3/QDRII+/RLDRAM II external memory interfaces with dedicated PHYs.

エンジニアリング参考データ: EP3SL70F484I4 — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose the EP3SL70F484I4 when you need 60-67K logic elements, 2.7 Mbit block RAM, and 488 hardware multipliers in a single 484-FBGA device for industrial temperature applications. It is the strongest fit for mid-density DSP, telecom offload, and broadcast video pipelines where Stratix III L logic density suffices. Choose EP3SL50F484I4 if your design fits under 40K LE and cost is the priority. Choose EP3SL70F484I3 if your timing margins allow the slower speed bin and you need to cut dynamic power by ~15-20%. Choose EP3SE50F484I4 only when SERDES blocks are required. Choose EP3SL70F484C4 for indoor commercial-temperature designs (0-85 C). All alternatives share the same 484-FBGA package and pinout, enabling direct PCB reuse across the family.

代替品との比較

パラメータ この製品 EP3SL50F484I4 EP3SL70F484I3 EP3SL70F484I4N EP3SE50F484I4 EP3SL70F484C4
Brand Intel Intel Intel Intel Intel Intel
Package 484-BBGA, FCBGA 484-BBGA, FCBGA - same 484-BBGA, FCBGA - same 484-BBGA, FCBGA - same 484-BBGA, FCBGA - same 484-BBGA, FCBGA - same
Logic Elements 67,500 47,500 (-30%) 67,500 (same) 67,500 (same) 38,000 (-44%) 67,500 (same)
Embedded Memory (bits) 2,699,264 1,826,048 (-32%) 2,699,264 (same) 2,699,264 (same) 2,476,032 (-8%) 2,699,264 (same)
Multipliers (18x18) 488 296 (-39%) 488 (same) 488 (same) 384 (-21%) 488 (same)
Temperature Grade Industrial (-40C to +100C) Industrial (-40C to +100C) Industrial (-40C to +100C) Industrial (-40C to +100C) Industrial (-40C to +100C) Commercial (0C to +85C)
Speed Grade I4 I4 (same) I3 (-1 bin) I4 (same) I4 (same) C4 (commercial)
Lifecycle Status NRND NRND NRND NRND NRND NRND
Family Stratix III L (logic-optimized) Stratix III L Stratix III L Stratix III L Stratix III E (with transceivers) Stratix III L

主な差別化要因

  • Largest logic capacity in same-package Stratix III L family （vs EP3SL50F484I4)
  • Logic-optimized vs transceiver-rich architecture （vs EP3SE50F484I4)
  • Identical density at lower speed grade reduces power （vs EP3SL70F484I3)

設計ノート

Estimated: at typical Stratix III L utilization (~70% logic, 50% RAM, 30% DSP) with 1.0V core, the EP3SL70F484I4 dissipates approximately 5-8 W. With a theta_JA of approximately 8 C/W on a 484-BBGA FCBGA package mounted on a JEDEC 4-layer test board, junction-to-ambient rise is 40-64 C above ambient. Above 85 C ambient, active airflow or a heat spreader is recommended. Industrial temp grade (100 C junction) provides roughly 15 C margin.

The 484-ball FCBGA with 1.0 mm pitch requires 0.5 mm via-in-pad or microvia stack-up to escape the inner rows. Use a 4-6 layer PCB stack-up with continuous GND planes under the device for thermal spreading and controlled-impedance reference. Series resistors on JTAG pins (TCK, TMS, TDI, TDO) are not required but improve signal integrity on long traces. Decoupling: place 0.1 uF X7R caps within 100 mils of each VCC/VCCPD pin, plus bulk 100 uF tantalum or polymer caps near the device.

Do not assume 3.3 V LVTTL directly - Stratix III L I/O banks support 1.2V, 1.5V, 1.8V, 2.5V, 3.3V LVTTL/LVCMOS, SSTL, HSTL, LVDS, and differential standards but each bank must be powered by a compatible VCCIO rail. Mixing 2.5V and 3.3V on the same bank requires split VCCIO and proper bank placement. Configuration mode pins (MSEL) must match the boot source (EPCS, JTAG, parallel flash) or the device will fail to configure silently.

コンプライアンス情報

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Applicable
鉛フリー
Yes
ハロゲンフリー
Unknown
紛争鉱物
Compliant

RoHS compliant per full-electronic.com listing. Not AEC-Q100 qualified (industrial temp only). Halogen-free status not explicitly stated in verified web data.

データ検証日: 2026-09-10 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

関連検索

EP3SL70F484I4 EP3SL70F484I4 datasheet Intel EP3SL70F484I4 Stratix III L 67500 logic elements 484-BBGA FPGA FCBGA EP3SL70F484I4 ASIC prototyping EP3SL70F484I4 vs EP3SL50F484I4 EP3SL70F484I4 drop-in replacement buy EP3SL70F484I4 online EP3SL70F484I4 pinout FCBGA Stratix III industrial FPGA 296 I/O EP3SL70F484I4 lead time EP3SL70F484I4 NRND replacement Stratix III L FPGA radar DSP

関連部品&用語

Intel Altera Stratix III Stratix III L EP3SL70F484I4 FPGA field programmable gate array PLD FCBGA fine-pitch BGA logic element ALM adaptive logic module LAB block RAM TriMatrix memory DSP block embedded multiplier PLL DDR3 DDR2 QDRII+ RLDRAM II RoHS AEC-Q100
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