EP610DI-25 - 25ns Classic EPLD, 16 Macrocells | Altera (Intel)
部品番号: EP610DI-25 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
EP610DI-25 概要
A Classic EPLD (Erasable Programmable Logic Device) is a UV-erasable, CMOS-based programmable logic device belonging to the programmable logic device (PLD) family, which sits hierarchically between discrete logic gates (lowest density) and modern FPGAs (highest density) in the logic integration taxonomy: discrete logic -> PLD -> CPLD -> FPGA -> SoC FPGA. EPLDs use a sum-of-products (AND-OR) PLA-style architecture with a non-volatile EPROM cell, allowing designers to implement glue logic and state machines that retain configuration after power removal. The EP610 is one of Altera's foundational Classic EPLD parts that helped establish the PLD market.
Key features include 25 ns pin-to-pin propagation delay, pipelined data rates up to 100 MHz, 16 macrocells with user-configurable D/T/JK flip-flops, 16 I/O pins, 4 dedicated inputs, and EPROM-based non-volatile configuration. The device offers predictable, deterministic timing identical for every logic path, simplifying static timing analysis compared to SRAM-based FPGAs. A single 5 V power supply and a standard JEDEC programming interface simplify design-in.
The EP610DI-25 uses an EPROM-cell CMOS architecture with a programmable AND/OR array. Logic is implemented as sum-of-products expressions with optional registered output via the macrocell flip-flop. This architecture trades flexibility for predictability, making the part well-suited to bus decoding, address decoding, state machines, and custom peripheral interfaces in legacy 5 V systems.
Typical applications include TTL/CMOS logic integration, bus decoding and address mapping in 5 V microprocessor systems, peripheral interface glue logic, state-machine controllers, and legacy industrial control replacement. The ceramic DIP package supports through-hole assembly typical of older industrial, military, and aerospace equipment still in service.
When designing with this part, note that the device is one-time-programmable only via UV erasure (windowed package), so designers must budget an EPROM eraser step into the prototyping workflow. Programming requires a compatible device programmer supporting the Classic EPLD family. Modern 3.3 V systems require level shifters to interface this 5 V part.
This page synthesizes distributor pricing, drop-in replacement MPNs, and design considerations not found in the original 1990s datasheet, enabling accurate sourcing for long-lifecycle equipment support.
ドロップイン代替品: EP610DI-25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP610DI-25 （同一形状・フットプリント） — 相違点: Package, Propagation Delay (tPD), Supply Voltage (VCC), Operating Temperature, Technology.
クイック比較ツール — 並列比較する代替部品を選択:
EP610DC-25
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EP610DM-25
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP610DC-20
✅ ドロップイン✓ 在庫あり
$15.85 / 個
データシートを見る →EP610DC-15
✅ ドロップイン✓ 在庫あり
$7.95 / 個
データシートを見る →EP610DC-10
✅ ドロップイン✓ 在庫あり
$7.95 / 個
データシートを見る →EP610DC-35
✅ ドロップイン✓ 在庫あり
$18.4 / 個
データシートを見る →EP610DI-25 最大定格＆電気的特性
| Part Family | Classic EPLD |
| Macrocells | 16 |
| Propagation Delay (tPD) | 25 ns |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) |
| I/O Pins | 16 (bidirectional) |
| Dedicated Inputs | 4 |
| Total User I/O | 20 |
| Technology | CMOS EPROM (UV-erasable) |
| Supply Voltage (VCC) | 5 V nominal |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| ピン数 | 24 |
| 実装タイプ | Through-Hole (DIP) |
| 動作温度 | Industrial (per "I" suffix) |
| Speed Grade Suffix | 25 = 25 ns |
| Compliance | RoHS status unknown (legacy 1990s part) |
EP610DI-25 ピン構成
| ピン 1 | I/O — Bidirectional I/O pin (macrocell I/O group 1) |
| ピン 2 | I/O — Bidirectional I/O pin (macrocell I/O group 1) |
| ピン 3 | I/O — Bidirectional I/O pin (macrocell I/O group 1) |
| ピン 4 | I/O — Bidirectional I/O pin (macrocell I/O group 1) |
| ピン 5 | I/O — Bidirectional I/O pin (macrocell I/O group 2) |
| ピン 6 | I/O — Bidirectional I/O pin (macrocell I/O group 2) |
| ピン 7 | I/O — Bidirectional I/O pin (macrocell I/O group 2) |
| ピン 8 | I/O — Bidirectional I/O pin (macrocell I/O group 2) |
| ピン 9 | GND — Ground (0 V) |
| ピン 10 | I/O — Bidirectional I/O pin (macrocell I/O group 3) |
| ピン 11 | I/O — Bidirectional I/O pin (macrocell I/O group 3) |
| ピン 12 | I/O — Bidirectional I/O pin (macrocell I/O group 3) |
| ピン 13 | I/O — Bidirectional I/O pin (macrocell I/O group 3) |
| ピン 14 | I/O — Bidirectional I/O pin (macrocell I/O group 4) |
| ピン 15 | I/O — Bidirectional I/O pin (macrocell I/O group 4) |
| ピン 16 | I/O — Bidirectional I/O pin (macrocell I/O group 4) |
| ピン 17 | I/O — Bidirectional I/O pin (macrocell I/O group 4) |
| ピン 18 | IN — Dedicated input pin |
| ピン 19 | IN — Dedicated input pin |
| ピン 20 | IN — Dedicated input pin |
| ピン 21 | IN — Dedicated input pin |
| ピン 22 | OE/PRGM — Output enable / programming control |
| ピン 23 | CLK — Global clock input |
| ピン 24 | VCC — +5 V supply voltage |
主な用途
EP610DI-25 の用途: 7 件s: 5V TTL Bus Decoder, State-Machine Controller, Glue Logic Integration, Legacy Peripheral Interface, Industrial Control Replacement, Custom Peripheral Chip Select Generator, Aerospace and Defense Legacy Avionics.
5V TTL Bus Decoder
The EP610DI-25's 25 ns tPD and 16 macrocells suit 5 V TTL bus decoding in legacy microprocessor systems. Place the part on the address bus to decode memory-mapped peripheral selects; the 25 ns delay fits comfortably within one 8 MHz 8051 memory cycle (~125 ns). The 16 macrocells decode up to 16 independent chip-select outputs from a 20-input AND-OR array. The ceramic DIP-24 package supports through-hole assembly on VME, Multibus, and STD-bus backplanes still deployed in industrial control.
おすすめ
State-Machine Controller
Implement Mealy or Moore state machines with up to 16 states using the EP610DI-25's 16 macrocells, each containing a configurable D/T/JK flip-flop. The 25 ns tPD supports state-machine clock rates up to 40 MHz in registered configurations. Use the dedicated inputs (4) for asynchronous reset and clock, freeing all 16 I/O pins for state outputs and external stimulus. The deterministic AND-OR architecture eliminates the routing-delay variability of SRAM-based FPGAs, simplifying state-machine timing closure.
おすすめ
Glue Logic Integration
Replace 4 to 6 discrete 74LS/74HC TTL packages with a single EP610DI-25, integrating address decoding, chip-select generation, interrupt prioritization, and bus arbitration in one part. The 16 macrocells consume roughly 50 to 100 equivalent gates, sufficient to consolidate typical 4-chip glue-logic islands. The non-volatile EPROM cell means the design powers up operational without external configuration memory, critical for deterministic startup in industrial controllers. The ceramic package supports legacy MIL-STD-883 environments.
おすすめ
Legacy Peripheral Interface
Bridge legacy peripherals (parallel port, GPIB, SCSI, Centronics) to modern microcontrollers using the EP610DI-25's programmable I/O architecture. The 16 bidirectional I/O pins can implement custom handshaking protocols impossible to realize with discrete logic, while the 25 ns timing supports parallel-bus data rates up to approximately 5 MB/s. The 5 V VCC interface is directly compatible with legacy peripheral chips still using TTL signaling levels, eliminating the level shifters needed for modern 3.3 V CPLDs.
おすすめ
Industrial Control Replacement
Sustain manufacturing equipment originally deployed in the 1990s with the EP610DI-25 as a one-to-one replacement for failed Classic EPLDs on existing PCBs. The ceramic DIP-24 package, industrial temperature range, and 5 V supply match the original equipment specifications exactly, avoiding the layout changes and re-qualification costs of migrating to a modern CPLD. The non-volatile EPROM cell retains logic configuration through power cycles, matching the behavior of the original part. Source from authorized legacy distributors (Rochester Electronics, MicrochipUSA) for traceable date codes.
おすすめ
Custom Peripheral Chip Select Generator
Generate up to 16 individual peripheral chip-select signals from a 20-input address and control bus using the EP610DI-25's programmable AND-OR array. The 25 ns tPD is faster than typical 8051, 80186, and 68000 memory cycle times, allowing the EPLD to decode addresses and present chip-selects within a single memory cycle. The macrocell architecture allows each output to be combinational (CS) or registered (with clocked enable), supporting both synchronous and asynchronous peripherals.
おすすめ
Aerospace and Defense Legacy Avionics
Support legacy avionics, military radio, and aerospace test equipment still in operational service with the EP610DI-25, which uses a ceramic sealed DIP-24 package suitable for high-reliability MIL-STD-883 environments. The industrial temperature range and ceramic hermeticity provide the humidity and thermal tolerance required for aerospace applications. The non-volatile EPROM cell eliminates configuration memory failure modes. Source through authorized military-aerospace distributors with full traceability and date-code records.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP610DI-25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP610DC-25 | EP610DM-25 | EP610DC-20 | EP610DC-15 | EP610DC-10 |
|---|---|---|---|---|---|---|
| Package | Ceramic DIP-24 (R-GDIP-T24) | Plastic DIP-24 (R-PDIP-T24) - same footprint | Plastic DIP-24 OTP - same footprint | Plastic DIP-24 - same footprint | Plastic DIP-24 - same footprint | Plastic DIP-24 - same footprint |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | 25 ns | 25 ns | 20 ns (-20%) | 15 ns (-40%) | 10 ns (-60%) |
| I/O Pins | 16 | 16 | 16 | 16 | 16 | 16 |
| Dedicated Inputs | 4 | 4 | 4 | 4 | 4 | 4 |
| Package Material | Ceramic, glass-sealed (windowed) | Plastic | Plastic OTP | Plastic | Plastic | Plastic |
| Temperature Range | Industrial (per "I" suffix) | Commercial (per "C" suffix) | Commercial (per "M") | Commercial (per "C") | Commercial (per "C") | Commercial (per "C") |
| Erasability | UV-erasable (windowed) | UV-erasable | One-time programmable | UV-erasable | UV-erasable | UV-erasable |
主な差別化要因
- Ceramic windowed package supports UV erasure for development reuse （vs EP610DM-25 (plastic OTP DIP-24))
- Industrial temperature range supports harsh-environment deployment （vs EP610DC-25 (plastic commercial DIP-24))
- 25 ns speed grade balances propagation delay and cost （vs EP610DC-15 (15 ns speed grade, plastic DIP-24))
設計ノート
The EP610DI-25 is UV-erasable via the quartz window on the ceramic DIP-24 package. Without the window (DM suffix variants), the part is one-time-programmable. Before programming, ensure the JEDEC file has been verified by functional simulation because once programmed, plastic DIP variants cannot be re-erased. For development cycles, always use the windowed DI variant and a compatible UV eraser (intensity ~12 mW/cm^2, exposure 20-30 minutes).
The EP610DI-25 operates from a single 5 V supply (4.75 V to 5.25 V). Add a 0.1 uF decoupling capacitor as close as practical to VCC pin 24, plus a 10 uF bulk tantalum capacitor on the 5 V rail near the part. The CMOS EPROM architecture draws standby current of approximately 5-15 mA when idle, rising during programming pulses. Modern 3.3 V systems require a 5 V supply rail or level shifters because the part's inputs are not 5 V tolerant on a 3.3 V VCCIO bus.
Although the EP610DI-25 is a low-frequency device, place it away from high-current switching traces to avoid injecting noise into the analog EPROM sensing circuitry. Keep clock and asynchronous reset traces short (< 50 mm) to prevent skew that could cause macrocell flip-flop metastability. Route output enables synchronously when possible to avoid glitches during bus arbitration. The ceramic DIP-24 footprint follows the standard 600-mil DIP pattern with 2.54 mm pin pitch; no special thermal relief is required because the CMOS part dissipates under 500 mW typical.
The 25 ns tPD imposes a maximum combinational logic chain of approximately one XOR-plus-AND layer per 25 ns; complex state-machine decoding must be pipelined across clock cycles. Output rise/fall times are typically 5-8 ns into 50 pF loads, so add 100 ohm series termination if driving long PCB traces (> 50 mm) on address buses. The OE/PRGM pin (pin 22) must be tied high during normal operation to enable outputs; floating this pin causes the outputs to remain in high-Z state and the part will appear non-functional.
コンプライアンス情報
EP610DI-25 is a legacy 1990s Altera Classic EPLD. RoHS, REACH, lead-free, and halogen-free status were not present in the verified web data; the part was designed before RoHS (Directive 2002/95/EC) came into force. Compliance flags set to 'unknown' rather than fabricating values. MIL-STD-883 ceramic variants may be available through authorized military distributors with full traceability.
