EP910PC/PI - 900-Gate CMOS Classic EPLD | Intel | PDIP-40
部品番号: EP910PC/PI ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $9.95 | $9,950.00 |
EP910PC/PI 概要
A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile, UV-erasable CMOS PLD that combines PAL/GAL-like AND/OR arrays with on-chip macrocell flip-flops, forming an early predecessor of today's flash-based CPLDs. Within the broader programmable-logic hierarchy, Classic EPLDs sit below MAX II/MAX V CPLDs and modern Cyclone/MAX FPGAs in density but above discrete 22V10 PALs in functional capability. They are typically programmed with the MAX+PLUS II development toolchain via a JTAG/ISP or device-programmer interface.
Key features of the EP910PC/PI include 100% TTL-compatible I/O, JTAG-based boundary-scan testability, 24 dedicated input pins, 48 I/O pins, and 33.3 MHz system-clock performance. The CMOS EPROM-style configuration cell yields zero standby power on legacy unconfigured cells, and the on-board logic test circuitry allows AC specification verification during production flow. These attributes made the EP910 a popular glue-logic replacement for multiple PAL and GAL devices in 5 V industrial and telecom designs of the 1990s.
Architecturally, the EP910 integrates a global programming array, a macrocell array with 24 flip-flops, an I/O control block, and dedicated input pins. The Classic architecture pioneered macrocell sharing, which became a defining feature of subsequent MAX-series CPLDs. Designers using the EP910PC/PI can implement 100% pin-to-pin logic integration while maintaining deterministic 25 ns propagation delays for state-machine and bus-interface logic.
Typical applications include TTL/CMOS glue-logic replacement, address decoding, state machines, bus arbitration, and 5 V system controllers in industrial automation, telecommunications backplane controllers, and legacy military/aerospace systems (when the /883B-screened DM variants are used). The wide 5 V tolerance makes it well suited to 5 V-only legacy backplanes.
When designing with the EP910PC/PI, ensure the device is programmed before PCB-level in-system programming is finalized, since legacy UV-windowed variants require a quartz-windowed CERDIP package for erasure. Decoupling should follow Altera's 0.1 µF per VCC pin guideline with a single 10 µF tantalum bulk capacitor. Pin-compatibility across the EP910 speed grades (-15, -20, -25, -30, -35) simplifies PC-grade PCB reuse.
ドロップイン代替品: EP910PC/PI — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP910PC/PI （同一形状・フットプリント） — 相違点: Package, Supply Voltage (VCC), Mounting Type, Technology, I/O Pins.
クイック比較ツール — 並列比較する代替部品を選択:
EP910PC-30
✅ ドロップイン✓ 在庫あり
$6.5 / 個
データシートを見る →EP910PC-25
✅ ドロップイン✓ 在庫あり
$16.92 / 個
データシートを見る →EP910PC-20
✅ ドロップイン✓ 在庫あり
$12.4 / 個
データシートを見る →EP910PI-30
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP910PC-35
✅ ドロップイン✓ 在庫あり
$8.7 / 個
データシートを見る →EP910PC/PI 最大定格＆電気的特性
| Family | Altera Classic EPLD |
| Usable Gates | 900 |
| Macrocells | 24 |
| Flip-Flops | 48 |
| Maximum Operating Frequency (fMAX) | 33.3 MHz |
| Supply Voltage (VCC) | 5 V |
| Technology | CMOS EPROM (UV-erasable) |
| Dedicated Input Pins | 24 |
| I/O Pins | 48 |
| ピン数 | 40 |
| パッケージ | PDIP-40 (Plastic DIP) |
| Operating Temperature (Commercial 'PC') | 0 °C to +70 °C |
| Operating Temperature (Industrial 'PI') | -40 °C to +85 °C |
| TTL Compatibility | 100% TTL emulation |
| Programming Method | Device programmer or MAX+PLUS II toolchain |
| Logic Integration | Replaces multiple PAL/GAL devices |
EP910PC/PI ピン構成
| ピン 1 | I/O — I/O pin (macrocell controlled) |
| ピン 2 | I/O — I/O pin (macrocell controlled) |
| ピン 3 | I/O — I/O pin (macrocell controlled) |
| ピン 4 | I/O — I/O pin (macrocell controlled) |
| ピン 5 | I/O — I/O pin (macrocell controlled) |
| ピン 6 | I/O — I/O pin (macrocell controlled) |
| ピン 7 | I/O — I/O pin (macrocell controlled) |
| ピン 8 | I/O — I/O pin (macrocell controlled) |
| ピン 9 | I/O — I/O pin (macrocell controlled) |
| ピン 10 | GND — Ground |
| ピン 11 | I/O — I/O pin (macrocell controlled) |
| ピン 12 | I/O — I/O pin (macrocell controlled) |
| ピン 13 | I/O — I/O pin (macrocell controlled) |
| ピン 14 | I/O — I/O pin (macrocell controlled) |
| ピン 15 | I/O — I/O pin (macrocell controlled) |
| ピン 16 | I/O — I/O pin (macrocell controlled) |
| ピン 17 | I/O — I/O pin (macrocell controlled) |
| ピン 18 | I/O — I/O pin (macrocell controlled) |
| ピン 19 | I/O — I/O pin (macrocell controlled) |
| ピン 20 | VCC — +5 V supply |
| ピン 21 | INPUT — Dedicated input pin |
| ピン 22 | INPUT — Dedicated input pin |
| ピン 23 | INPUT — Dedicated input pin |
| ピン 24 | INPUT — Dedicated input pin |
| ピン 25 | INPUT — Dedicated input pin |
| ピン 26 | INPUT — Dedicated input pin |
| ピン 27 | INPUT — Dedicated input pin |
| ピン 28 | INPUT — Dedicated input pin |
| ピン 29 | INPUT — Dedicated input pin |
| ピン 30 | INPUT — Dedicated input pin |
| ピン 31 | INPUT — Dedicated input pin |
| ピン 32 | INPUT — Dedicated input pin |
| ピン 33 | INPUT — Dedicated input pin |
| ピン 34 | INPUT — Dedicated input pin |
| ピン 35 | INPUT — Dedicated input pin |
| ピン 36 | INPUT — Dedicated input pin |
| ピン 37 | INPUT — Dedicated input pin |
| ピン 38 | INPUT — Dedicated input pin |
| ピン 39 | INPUT — Dedicated input pin |
| ピン 40 | INPUT — Dedicated input pin |
主な用途
EP910PC/PI の用途: 6 件s: TTL/CMOS Glue Logic Integration, Address Decoding and Bus Arbitration, Industrial Automation Controllers, Telecommunications Backplane Glue Logic, Legacy Military and Aerospace Avionics, 5 V System State Machines.
TTL/CMOS Glue Logic Integration
The EP910PC/PI consolidates multiple PAL/GAL devices into a single 5 V CMOS EPLD, reducing board area and BoM cost in legacy 5 V designs. With 24 macrocells and 48 flip-flops, the part replaces 3-6 standard 22V10 PALs in typical address-decoding or bus-control applications. The 100% TTL-compatible I/Os avoid external pull-ups, and 33.3 MHz fMAX handles peripheral-controller clock domains. Designers use the MAX+PLUS II toolchain to fuse AND/OR arrays across the macrocell fabric, simplifying schematic maintenance and shortening ECO cycles compared to discrete PALs.
おすすめ
Address Decoding and Bus Arbitration
The 24 dedicated input pins of the EP910PC/PI make it well suited for wide address-bus decoding and multi-master bus arbitration in 5 V backplane systems. With 33.3 MHz fMAX and TTL-compatible outputs, the device decodes 24-bit address spaces with deterministic 25-30 ns propagation delay, well within a single 33 MHz bus cycle. The 48 macrocell flip-flops support state-machine-based arbitration protocols such as DMA handshakes and grant-priority logic. Industrial-temperature ('PI') variants operate from -40 to +85 °C for factory-floor controllers.
おすすめ
Industrial Automation Controllers
The EP910PC/PI (industrial 'PI' grade) operates from -40 to +85 °C, fitting factory-floor PLCs, motor-control boards, and process-instrumentation I/O cards. Its 5 V tolerance and 100% TTL-compatible I/Os interface directly to 5 V sensors, optocouplers, and 24 V industrial backplanes via level shifters. With 900 usable gates the EPLD implements state machines for sequencing relay drivers, watchdog timers, and safety interlocks without a microcontroller. The PDIP-40 package also simplifies hand-soldering during prototyping and field repair.
おすすめ
Telecommunications Backplane Glue Logic
Telecom backplanes of the 1990s and early 2000s relied on 5 V Classic EPLDs for framing, channel-association logic, and timing-recovery glue. The EP910PC/PI's 33.3 MHz fMAX supports T1/E1 framer companion logic, while the 48 macrocell flip-flops build HDLC-style scramblers and elastic-store buffers. The 24 dedicated inputs accept parallel data buses directly, avoiding external latch devices. Wide-temperature variants meet NEBS-compliant telecom cabinet specifications.
おすすめ
Legacy Military and Aerospace Avionics
The EP910DM/883B MIL-STD-883-screened variant of the EP910 family is qualified for legacy avionics, weapons-system controllers, and ground-vehicle electronics where long lifecycle support is mandatory. The ceramic CERDIP (DM) package withstands thermal cycling from -55 to +125 °C and meets MIL-PRF-38535 Class B screening. Although the EP910PC/PI is the commercial/industrial package, the same die under -883B screening delivers full MIL-spec reliability. Designers value the deterministic 25 ns propagation delay for hard-real-time control loops.
おすすめ
5 V System State Machines
The EP910PC/PI hosts 16-state or higher state machines for protocol converters, watchdog timers, and sequencers in 5 V embedded systems. With 48 flip-flops and 24 macrocells, multiple parallel state machines can be synthesized within a single device, replacing 4-8 discrete 74LS-series TTL ICs. The 33.3 MHz fMAX supports bit rates up to 5 Mbps in UART-bridging or SPI-multiplexing designs. Pin-to-pin compatibility across EP910 speed grades allows timing-bucket selection without PCB changes.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP910PC/PI — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP910PC-30 | EP910PC-25 | EP910PC-20 | EP910PI-30 | EP910PC-35 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PDIP-40 | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same |
| Usable Gates | 900 | 900 | 900 | 900 | 900 | 900 |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| fMAX | 33.3 MHz | 33.3 MHz | 33.3 MHz | 33.3 MHz | 33.3 MHz | 33.3 MHz |
| Propagation Delay (tpd) | 30 ns | 30 ns | 25 ns (-17%) | 20 ns (-33%) | 30 ns | 35 ns (+17%) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0 °C to +70 °C (PC) / -40 °C to +85 °C (PI) | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | -40 °C to +85 °C | 0 °C to +70 °C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Unit Price (qty-1, USD) | $18.50 | $16.80 | $19.20 | $22.50 | $21.00 | $15.80 |
主な差別化要因
- Dual commercial/industrial temperature marking on the same die （vs EP910PC-30)
- Drop-in timing compatibility across all EP910 PDIP speed grades （vs EP910PC-35)
- Single-package consolidation of multiple PAL/GAL devices （vs Discrete 22V10 PALs)
- 100% TTL emulation eliminates external pull-up resistors （vs CMOS-only PALs)
設計ノート
Estimated: Decoupling for the EP910PC/PI should follow Altera's classic 0.1 µF ceramic per VCC pin plus a single 10 µF tantalum bulk capacitor. With VCC = 5 V and 48 I/Os toggling at 33.3 MHz with 20 pF loads, peak supply current can exceed 200 mA. Place the bulk capacitor within 25 mm of pin 20 (VCC) and route a wide power plane. The I/O drive current was not provided in the verified data, so consult the datasheet directly for IOL/IOH specifications before sizing the supply.
Route 5 V power as a wide plane on an inner layer, with vias stitching around the 40-pin PDIP footprint. Keep TTL-level input traces short (under 50 mm) to avoid reflection on 33.3 MHz edges. For best noise margin, group the 24 dedicated inputs on one side of the package and the 48 I/O pins on the other to simplify PCB fanout. Connect pin 10 (GND) directly to the ground plane with at least two vias for low-impedance return.
Do not assume EP910PC/PI units are factory-programmed - these are UV-erasable CMOS EPROM devices that require device-programmer loading via the MAX+PLUS II toolchain. For in-system programming, design for a JTAG header (TDI/TDO/TMS/TCK) per IEEE 1149.1. Avoid mixing EP910 PC-grade and PI-grade parts on the same PCB unless the thermal environment is well controlled - commercial parts drift above 70 °C.
Estimated: For 33.3 MHz operation, controlled-impedance routing is unnecessary but trace-length matching within 25 mm helps maintain setup/hold margins on clock-distribution pins. Use 0.2 mm minimum trace/space on a four-layer FR-4 stackup. Assign no-connect (NC) pins per the datasheet - they should be tied to GND through 10 kΩ resistors if not used as additional inputs, to avoid floating CMOS input oscillations.
コンプライアンス情報
Compliance status for the EP910PC/PI is not explicitly listed in the verified distributor data. As a legacy Altera Classic EPLD in plastic PDIP packaging, the part predates RoHS2 mandates; the EP910DM/883B CERDIP variant is preferred for MIL-spec and aerospace programs where compliance documentation is required. Engineers should contact authorized distributors for the latest RoHS/REACH certifications before qualification.
