EP910PC-30T - 900-Gate Classic EPLD, 30ns, DIP-40 | Intel (Altera)
部品番号: EP910PC-30T ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
EP910PC-30T 概要
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that replaces multiple discrete PAL/GAL devices with a single CMOS IC; in the broader taxonomy it sits between simple PLDs (PAL/GAL) and modern CPLDs/FPGAs as an early high-density, UV-erasable logic family. The Classic family provides densities from 300 to 900 usable gates and propagation delays as low as 10 ns, making it a workhorse for industrial control, glue logic, and bus-interface bridging where modern FPGAs would be over-spec and over-priced.
Key features include 240 product terms across 24 macrocells interconnected by a global programmable interconnect array, 100% TTL-compatible I/O, on-board logic test circuitry for AC verification during production flow, and programming compatibility with the MAX+PLUS II development system. The 'PC' package suffix denotes plastic DIP, while '-30T' indicates the 30 ns speed grade in tube packaging, identical to the commercial EP910PC-30 except for delivery format.
Architecturally the EP910PC-30T uses a PAL-type AND/OR structure with a global bus connecting each macrocell, supported by a 5 V CMOS process that delivers low quiescent power compared to bipolar TTL PLDs. Each macrocell contains an XOR gate, a programmable flip-flop, an output enable, and a feedback path, allowing registered, combinational, and bidirectional I/O configurations within the same device. The Classic family's logic test circuitry allows verification of function and AC specifications during standard production flow.
Typical applications include industrial control glue logic, address decoding and bus interfacing for legacy microprocessors (e.g., 8086, 68000, Z80 systems), state-machine replacement of discrete SSI/MSI logic, custom peripheral controllers in test equipment, and pin-compatible upgrades of older EP310/EP320 designs. It is commonly used to consolidate multiple 16L8/20L8 PALs into a single device, simplifying PCB layout and reducing part count.
When designing with this device, ensure your design tools support the Classic device family (MAX+PLUS II or compatible legacy software). Verify the 30 ns propagation delay meets your timing budget against the slowest clock edge in your system. Plan for end-of-life sourcing: the Classic family is mature and inventory is mostly distributor or aftermarket stock; second-source or upgrade paths should be evaluated for new long-life designs.
This page synthesizes distributor pricing, same-package drop-in alternatives within the EP910 family, and practical design notes not found in the original Altera datasheet, giving engineers a single reference for sourcing and implementing the EP910PC-30T.
ドロップイン代替品: EP910PC-30T — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP910PC-30T （同一形状・フットプリント） — 相違点: Package, Supply Voltage (VCC), Usable Gates, Mounting Type, Technology.
クイック比較ツール — 並列比較する代替部品を選択:
EP910PC-30
✅ ドロップイン✓ 在庫あり
$6.5 / 個
データシートを見る →EP910PC-25
✅ ドロップイン✓ 在庫あり
$16.92 / 個
データシートを見る →EP910PC-20
✅ ドロップイン✓ 在庫あり
$12.4 / 個
データシートを見る →EP910PC-20T
✅ ドロップイン✓ 在庫あり
$8.7 / 個
データシートを見る →EP910PC-15
✅ ドロップイン✓ 在庫あり
$12.8 / 個
データシートを見る →EP910PC-30T 最大定格＆電気的特性
| Family | Altera Classic EPLD |
| Device | EP910 |
| Usable Gates | 900 |
| Macrocells | 24 |
| Product Terms | 240 |
| Dedicated Inputs | 12 |
| I/O Pins | 24 |
| Propagation Delay (tPD) | 30 ns |
| Maximum Clock Frequency (fCNT) | 33.3 MHz |
| Process Technology | CMOS |
| 電源電圧 | 5 V (TTL compatible) |
| パッケージ | PDIP-40 (Plastic DIP) |
| 実装タイプ | Through-Hole |
| 動作温度 | 0C to +70C (commercial) |
| Logic Compatibility | 100% TTL emulation |
| Programming | MAX+PLUS II / UV-erasable |
EP910PC-30T ピン構成
| ピン 1 | I/O — Macrocell I/O (pin 1) |
| ピン 2 | I/O — Macrocell I/O (pin 2) |
| ピン 3 | I/O — Macrocell I/O (pin 3) |
| ピン 4 | I/O — Macrocell I/O (pin 4) |
| ピン 5 | I/O — Macrocell I/O (pin 5) |
| ピン 6 | I/O — Macrocell I/O (pin 6) |
| ピン 7 | I/O — Macrocell I/O (pin 7) |
| ピン 8 | I/O — Macrocell I/O (pin 8) |
| ピン 9 | I/O — Macrocell I/O (pin 9) |
| ピン 10 | I/O — Macrocell I/O (pin 10) |
| ピン 11 | I/O — Macrocell I/O (pin 11) |
| ピン 12 | I/O — Macrocell I/O (pin 12) |
| ピン 13 | IN — Dedicated input (pin 1) |
| ピン 14 | IN — Dedicated input (pin 2) |
| ピン 15 | IN — Dedicated input (pin 3) |
| ピン 16 | IN — Dedicated input (pin 4) |
| ピン 17 | IN — Dedicated input (pin 5) |
| ピン 18 | IN — Dedicated input (pin 6) |
| ピン 19 | IN — Dedicated input (pin 7) |
| ピン 20 | GND — Ground |
| ピン 21 | IN — Dedicated input (pin 8) |
| ピン 22 | IN — Dedicated input (pin 9) |
| ピン 23 | IN — Dedicated input (pin 10) |
| ピン 24 | IN — Dedicated input (pin 11) |
| ピン 25 | IN — Dedicated input (pin 12) |
| ピン 26 | CLK/IN — Clock input or dedicated input |
| ピン 27 | I/O — Macrocell I/O (pin 13) |
| ピン 28 | I/O — Macrocell I/O (pin 14) |
| ピン 29 | I/O — Macrocell I/O (pin 15) |
| ピン 30 | I/O — Macrocell I/O (pin 16) |
| ピン 31 | I/O — Macrocell I/O (pin 17) |
| ピン 32 | I/O — Macrocell I/O (pin 18) |
| ピン 33 | I/O — Macrocell I/O (pin 19) |
| ピン 34 | I/O — Macrocell I/O (pin 20) |
| ピン 35 | I/O — Macrocell I/O (pin 21) |
| ピン 36 | I/O — Macrocell I/O (pin 22) |
| ピン 37 | I/O — Macrocell I/O (pin 23) |
| ピン 38 | I/O — Macrocell I/O (pin 24) |
| ピン 39 | NC — Not connected (per datasheet) |
| ピン 40 | VCC — 5 V supply voltage |
主な用途
EP910PC-30T の用途: 6 件s: Industrial Control Glue Logic, Legacy Microprocessor Bus Interfacing, State-Machine Replacement of Discrete Logic, Address Decoding and Chip-Select Generation, Custom Peripheral Controllers in Test Equipment, Pin-Compatible Upgrade of EP310/EP320 Designs.
Industrial Control Glue Logic
The EP910PC-30T consolidates multiple discrete PAL/GAL devices (e.g., 16L8, 20L8) into a single 24-macrocell chip in factory automation retrofits, reducing PCB part count and assembly cost. Its 30 ns tPD suits state machines and decoders clocked at sub-10 MHz, typical for PLC I/O scan and conveyor control. The PDIP-40 through-hole package survives vibration and thermal cycling common in industrial cabinets. Designers use MAX+PLUS II to integrate address decoding, handshake sequencing, and motor-control interlocks that previously required three to five SSI/MSI packages.
おすすめ
Legacy Microprocessor Bus Interfacing
The EP910PC-30T is widely deployed as a bus-interface bridge between 8086/68000/Z80 microprocessors and modern peripherals in legacy aerospace, military, and medical equipment still in active service. Its 12 dedicated inputs and 24 bidirectional I/O pins cleanly handle 16-bit address decoding plus chip-select generation for memory and I/O banks. The 33.3 MHz fCNT is well above the bus speed of legacy CPUs (8-25 MHz), and the 5 V TTL-compatible I/O eliminates level-shifters when interfacing to vintage peripherals. Drop-in compatibility across speed grades enables straightforward obsolescence management.
おすすめ
State-Machine Replacement of Discrete Logic
The EP910PC-30T replaces 4-8 discrete 74LS/74HC flip-flops, gates, and PALs with a single programmable device implementing custom sequencers in test equipment, instrumentation, and motor controllers. Its 240 product terms comfortably support 20-30 state-transition equations with redundant term allocation, while the 24 macrocells handle both registered outputs (for Q-state feedback) and combinational outputs (for decoded outputs). This consolidation cuts board area by 60-70% and eliminates routing congestion in mixed-signal test instruments.
おすすめ
Address Decoding and Chip-Select Generation
The EP910PC-30T is ideal for memory and I/O address decoding in embedded systems where it generates up to 24 independent chip-select signals from a 16-20 bit address bus. With 24 macrocells and 240 product terms, designers can decode complex memory maps including partial-address overlays, bank-switching, and interrupt acknowledge logic without resorting to cascaded 74LS138 decoders. Its 30 ns tPD adds only modest propagation delay to the chip-select path, well within typical 8/16-bit system timing margins. Through-hole PDIP-40 packaging survives hand-soldering repairs on legacy boards.
おすすめ
Custom Peripheral Controllers in Test Equipment
In test and measurement fixtures, the EP910PC-30T implements custom GPIB/IEEE-488 handshakes, parallel-port bit-banging, and stimulus/response sequencers that don't justify a full microcontroller. Its 100% TTL compatibility interfaces directly to legacy test-bus transceivers, and the programmable I/O direction per macrocell simplifies bidirectional test-pin multiplexing. The 33.3 MHz fCNT handles real-time sampling rates up to several MHz - sufficient for digital-logic-test fixtures and boundary-scan controllers. End-of-life status means new designs should evaluate MAX V or Lattice ispMACH equivalents.
おすすめ
Pin-Compatible Upgrade of EP310/EP320 Designs
The EP910PC-30T serves as a density upgrade for legacy designs originally built around the smaller EP310 (300 gates) or EP320 (600 gates) Classic EPLDs. Its 900 usable gates, 24 macrocells, and 240 product terms provide 3x the logic of the EP310 without any PCB rework when the original design reserved adequate footprint - the EP910 shares the same Classic pinout philosophy in PDIP-40. Designers can thus expand functionality (more registers, wider decoders, additional state-machine states) while preserving the original board layout, an invaluable capability for in-production legacy systems.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP910PC-30T — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP910PC-30 | EP910PC-25 | EP910PC-20 | EP910PC-20T | EP910PC-15 |
|---|---|---|---|---|---|---|
| Package | PDIP-40 | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Propagation Delay (tPD) | 30 ns | 30 ns | 25 ns (faster) | 20 ns (faster) | 20 ns (faster) | 15 ns (fastest) |
| Usable Gates | 900 | 900 | 900 | 900 | 900 | 900 |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Product Terms | 240 | 240 | 240 | 240 | 240 | 240 |
| Max Clock Frequency | 33.3 MHz | 33.3 MHz | 40 MHz | 50 MHz | 50 MHz | 62.5 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Delivery Format | Tube | Tape & Reel / Tray | Tube (default) | Tube (default) | Tube | Tube (default) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Most widely stocked EP910 speed grade in PDIP-40 （vs EP910PC-25 / EP910PC-20 / EP910PC-15)
- Tube-delivery format ideal for low-volume through-hole assembly （vs EP910PC-30 (tape & reel))
- Full Classic EPLD feature set at lowest 2026 market price （vs EP910PC-25)
設計ノート
Do not substitute a slower speed grade (e.g., EP910PC-30T) into a design originally timing-budgeted for a faster grade (e.g., EP910PC-25 or EP910PC-20) without re-running static timing analysis. The 30 ns grade's 17-50% longer tPD will cause setup-time violations in paths that previously had small positive slack. Conversely, a faster grade can always replace a slower grade provided the silicon revision matches; verify lot-traceability when sourcing for medical/aerospace systems.
Use a DIP-40 socket (e.g., Aries 40-pin machined-pin) for prototyping - this allows rapid swap of speed grades and re-programming during design iteration. For production through-hole boards, ensure the EP910PC-30T is oriented with the pin-1 notch matching the silkscreen. Decoupling: place one 0.1 uF ceramic + one 10 uF electrolytic within 5 mm of the VCC pin (40) and GND pin (20); the EP910's high-speed CMOS output switching can inject significant supply noise without proper bypassing.
The EP910PC-30T outputs drive 5 V TTL loads directly; for fan-out above 20 LSTTL loads, buffer with 74LS244 or 74F244. Output edge rates are approximately 3-5 ns (TTL-compatible), so transmission-line effects are negligible on boards under 30 cm with standard 0.65 mm traces, but stripline impedance should be calculated for backplane designs above 50 MHz. The 24 macrocell outputs are individually programmable for registered, combinational, or bidirectional operation, simplifying mixed I/O designs.
コンプライアンス情報
Classic EPLD family pre-dates RoHS directive; PDIP-40 lead-frame is SnPb finish. Not AEC-Q100 qualified (industrial/automotive grade unavailable). For RoHS-compliant rebuilds, use ceramic or modern MAX-series CPLDs.
