EPF8636ALC84-4 - FLEX 8000 FPGA, 504 Cells, 84-PLCC | Intel / Altera
部品番号: EPF8636ALC84-4 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $44.18 | $44.18 |
| 10 | $39.76 | $397.60 |
| 100 | $33.14 | $3,314.00 |
| 500 | $28.62 | $14,310.00 |
| 1,000 | $24.3 | $24,300.00 |
EPF8636ALC84-4 概要
An FPGA (Field-Programmable Gate Array) is a semiconductor device containing programmable logic blocks, interconnects, and I/O cells that the designer configures after manufacture. In the system hierarchy, an FPGA sits between an ASIC (custom silicon) and a CPLD (smaller programmable logic), offering higher density than a CPLD while preserving the in-system reprogrammability that ASICs lack. FLEX 8000 devices are SRAM-based, meaning configuration data must be reloaded on every power-up from an external EPROM, a serial configuration device such as the EPC1, EPC1064, EPC1213, or EPC1441, or from a system controller. This places the FLEX 8000 family in the broader category of programmable logic devices (PLDs) under the larger umbrella of digital logic ICs.
Key features of the EPF8636ALC84-4 include 68 bidirectional I/O pins, 504 logic cells, an 8-element carry chain per LAB for fast arithmetic, multi-volt I/O capability on most packages (the EPF8636A in 84-pin PLCC does NOT support 3.3 V I/O; only 5.0 V I/O is supported), JTAG-based boundary-scan test support via the IEEE 1149.1 interface, and continuous interconnect via FastTrack routing. The -4 speed grade denotes one of the faster FLEX 8000 speed bins. Configuration is volatile, so a boot memory is mandatory.
The FLEX 8000 architecture arranges LABs in rows and columns, with each LAB containing eight 4-input look-up tables (LUTs) plus dedicated carry logic. FastTrack continuous routing uses row and column channels of pass transistors and tri-state buffers to deliver predictable timing across the entire device, regardless of placement. A single embedded array block (EAB) per row provides on-chip RAM/ROM blocks for state machines and lookup tables. Together, these elements deliver the deterministic performance required for glue logic, bus interfacing, and moderate-complexity state machines.
Typical applications include industrial glue logic, legacy PCI bus bridges, parallel peripheral interfaces (Centronics, GPIB), telecommunications control cards, and educational / development platforms where a large, inexpensive 5 V FPGA is required. The 84-pin PLCC package is socket-compatible with several earlier FLEX 8000 derivatives, simplifying board bring-up and rework.
When designing with the EPF8636ALC84-4, ensure a 5.0 V supply rail (the 84-pin PLCC does NOT support 3.3 V I/O). For configuration, choose a serial boot device such as EPC1 or EPC1064, or program a parallel EPROM. Always use the Altera (or third-party) MAX+PLUS II / Quartus toolchain for place-and-route, and observe derating for I/O drive strength above 50 MHz to avoid ground-bounce issues.
This page synthesizes distributor pricing (DigiKey, Mouser, Octopart as of 2026-09-12), same-family Altera drop-in alternatives with different speed grades, and practical design notes not assembled in the original datasheet.
ドロップイン代替品: EPF8636ALC84-4 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPF8636ALC84-4 （同一形状・フットプリント） — 相違点: Configuration Method, Mounting Type, Usable Gates, Package, Operating Temperature.
クイック比較ツール — 並列比較する代替部品を選択:
EPF8636ALC84-3
✅ ドロップイン✓ 在庫あり
$18.75 / 個
データシートを見る →EPF8282ALC84-4
✅ ドロップイン✓ 在庫あり
$9.75 / 個
データシートを見る →EPF8282ALC84-4N
✅ ドロップイン✓ 在庫あり
$23.85 / 個
データシートを見る →EPF8452ALC84-4
✅ ドロップイン✓ 在庫あり
$9.85 / 個
データシートを見る →EPF8452ALC84-3
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EPF8452ALI84-4
✅ ドロップイン✓ 在庫あり
$9.75 / 個
データシートを見る →EPF8282ALC84-3
✅ ドロップイン✓ 在庫あり
$9.85 / 個
データシートを見る →EPF8636ALC84-4 最大定格＆電気的特性
| Family | FLEX 8000 |
| Number of Logic Cells | 504 |
| Number of Logic Array Blocks (LABs) | 63 |
| Maximum Usable Gates | 6,000 |
| Number of User I/O Pins | 68 |
| Maximum Operating Frequency | 125 MHz |
| Process Technology | 0.42 µm CMOS SRAM |
| Supply Voltage (Core) | 5.0 V |
| I/O Voltage (84-pin PLCC) | 5.0 V only (3.3 V I/O NOT supported on this package) |
| Operating Current (typical) | 10 mA |
| パッケージ | 84-Pin PLCC (J-Lead) |
| 実装タイプ | Surface Mount / Socket |
| 動作温度 | 0 °C to +70 °C (Commercial) |
| Speed Grade | -4 |
| Configuration Method | Serial (EPC1/EPC1064/EPC1213/EPC1441) or parallel EPROM |
| Configuration Memory Type | Volatile SRAM (requires boot device) |
| Boundary Scan | IEEE 1149.1 (JTAG) |
| RoHS ステータス | Non-compliant (legacy PLCC, lead-bearing) |
EPF8636ALC84-4 ピン構成
| ピン 1 | I/O — User I/O pin (LAB row/column dependent) |
| ピン 2 | I/O — User I/O pin |
| ピン 3 | I/O — User I/O pin |
| ピン 4 | I/O — User I/O pin |
| ピン 5 | I/O — User I/O pin |
| ピン 6 | I/O — User I/O pin |
| ピン 7 | VCC — Core supply voltage (5.0 V) |
| ピン 8 | I/O — User I/O pin |
| ピン 9 | I/O — User I/O pin |
| ピン 10 | I/O — User I/O pin |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O pin |
| ピン 13 | I/O — User I/O pin |
| ピン 14 | I/O — User I/O pin |
| ピン 15 | TDI — JTAG Test Data In (IEEE 1149.1) |
| ピン 16 | I/O — User I/O pin |
| ピン 17 | TMS — JTAG Test Mode Select |
| ピン 18 | I/O — User I/O pin |
| ピン 19 | TCK — JTAG Test Clock |
| ピン 20 | I/O — User I/O pin |
| ピン 21 | I/O — User I/O pin |
| ピン 22 | I/O — User I/O pin |
| ピン 23 | GND — Ground |
| ピン 24 | I/O — User I/O pin |
| ピン 25 | I/O — User I/O pin |
| ピン 26 | I/O — User I/O pin |
| ピン 27 | I/O — User I/O pin |
| ピン 28 | I/O — User I/O pin |
| ピン 29 | I/O — User I/O pin |
| ピン 30 | I/O — User I/O pin |
| ピン 31 | I/O — User I/O pin |
| ピン 32 | VCC — Core supply voltage (5.0 V) |
| ピン 33 | I/O — User I/O pin |
| ピン 34 | I/O — User I/O pin |
| ピン 35 | I/O — User I/O pin |
| ピン 36 | I/O — User I/O pin |
| ピン 37 | I/O — User I/O pin |
| ピン 38 | nCONFIG — Configuration control (active low) |
| ピン 39 | I/O — User I/O pin |
| ピン 40 | I/O — User I/O pin |
| ピン 41 | I/O — User I/O pin |
| ピン 42 | I/O — User I/O pin |
| ピン 43 | I/O — User I/O pin |
| ピン 44 | GND — Ground |
| ピン 45 | I/O — User I/O pin |
| ピン 46 | I/O — User I/O pin |
| ピン 47 | I/O — User I/O pin |
| ピン 48 | I/O — User I/O pin |
| ピン 49 | I/O — User I/O pin |
| ピン 50 | I/O — User I/O pin |
| ピン 51 | I/O — User I/O pin |
| ピン 52 | I/O — User I/O pin |
| ピン 53 | I/O — User I/O pin |
| ピン 54 | VCC — Core supply voltage (5.0 V) |
| ピン 55 | I/O — User I/O pin |
| ピン 56 | I/O — User I/O pin |
| ピン 57 | I/O — User I/O pin |
| ピン 58 | I/O — User I/O pin |
| ピン 59 | I/O — User I/O pin |
| ピン 60 | I/O — User I/O pin |
| ピン 61 | I/O — User I/O pin |
| ピン 62 | I/O — User I/O pin |
| ピン 63 | I/O — User I/O pin |
| ピン 64 | GND — Ground |
| ピン 65 | I/O — User I/O pin |
| ピン 66 | I/O — User I/O pin |
| ピン 67 | I/O — User I/O pin |
| ピン 68 | DCLK — Configuration clock |
| ピン 69 | I/O — User I/O pin |
| ピン 70 | DATA0 — Configuration data input |
| ピン 71 | nSTATUS — Configuration status (active low) |
| ピン 72 | CONF_DONE — Configuration done (open-drain) |
| ピン 73 | I/O — User I/O pin |
| ピン 74 | I/O — User I/O pin |
| ピン 75 | I/O — User I/O pin |
| ピン 76 | I/O — User I/O pin |
| ピン 77 | I/O — User I/O pin |
| ピン 78 | I/O — User I/O pin |
| ピン 79 | VCC — Core supply voltage (5.0 V) |
| ピン 80 | I/O — User I/O pin |
| ピン 81 | I/O — User I/O pin |
| ピン 82 | I/O — User I/O pin |
| ピン 83 | I/O — User I/O pin |
| ピン 84 | TDO — JTAG Test Data Out |
主な用途
EPF8636ALC84-4 の用途: 7 件s: Industrial Glue Logic Replacement, Legacy PCI Bus Bridge and Interface Controller, Telecommunications Control Card, Parallel Peripheral Interface (Centronics, GPIB, SCSI), Educational FPGA Development Platform, Legacy Industrial Bus Controller (VME, ISA, Multibus), Custom State-Machine Replacement of TTL/CMOS Logic.
Industrial Glue Logic Replacement
The EPF8636ALC84-4 fits legacy industrial glue-logic replacement because it integrates 504 logic cells and 68 I/Os into a single 5 V device, replacing dozens of 74-series TTL gates while preserving the 84-pin PLCC socket footprint common on 1990s-era control boards. Its 125 MHz Fmax in the -4 speed grade easily handles bus arbitration, address decoding, and timing-generator functions at industrial clock rates below 50 MHz. MultiVolt I/O limitations on the 84-pin PLCC mean designs must remain on 5 V rails, matching most legacy industrial backplanes. JTAG boundary-scan support simplifies board-level test in production.
おすすめ
Legacy PCI Bus Bridge and Interface Controller
The EPF8636ALC84-4 is well suited to legacy 33 MHz, 32-bit PCI bridge and interface-controller implementations because its 504 logic cells comfortably absorb the PCI state machine, parity logic, and address-decoder needed for an add-in card, while 68 user I/Os are sufficient to expose a 32-bit PCI bus plus auxiliary peripheral pins. The 5 V PCI signalling standard matches the device's 5 V I/O-only 84-pin PLCC variant without level shifters. The -4 speed grade comfortably closes 33 MHz timing at 30% utilization in MAX+PLUS II. Designers should observe 5 V tolerance and PCI 2.1 add-in card mechanical requirements.
おすすめ
Telecommunications Control Card
In telecommunications control cards such as E1/T1 line-interface controllers, ISDN termination boards, and central-office crosspoint switches, the EPF8636ALC84-4 offers sufficient logic density to implement HDLC framing, timeslot assignment, and alarm logic in a single device. Its 5 V tolerant I/Os interface directly to legacy telecom line-interface ICs (LIUs) without level shifters, while 63 LABs and embedded EABs provide the on-chip RAM required for small elastic buffers and lookup tables. The 0 to 70 °C operating range covers indoor central-office environments. JTAG support simplifies in-system test on populated backplanes.
おすすめ
Parallel Peripheral Interface (Centronics, GPIB, SCSI)
The EPF8636ALC84-4 can be used as the controller for legacy parallel peripheral interfaces such as Centronics parallel ports, IEEE-488 GPIB controller cards, and SCSI-2 host adapters, where 68 user I/Os directly drive the data, handshake, and control lines without external bus transceivers for short-distance applications. The 504 logic cells absorb the state machine, handshaking, and DMA arbitration logic, while the 125 MHz Fmax comfortably handles 8 MHz SCSI and 1 Mbyte/s Centronics throughput. 5 V I/O operation matches classic peripheral bus signalling levels.
おすすめ
Educational FPGA Development Platform
Universities and training labs frequently choose the EPF8636ALC84-4 for introductory digital-design courses because the 84-pin PLCC package is large enough to probe with standard oscilloscope hooks, the 5 V supply matches breadboard-friendly power rails, and the 504-cell capacity supports moderate lab projects such as UARTs, simple CPUs, and VGA controllers. The mature MAX+PLUS II toolchain is freely available and includes example designs, making the device an excellent pedagogical tool. The low cost on the secondary market (around $44 per unit) suits lab budgets when the part is treated as a consumable.
おすすめ
Legacy Industrial Bus Controller (VME, ISA, Multibus)
In VMEbus, ISA, and Multibus-based industrial controllers that remain in service on factory floors, the EPF8636ALC84-4 serves as a bus-master or slave controller implementing address decoding, interrupt handling, and DMA handshaking. The 5 V signalling matches VME and ISA backplane levels directly, and 68 user I/Os can be allocated between data, address, and control buses. With 504 cells the device can host the entire bus-interface state machine plus local peripheral glue. The commercial 0 to 70 °C range suits indoor control cabinets, while JTAG aids in-cabinet programming during commissioning.
おすすめ
Custom State-Machine Replacement of TTL/CMOS Logic
Designers replacing dozens of discrete 74LS/74HC TTL or 4000-series CMOS packages with a single programmable device often choose the EPF8636ALC84-4 because the 504 logic cells and 63 LABs are sufficient to absorb mid-sized state machines, decoders, and timing generators, while 68 I/Os comfortably replace 16 to 20 packages of glue logic. The 5 V I/O-only PLCC variant integrates directly into existing 5 V designs without level shifting. In-system SRAM-based programmability lets engineers iterate designs quickly without rework, and the obsolete status makes remaining stock attractive for one-off legacy repairs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPF8636ALC84-4 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPF8636ALC84-3 | EPF8282ALC84-4 | EPF8452ALC84-4 | EPF8452ALI84-4 |
|---|---|---|---|---|---|
| Brand | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) |
| Package | 84-Pin PLCC (J-Lead) | 84-Pin PLCC (J-Lead) - same | 84-Pin PLCC (J-Lead) - same | 84-Pin PLCC (J-Lead) - same | 84-Pin PLCC (J-Lead) - same |
| Logic Cells | 504 | 504 | 208 | 452 | 452 |
| Number of LABs | 63 | 63 | 26 | 56 | 56 |
| User I/O Pins | 68 | 68 | 68 | 68 | 68 |
| Speed Grade | -4 (fast) | -3 | -4 | -4 | -4 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) | -40 °C to +85 °C (Industrial) |
| Process | 0.42 µm CMOS | 0.42 µm CMOS | 0.42 µm CMOS | 0.42 µm CMOS | 0.42 µm CMOS |
| Configuration Memory | Volatile SRAM | Volatile SRAM | Volatile SRAM | Volatile SRAM | Volatile SRAM |
主な差別化要因
- Highest-density 84-pin PLCC FLEX 8000 device （vs EPF8452ALC84-4)
- Fastest speed grade available in EPF8636A 84-PLCC family （vs EPF8636ALC84-3)
- Mature FLEX 8000 toolchain support with broad reference designs （vs EPF8282ALC84-4)
設計ノート
The EPF8636ALC84-4 requires a stable 5.0 V supply with adequate decoupling. Place a 100 µF bulk tantalum capacitor and 0.1 µF ceramic decoupling caps on every VCC/GND pair within 25 mm of the package. Estimated: at full I/O switching (68 outputs at 20 pF each, 25 MHz), I/O supply current can exceed 100 mA transient - budget 5 V regulator headroom accordingly and use a low-ESR bulk cap. Core current at 10 mA typical is modest; the I/O bank dominates the power budget.
Do not assume 3.3 V I/O capability on the 84-pin PLCC package. The EPF8636A 84-pin variant supports 5.0 V I/O only; driving 3.3 V signals into a 5 V CMOS input is acceptable but 5 V signals into a 3.3 V receiver downstream requires a level shifter. Engineers migrating to this part from a larger FLEX 8000 package (e.g. 144-pin TQFP) often overlook this restriction and damage downstream 3.3 V ASICs.
Route JTAG signals (TCK, TMS, TDI, TDO) with short traces and a 10 kΩ pull-up on TCK/TMS/TDI per the IEEE 1149.1 spec. Place the EPC1 or EPC1064 configuration device within 50 mm of the FLEX 8000 to keep the DCLK and DATA0 traces short - long configuration traces introduce bit errors during boot. Provide a 1 kΩ pull-up on nCONFIG and nSTATUS to allow in-system reprogramming via JTAG or external controller.
The EPF8636ALC84-4 in 84-pin PLCC has a thermal resistance (θJA) on the order of 35-45 °C/W for a socketed part in still air. At typical 10 mA core current and 5 V supply, power dissipation is roughly 50 mW (core) plus I/O switching losses, well within the commercial 0-70 °C range. Estimated junction temperature rise at 0.5 W total dissipation: 17-22 °C above ambient - no heatsink needed for socketed designs. Forced-air cooling or thermal vias are not required for this package.
The FLEX 8000 family uses 5 V CMOS I/O with TTL-compatible thresholds. Series-terminate clock and high-speed outputs (above 16 MHz) with 33 Ω resistors to dampen reflections on unterminated traces. Avoid daisy-chained clock distribution - use a clock buffer such as the 74FCT807 or Altera EPM7032 for fanout. Ground-bounce peaks can exceed 1.5 V when many outputs switch simultaneously, so avoid connecting FLEX 8000 outputs directly to analog signal chains without RC filtering.
コンプライアンス情報
EPF8636ALC84-4 uses lead-bearing PLCC packaging (legacy Altera FLEX 8000 family, pre-RoHS-transition product). Not AEC-Q100 qualified (industrial/consumer only). For lead-free requirement, EPF8282ALC84-4N is the lead-free counterpart in the same package.
