EPM7160ELI84-20 - MAX 7000 CPLD, 160 Macrocells, 5V, 84-PLCC | Intel
部品番号: EPM7160ELI84-20 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.05 | $1,405.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $11.1 | $11,100.00 |
EPM7160ELI84-20 概要
What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that sits between simple PAL/GAL devices and high-density FPGAs in the programmable logic hierarchy. CPLDs are typically used for glue logic, bus interfacing, state-machine control, and power-up sequencing in digital systems where deterministic timing, fast input-to-output propagation, and instant-on behavior are required. The MAX 7000 family is one of the longest-lived CPLD families in the industry, having shipped continuously since the 1990s in industrial, telecommunications, and embedded designs.
Key features of the EPM7160ELI84-20 include 64 user I/O pins organized into four Logic Array Blocks (LABs), a pin-to-pin propagation delay of 20 ns (the '-20' speed grade), 5.0V core VCC operation, and programmable power-saving mode on a per-macrocell basis. The device also offers open-drain output options, programmable security bits for design protection, and JTAG boundary-scan test support per IEEE 1149.1.
Architecturally, the EPM7160ELI84-20 uses a classic MAX-style AND-OR plane with a programmable interconnect array (PIA) that provides deterministic, consistent routing delays across all logic paths, simplifying static timing closure compared to FPGAs. Each macrocell contains a programmable flip-flop, product-term selection logic, and a configurable I/O register, enabling efficient implementation of wide combinatorial and registered logic.
Typical applications include industrial control and factory-automation boards, telecommunications line cards and legacy backplane glue logic, PCI bus interface bridges, address decoding and interrupt controllers in embedded CPU designs, and replacement of multiple discrete 74LS/74HC logic devices on legacy PCBs. The instant-on, non-volatile nature of the MAX 7000 family makes it especially attractive for safety-critical boot logic and deterministic control.
When designing with this device, plan I/O assignments early - the 84-pin PLCC exposes 64 usable I/Os and four dedicated JTAG/programming pins, so not all 84 pins are user I/O. Use the Altera/Intel Quartus (or legacy MAX+PLUS II) toolchain for synthesis, fitting, and programming, and respect the 5.0V VCC requirement when mixing with 3.3V logic (the I/Os are 5V-tolerant inputs but cannot drive 3.3V outputs above their VCCIO).
This page synthesizes distributor stock status, the same-brand MAX 7000 family drop-in variants, and practical design considerations not found in the manufacturer datasheet, helping engineers make informed decisions about lifecycle status and replacement strategy for this mature, long-running CPLD.
ドロップイン代替品: EPM7160ELI84-20 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM7160ELI84-20 （同一形状・フットプリント） — 相違点: Mounting Type, Operating Temperature, Package, RoHS Status, Family.
クイック比較ツール — 並列比較する代替部品を選択:
EPM7160ELC84-20
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$16.95 / 個
データシートを見る →EPM7160ELC84-15
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$5.95 / 個
データシートを見る →EPM7160ELC84-12
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$11.1 / 個
データシートを見る →EPM7160SLC84-10
✅ ドロップイン✓ 在庫あり
$35.77 / 個
データシートを見る →EPM7160SLC84-6
✅ ドロップイン✓ 在庫あり
$15.86 / 個
データシートを見る →EPM7160ELI84-20 最大定格＆電気的特性
| Series | MAX 7000 |
| Device Family | MAX 7000 (Complex Programmable Logic Device) |
| Number of Macrocells | 160 |
| Number of Logic Array Blocks (LABs) | 4 |
| Usable Gates | 3.2K |
| Number of User I/O Pins | 64 |
| Maximum Operating Frequency | 62.5 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns (speed grade '-20') |
| Supply Voltage (VCC) | 5.0 V |
| Process Technology | CMOS, EEPROM-based configuration |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Programmable Security | Yes (security bit) |
| パッケージ | 84-Pin PLCC (J-Lead) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (Industrial grade 'I') |
| RoHS ステータス | Not Compliant (per Arrow listing) |
| Configuration Memory | Non-volatile EEPROM (instant-on) |
EPM7160ELI84-20 ピン構成
| ピン 1 | I/O — User I/O pin (pin function programmable) |
| ピン 2 | I/O — User I/O pin (pin function programmable) |
| ピン 3 | I/O — User I/O pin (pin function programmable) |
| ピン 4 | I/O — User I/O pin (pin function programmable) |
| ピン 5 | I/O — User I/O pin (pin function programmable) |
| ピン 6 | I/O — User I/O pin (pin function programmable) |
| ピン 7 | I/O — User I/O pin (pin function programmable) |
| ピン 8 | I/O — User I/O pin (pin function programmable) |
| ピン 9 | I/O — User I/O pin (pin function programmable) |
| ピン 10 | I/O — User I/O pin (pin function programmable) |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O pin (pin function programmable) |
| ピン 13 | I/O — User I/O pin (pin function programmable) |
| ピン 14 | I/O — User I/O pin (pin function programmable) |
| ピン 15 | I/O — User I/O pin (pin function programmable) |
| ピン 16 | I/O — User I/O pin (pin function programmable) |
| ピン 17 | I/O — User I/O pin (pin function programmable) |
| ピン 18 | I/O — User I/O pin (pin function programmable) |
| ピン 19 | I/O — User I/O pin (pin function programmable) |
| ピン 20 | I/O — User I/O pin (pin function programmable) |
| ピン 21 | GND — Ground |
| ピン 22 | I/O — User I/O pin (pin function programmable) |
| ピン 23 | I/O — User I/O pin (pin function programmable) |
| ピン 24 | I/O — User I/O pin (pin function programmable) |
| ピン 25 | I/O — User I/O pin (pin function programmable) |
| ピン 26 | I/O — User I/O pin (pin function programmable) |
| ピン 27 | I/O — User I/O pin (pin function programmable) |
| ピン 28 | I/O — User I/O pin (pin function programmable) |
| ピン 29 | I/O — User I/O pin (pin function programmable) |
| ピン 30 | I/O — User I/O pin (pin function programmable) |
| ピン 31 | GND — Ground |
| ピン 32 | I/O — User I/O pin (pin function programmable) |
| ピン 33 | I/O — User I/O pin (pin function programmable) |
| ピン 34 | I/O — User I/O pin (pin function programmable) |
| ピン 35 | I/O — User I/O pin (pin function programmable) |
| ピン 36 | I/O — User I/O pin (pin function programmable) |
| ピン 37 | I/O — User I/O pin (pin function programmable) |
| ピン 38 | I/O — User I/O pin (pin function programmable) |
| ピン 39 | I/O — User I/O pin (pin function programmable) |
| ピン 40 | I/O — User I/O pin (pin function programmable) |
| ピン 41 | GND — Ground |
| ピン 42 | I/O — User I/O pin (pin function programmable) |
| ピン 43 | TDI — JTAG Test Data In (IEEE 1149.1) |
| ピン 44 | TMS — JTAG Test Mode Select (IEEE 1149.1) |
| ピン 45 | TCK — JTAG Test Clock (IEEE 1149.1) |
| ピン 46 | I/O — User I/O pin (pin function programmable) |
| ピン 47 | I/O — User I/O pin (pin function programmable) |
| ピン 48 | I/O — User I/O pin (pin function programmable) |
| ピン 49 | I/O — User I/O pin (pin function programmable) |
| ピン 50 | I/O — User I/O pin (pin function programmable) |
| ピン 51 | GND — Ground |
| ピン 52 | I/O — User I/O pin (pin function programmable) |
| ピン 53 | I/O — User I/O pin (pin function programmable) |
| ピン 54 | I/O — User I/O pin (pin function programmable) |
| ピン 55 | I/O — User I/O pin (pin function programmable) |
| ピン 56 | I/O — User I/O pin (pin function programmable) |
| ピン 57 | I/O — User I/O pin (pin function programmable) |
| ピン 58 | I/O — User I/O pin (pin function programmable) |
| ピン 59 | I/O — User I/O pin (pin function programmable) |
| ピン 60 | I/O — User I/O pin (pin function programmable) |
| ピン 61 | GND — Ground |
| ピン 62 | I/O — User I/O pin (pin function programmable) |
| ピン 63 | I/O — User I/O pin (pin function programmable) |
| ピン 64 | I/O — User I/O pin (pin function programmable) |
| ピン 65 | I/O — User I/O pin (pin function programmable) |
| ピン 66 | I/O — User I/O pin (pin function programmable) |
| ピン 67 | I/O — User I/O pin (pin function programmable) |
| ピン 68 | I/O — User I/O pin (pin function programmable) |
| ピン 69 | I/O — User I/O pin (pin function programmable) |
| ピン 70 | I/O — User I/O pin (pin function programmable) |
| ピン 71 | GND — Ground |
| ピン 72 | I/O — User I/O pin (pin function programmable) |
| ピン 73 | I/O — User I/O pin (pin function programmable) |
| ピン 74 | I/O — User I/O pin (pin function programmable) |
| ピン 75 | I/O — User I/O pin (pin function programmable) |
| ピン 76 | I/O — User I/O pin (pin function programmable) |
| ピン 77 | TDO — JTAG Test Data Out (IEEE 1149.1) |
| ピン 78 | GND — Ground |
| ピン 79 | I/O — User I/O pin (pin function programmable) |
| ピン 80 | I/O — User I/O pin (pin function programmable) |
| ピン 81 | I/O — User I/O pin (pin function programmable) |
| ピン 82 | I/O — User I/O pin (pin function programmable) |
| ピン 83 | I/O — User I/O pin (pin function programmable) |
| ピン 84 | VCC — +5.0V supply voltage |
主な用途
EPM7160ELI84-20 の用途: 6 件s: Industrial Control & Factory Automation, Telecommunications Backplane Glue Logic, Legacy PCI / ISA Bus Interface Bridges, Embedded CPU Address Decoding & Chip-Select Generation, Replacing Multiple 74-Series Discrete Logic ICs, Power-Up Sequencing & Reset Distribution.
Industrial Control & Factory Automation
The EPM7160ELI84-20 is well-suited for industrial PLCs, motor-control boards, and factory-automation controllers requiring deterministic glue logic between microcontrollers, sensors, and actuators. Its 160 macrocells and 64 user I/Os provide ample capacity to consolidate multiple 74LS/74HC discrete-logic packages into a single reprogrammable device, simplifying BOM and PCB layout. The industrial -40C to +85C temperature rating enables deployment in uncontrolled factory-floor environments without derating. The 20 ns pin-to-pin delay delivers deterministic timing for safety-interlock logic and emergency-stop signal paths. The 5V tolerance and JTAG ISP allow in-field firmware updates via standard programming hardware without removing the board from service, reducing maintenance windows in 24/7 production lines.
おすすめ
Telecommunications Backplane Glue Logic
Legacy telecommunications line cards, T1/E1 interface boards, and central-office switching equipment commonly use the EPM7160ELI84-20 for address decoding, interrupt steering, and bus-interface bridging. The 62.5 MHz maximum frequency and 20 ns tPD comfortably handle bus-cycle timing for 33 MHz PCI and proprietary backplane protocols at 5V logic levels. The 64 user I/Os can replace dozens of discrete 74FCT and 74ABT logic devices, freeing board area for higher-value signal-conditioning circuitry. EEPROM-based instant-on configuration eliminates the need for external boot PROMs, critical for telecom systems that must come up in a defined state after power restoration. JTAG boundary-scan testability per IEEE 1149.1 simplifies board-level test and field diagnostics.
おすすめ
Legacy PCI / ISA Bus Interface Bridges
The EPM7160ELI84-20 is widely deployed as a PCI-to-local-bus bridge, ISA bus decoder, and interrupt controller in embedded x86 systems where its 5V-tolerant I/Os and 20 ns propagation delay match the legacy bus timing budgets. Designers use its 160 macrocells to implement bus-state machines, address-decoder PLAs, and wait-state generators that would otherwise require multiple PAL/GAL devices. The 5.0V core supply aligns with PCI 5V signaling and ISA bus levels, avoiding the need for level shifters. EEPROM non-volatility means the bridge logic is operational within microseconds of power-on, satisfying the PCI specification's bus-enumeration timing requirements. The 84-pin PLCC remains in production for legacy board-repair and obsolescence-management programs in industrial PCs and point-of-sale terminals.
おすすめ
Embedded CPU Address Decoding & Chip-Select Generation
Embedded designs based on 80186, 68k, PowerPC, and ARM7 processors use the EPM7160ELI84-20 to generate chip-select signals, decode memory maps, and arbitrate shared bus peripherals. Its 160 macrocells and 64 I/Os can implement 8 to 16 independent chip-select decoders with individually programmable wait-state insertion. The deterministic 20 ns tPD delivers consistent chip-select timing regardless of input combinations, critical for zero-wait-state memory interfaces. The non-volatile EEPROM configuration means the memory map is locked-in at power-on without external boot logic, simplifying system bring-up. Industrial temperature grade supports embedded boards deployed in outdoor enclosures, vehicle controllers, and ruggedized military/aerospace subsystems.
おすすめ
Replacing Multiple 74-Series Discrete Logic ICs
The EPM7160ELI84-20 is a classic BOM-reduction tool, replacing 10 to 20 discrete 74LS, 74HC, 74FCT, or 74ABT logic packages with a single programmable device in legacy PCBs. Each macrocell can implement a sum-of-products equation equivalent to a 74-series PAL/GAL, and the wide input gating (up to 36 inputs per macrocell in MAX 7000) supports complex combinatorial functions. The 5V VCC directly replaces 74LS/74HC designs without supply changes. JTAG ISP allows engineers to fix logic bugs, add features, or respin functionality without reworking the PCB - a key advantage for legacy products still in service but out of production. This application is especially valuable in aerospace, medical-device, and industrial-automation fields where board re-spins are expensive or require regulatory re-certification.
おすすめ
Power-Up Sequencing & Reset Distribution
In multi-rail systems requiring careful power-up sequencing (ASICs, FPGAs, microcontrollers, and analog ICs), the EPM7160ELI84-20 provides deterministic sequencing logic that becomes active immediately upon VCC ramp thanks to its non-volatile EEPROM configuration. The device can monitor up to 64 input rails or enable signals, generate programmable delay chains via its macrocell flip-flops, and drive sequencing outputs with 20 ns precision. Compared to a sequencer IC, the EPM7160ELI84-20 allows full customization of timing, polarity, and dependencies without a separate firmware step. Industrial temperature rating and 5V tolerance suit it for ATX, telecom-shelf, and industrial-PC power architectures where 5V standby rails are standard.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM7160ELI84-20 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM7160ELC84-20 | EPM7160ELC84-15 | EPM7160ELC84-12 | EPM7160SLC84-10 | EPM7160SLC84-6 |
|---|---|---|---|---|---|---|
| Package | 84-Pin PLCC | 84-Pin PLCC - same | 84-Pin PLCC - same | 84-Pin PLCC - same | 84-Pin PLCC - same | 84-Pin PLCC - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 160 |
| Usable Gates | 3.2K | 3.2K | 3.2K | 3.2K | 3.2K | 3.2K |
| Pin-to-Pin Delay (tPD) | 20 ns | 20 ns (same) | 15 ns (faster) | 12 ns (faster) | 10 ns (faster) | 6 ns (much faster) |
| Max Operating Frequency | 62.5 MHz | 62.5 MHz | 76.9 MHz | 100 MHz | 100 MHz | 125 MHz |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Supply Voltage (VCC) | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Family | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000S | MAX 7000S |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Industrial temperature grade at 5V （vs EPM7160ELC84-20)
- Higher logic capacity than MAX 7000S -6 parts in same package （vs EPM7128SLC84-6N)
- Non-volatile EEPROM vs SRAM-based FPGAs （vs Cyclone FPGAs)
設計ノート
The EPM7160ELI84-20 requires a stable 5.0V (4.75-5.25V) supply with sufficient decoupling. Place a 0.1uF ceramic decoupling capacitor as close as possible to each VCC pin (the 84-PLCC has multiple VCC/GND pairs distributed around the package), plus a single 10uF tantalum or aluminum bulk capacitor at the board entry point. The device's I/O pins source/sink up to 25 mA per pin (typical), so total VCC current can exceed 200 mA in heavily-loaded designs - verify your regulator has adequate headroom. Avoid placing the CPLD near high-current switching nodes (relays, motor drivers) to minimize supply-rail noise coupling into the 5V rail.
For 84-pin PLCC designs, use a PLCC socket (machine-pin or low-profile) to allow in-system programming and easy replacement of obsolete parts. Keep JTAG signals (TDI, TDO, TMS, TCK) accessible via a 2x5 0.1-inch header for ByteBlasterMV/USB-Blaster connection during development and field updates. Route JTAG traces away from high-speed switching signals and keep them under 6 inches to maintain signal integrity. For the 84-PLCC, the recommended land pattern is JEDEC MS-018 - follow this exactly to ensure socket compatibility. Add a ground plane beneath the device to provide low-impedance return paths for the high-speed I/O switching currents.
Estimated: When migrating from EPM7160ELI84-20 (industrial -40C to +85C) to EPM7160ELC84-20 (commercial 0C to +70C), confirm the target environment stays within the C-grade temperature range or the device lifetime will be severely reduced. Do not assume the MAX 7000 family is pin-compatible with MAX 7000S - bitstream files are not interchangeable even though packages match; recompile in Quartus for any -S variant. The 5V I/Os cannot directly drive 3.3V logic above their VIH level without level shifters or resistor dividers. When designing for new products in 2026, prefer MAX II (EPM240/570) or MAX V (5M80ZE64) for active lifecycle and lower power, reserving MAX 7000 for legacy board-repair applications.
コンプライアンス情報
RoHS non-compliant per Arrow EPM7160ELI84-20 listing (legacy 5V MAX 7000 PLCC part contains lead-based solder finish). AEC-Q100 not qualified - this is a general-purpose CPLD, not an automotive-grade part. Reach compliance status not explicitly listed in the provided data.
