EPF8636ALC84-4 - FLEX 8000 FPGA, 504 Cells, 84-PLCC | Intel / Altera
MPN: EPF8636ALC84-4 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $44.18 | $44.18 |
| 10 | $39.76 | $397.60 |
| 100 | $33.14 | $3,314.00 |
| 500 | $28.62 | $14,310.00 |
| 1,000 | $24.3 | $24,300.00 |
Drop-in alternatives for EPF8636ALC84-4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPF8636ALC84-3
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View Datasheet →EPF8282ALC84-4
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View Datasheet →EPF8282ALC84-4N
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View Datasheet →EPF8452ALC84-4
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View Datasheet →EPF8452ALC84-3
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View Datasheet →EPF8452ALI84-4
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View Datasheet →EPF8282ALC84-3
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View Datasheet →EPF8636ALC84-4 Maximum Ratings & Electrical Characteristics
| Family | FLEX 8000 |
| Number of Logic Cells | 504 |
| Number of Logic Array Blocks (LABs) | 63 |
| Maximum Usable Gates | 6,000 |
| Number of User I/O Pins | 68 |
| Maximum Operating Frequency | 125 MHz |
| Process Technology | 0.42 µm CMOS SRAM |
| Supply Voltage (Core) | 5.0 V |
| I/O Voltage (84-pin PLCC) | 5.0 V only (3.3 V I/O NOT supported on this package) |
| Operating Current (typical) | 10 mA |
| Package | 84-Pin PLCC (J-Lead) |
| Mounting Type | Surface Mount / Socket |
| Operating Temperature | 0 °C to +70 °C (Commercial) |
| Speed Grade | -4 |
| Configuration Method | Serial (EPC1/EPC1064/EPC1213/EPC1441) or parallel EPROM |
| Configuration Memory Type | Volatile SRAM (requires boot device) |
| Boundary Scan | IEEE 1149.1 (JTAG) |
| RoHS Status | Non-compliant (legacy PLCC, lead-bearing) |
EPF8636ALC84-4 Pin Configuration
| Pin 1 | I/O — User I/O pin (LAB row/column dependent) |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | VCC — Core supply voltage (5.0 V) |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | TMS — JTAG Test Mode Select |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | TCK — JTAG Test Clock |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | GND — Ground |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | VCC — Core supply voltage (5.0 V) |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | nCONFIG — Configuration control (active low) |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | GND — Ground |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | I/O — User I/O pin |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | VCC — Core supply voltage (5.0 V) |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | GND — Ground |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | DCLK — Configuration clock |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | DATA0 — Configuration data input |
| Pin 71 | nSTATUS — Configuration status (active low) |
| Pin 72 | CONF_DONE — Configuration done (open-drain) |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | I/O — User I/O pin |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | VCC — Core supply voltage (5.0 V) |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | I/O — User I/O pin |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | TDO — JTAG Test Data Out |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8636ALC84-4 is suitable for 7 applications: Industrial Glue Logic Replacement, Legacy PCI Bus Bridge and Interface Controller, Telecommunications Control Card, Parallel Peripheral Interface (Centronics, GPIB, SCSI), Educational FPGA Development Platform, Legacy Industrial Bus Controller (VME, ISA, Multibus), Custom State-Machine Replacement of TTL/CMOS Logic.
Industrial Glue Logic Replacement
The EPF8636ALC84-4 fits legacy industrial glue-logic replacement because it integrates 504 logic cells and 68 I/Os into a single 5 V device, replacing dozens of 74-series TTL gates while preserving the 84-pin PLCC socket footprint common on 1990s-era control boards. Its 125 MHz Fmax in the -4 speed grade easily handles bus arbitration, address decoding, and timing-generator functions at industrial clock rates below 50 MHz. MultiVolt I/O limitations on the 84-pin PLCC mean designs must remain on 5 V rails, matching most legacy industrial backplanes. JTAG boundary-scan support simplifies board-level test in production.
Recommended
Legacy PCI Bus Bridge and Interface Controller
The EPF8636ALC84-4 is well suited to legacy 33 MHz, 32-bit PCI bridge and interface-controller implementations because its 504 logic cells comfortably absorb the PCI state machine, parity logic, and address-decoder needed for an add-in card, while 68 user I/Os are sufficient to expose a 32-bit PCI bus plus auxiliary peripheral pins. The 5 V PCI signalling standard matches the device's 5 V I/O-only 84-pin PLCC variant without level shifters. The -4 speed grade comfortably closes 33 MHz timing at 30% utilization in MAX+PLUS II. Designers should observe 5 V tolerance and PCI 2.1 add-in card mechanical requirements.
Recommended
Telecommunications Control Card
In telecommunications control cards such as E1/T1 line-interface controllers, ISDN termination boards, and central-office crosspoint switches, the EPF8636ALC84-4 offers sufficient logic density to implement HDLC framing, timeslot assignment, and alarm logic in a single device. Its 5 V tolerant I/Os interface directly to legacy telecom line-interface ICs (LIUs) without level shifters, while 63 LABs and embedded EABs provide the on-chip RAM required for small elastic buffers and lookup tables. The 0 to 70 °C operating range covers indoor central-office environments. JTAG support simplifies in-system test on populated backplanes.
Recommended
Parallel Peripheral Interface (Centronics, GPIB, SCSI)
The EPF8636ALC84-4 can be used as the controller for legacy parallel peripheral interfaces such as Centronics parallel ports, IEEE-488 GPIB controller cards, and SCSI-2 host adapters, where 68 user I/Os directly drive the data, handshake, and control lines without external bus transceivers for short-distance applications. The 504 logic cells absorb the state machine, handshaking, and DMA arbitration logic, while the 125 MHz Fmax comfortably handles 8 MHz SCSI and 1 Mbyte/s Centronics throughput. 5 V I/O operation matches classic peripheral bus signalling levels.
Recommended
Educational FPGA Development Platform
Universities and training labs frequently choose the EPF8636ALC84-4 for introductory digital-design courses because the 84-pin PLCC package is large enough to probe with standard oscilloscope hooks, the 5 V supply matches breadboard-friendly power rails, and the 504-cell capacity supports moderate lab projects such as UARTs, simple CPUs, and VGA controllers. The mature MAX+PLUS II toolchain is freely available and includes example designs, making the device an excellent pedagogical tool. The low cost on the secondary market (around $44 per unit) suits lab budgets when the part is treated as a consumable.
Recommended
Legacy Industrial Bus Controller (VME, ISA, Multibus)
In VMEbus, ISA, and Multibus-based industrial controllers that remain in service on factory floors, the EPF8636ALC84-4 serves as a bus-master or slave controller implementing address decoding, interrupt handling, and DMA handshaking. The 5 V signalling matches VME and ISA backplane levels directly, and 68 user I/Os can be allocated between data, address, and control buses. With 504 cells the device can host the entire bus-interface state machine plus local peripheral glue. The commercial 0 to 70 °C range suits indoor control cabinets, while JTAG aids in-cabinet programming during commissioning.
Recommended
Custom State-Machine Replacement of TTL/CMOS Logic
Designers replacing dozens of discrete 74LS/74HC TTL or 4000-series CMOS packages with a single programmable device often choose the EPF8636ALC84-4 because the 504 logic cells and 63 LABs are sufficient to absorb mid-sized state machines, decoders, and timing generators, while 68 I/Os comfortably replace 16 to 20 packages of glue logic. The 5 V I/O-only PLCC variant integrates directly into existing 5 V designs without level shifting. In-system SRAM-based programmability lets engineers iterate designs quickly without rework, and the obsolete status makes remaining stock attractive for one-off legacy repairs.
Recommended
Recommended Products Summary
Engineering reference data for EPF8636ALC84-4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8636ALC84-3 | EPF8282ALC84-4 | EPF8452ALC84-4 | EPF8452ALI84-4 |
|---|---|---|---|---|---|
| Brand | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) |
| Package | 84-Pin PLCC (J-Lead) | 84-Pin PLCC (J-Lead) - same | 84-Pin PLCC (J-Lead) - same | 84-Pin PLCC (J-Lead) - same | 84-Pin PLCC (J-Lead) - same |
| Logic Cells | 504 | 504 | 208 | 452 | 452 |
| Number of LABs | 63 | 63 | 26 | 56 | 56 |
| User I/O Pins | 68 | 68 | 68 | 68 | 68 |
| Speed Grade | -4 (fast) | -3 | -4 | -4 | -4 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) | -40 °C to +85 °C (Industrial) |
| Process | 0.42 µm CMOS | 0.42 µm CMOS | 0.42 µm CMOS | 0.42 µm CMOS | 0.42 µm CMOS |
| Configuration Memory | Volatile SRAM | Volatile SRAM | Volatile SRAM | Volatile SRAM | Volatile SRAM |
Key Differentiators
- Highest-density 84-pin PLCC FLEX 8000 device (vs EPF8452ALC84-4)
- Fastest speed grade available in EPF8636A 84-PLCC family (vs EPF8636ALC84-3)
- Mature FLEX 8000 toolchain support with broad reference designs (vs EPF8282ALC84-4)
Design Notes
The EPF8636ALC84-4 requires a stable 5.0 V supply with adequate decoupling. Place a 100 µF bulk tantalum capacitor and 0.1 µF ceramic decoupling caps on every VCC/GND pair within 25 mm of the package. Estimated: at full I/O switching (68 outputs at 20 pF each, 25 MHz), I/O supply current can exceed 100 mA transient - budget 5 V regulator headroom accordingly and use a low-ESR bulk cap. Core current at 10 mA typical is modest; the I/O bank dominates the power budget.
Do not assume 3.3 V I/O capability on the 84-pin PLCC package. The EPF8636A 84-pin variant supports 5.0 V I/O only; driving 3.3 V signals into a 5 V CMOS input is acceptable but 5 V signals into a 3.3 V receiver downstream requires a level shifter. Engineers migrating to this part from a larger FLEX 8000 package (e.g. 144-pin TQFP) often overlook this restriction and damage downstream 3.3 V ASICs.
Route JTAG signals (TCK, TMS, TDI, TDO) with short traces and a 10 kΩ pull-up on TCK/TMS/TDI per the IEEE 1149.1 spec. Place the EPC1 or EPC1064 configuration device within 50 mm of the FLEX 8000 to keep the DCLK and DATA0 traces short - long configuration traces introduce bit errors during boot. Provide a 1 kΩ pull-up on nCONFIG and nSTATUS to allow in-system reprogramming via JTAG or external controller.
The EPF8636ALC84-4 in 84-pin PLCC has a thermal resistance (θJA) on the order of 35-45 °C/W for a socketed part in still air. At typical 10 mA core current and 5 V supply, power dissipation is roughly 50 mW (core) plus I/O switching losses, well within the commercial 0-70 °C range. Estimated junction temperature rise at 0.5 W total dissipation: 17-22 °C above ambient - no heatsink needed for socketed designs. Forced-air cooling or thermal vias are not required for this package.
The FLEX 8000 family uses 5 V CMOS I/O with TTL-compatible thresholds. Series-terminate clock and high-speed outputs (above 16 MHz) with 33 Ω resistors to dampen reflections on unterminated traces. Avoid daisy-chained clock distribution - use a clock buffer such as the 74FCT807 or Altera EPM7032 for fanout. Ground-bounce peaks can exceed 1.5 V when many outputs switch simultaneously, so avoid connecting FLEX 8000 outputs directly to analog signal chains without RC filtering.
Compliance Information
EPF8636ALC84-4 uses lead-bearing PLCC packaging (legacy Altera FLEX 8000 family, pre-RoHS-transition product). Not AEC-Q100 qualified (industrial/consumer only). For lead-free requirement, EPF8282ALC84-4N is the lead-free counterpart in the same package.
