EPM9560GI280-15 - 560-Macrocell MAX 9000 EPLD, 280-Pin PGA | Intel
部品番号: EPM9560GI280-15 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $165 | $165.00 |
| 10 | $148.5 | $1,485.00 |
| 100 | $132 | $13,200.00 |
| 250 | $121 | $30,250.00 |
| 500 | $110 | $55,000.00 |
EPM9560GI280-15 概要
A programmable logic device (PLD) is a general-purpose digital integrated circuit whose logic function and interconnects are defined by the end user after manufacturing. The MAX 9000 series implements a third-generation Multiple Array MatriX (MAX) architecture combining a programmable logic array with a fixed EEPROM configuration memory, allowing in-system programmability via 5.0-V tolerant ISP. Within the broader taxonomy, the EPM9560 is a Complex PLD (CPLD) positioned between small PLDs and full FPGAs, optimized for deterministic timing, fast pin-to-pin propagation, and low power at moderate logic densities.
Key features include 5.0-V in-system programmability (ISP), 3.3-V or 5-V flexible I/O operation, an internal frequency up to 145 MHz, propagation delay of 11.4 ns (tPD) at the -15 speed grade, 216 user I/Os, 12 dedicated inputs, and 560 macrocells for wide combinational/sequential logic. The 280-pin PGA ceramic, metal-sealed cofired package provides industrial-grade reliability across -40°C to 85°C operation.
The MAX architecture integrates a global interconnect matrix that delivers consistent, predictable timing across all 560 macrocells, which is critical when replacing multiple discrete PAL/GAL devices with a single CPLD. Each macrocell contains a programmable AND/OR array with a flip-flop, allowing implementation of state machines, counters, and registered logic without FPGA-like routing variability.
Typical applications include industrial control glue logic, communications backplane interfacing, PCI bus bridging, and legacy system upgrades. Engineers typically choose the EPM9560 when deterministic timing, instant-on from EEPROM, and high I/O count are required in environments where modern FPGAs are over-spec or over-priced.
When designing with the EPM9560GI280-15, ensure that the chosen socket supports 280-pin PGA with the correct pin grid pattern; verify that the Quartus / MAX+PLUS II legacy toolchain still supports the device family for new compilation flows. For new designs, evaluate MAX II or MAX V CPLDs as modern equivalents with lower power and faster compilation.
This page synthesizes distributor inventory, drop-in ceramic-PGA alternatives from the MAX 9000 family, and practical design considerations not consolidated in the original datasheet, giving procurement and engineering teams a faster decision path.
ドロップイン代替品: EPM9560GI280-15 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560GI280-15 （同一形状・フットプリント） — 相違点: Package, Architecture, In-System Programmability, Device Type, Usable Gates.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560GC280-15
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$115 / 個
データシートを見る →EPM9560GC280-15N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$125 / 個
データシートを見る →EPM9560GC280-20
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$360 / 個
データシートを見る →EPM9560GC280-20N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$285 / 個
データシートを見る →EPM9560ARC240-10
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$28.8 / 個
データシートを見る →EPM9560GI280-15 最大定格＆電気的特性
| Device Family | MAX 9000 |
| Architecture | CMOS EEPROM, third-generation Multiple Array MatriX (MAX) |
| Macrocells | 560 |
| Flip-Flops | 772 |
| User I/Os | 216 |
| Dedicated Inputs | 12 |
| Logic Elements / Gates | 12,000 usable gates |
| Internal Frequency (fMAX) | 145 MHz |
| Propagation Delay (tPD) | 11.4 ns |
| Clock-to-Output (tCO) | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | 4.5 V to 5.5 V (3.3 V or 5 V I/O) |
| In-System Programmability | 5.0-V ISP via JTAG |
| パッケージ | 280-pin PGA (ceramic, metal-sealed cofired) |
| 動作温度 | -40 °C to 85 °C (industrial) |
| Process Technology | CMOS EEPROM |
| 湿気感度レベル（MSL） | MSL-3 (168 hours) |
EPM9560GI280-15 280-pin pga (ceramic, metal-sealed cofired) ピン配置ガイド
EPM9560GI280-15 (280-pin pga (ceramic, metal-sealed cofired) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EPM9560GI280-15.
詳細は データシート をご参照ください。
主な用途
EPM9560GI280-15 の用途: 6 件s: Industrial Glue Logic Replacement, Telecom Backplane Bus Bridging, Legacy Avionics Display Controllers, PCI Bus Interface and Arbitration, Medical Imaging Signal Routing, Test & Measurement Equipment Front-End.
Industrial Glue Logic Replacement
The EPM9560GI280-15 fits industrial glue-logic replacement because it consolidates 560 macrocells (12,000 usable gates) into a single ceramic PGA package, eliminating the need for multiple discrete PAL/GAL devices on legacy backplanes. Its deterministic 11.4 ns pin-to-pin propagation delay and 145 MHz internal frequency handle address decoding, bus arbitration, and interrupt priority logic at full system clock without FPGA-like routing variability. Industrial -40 °C to 85 °C operation with 5-V tolerant I/O allows direct interfacing with TTL/CMOS legacy peripherals, simplifying board bring-up.
おすすめ
Telecom Backplane Bus Bridging
The EPM9560GI280-15 is ideal for telecom backplane bus bridging where 216 user I/Os can absorb multiple parallel buses (PCI, H.110, local CPU bus) into a single chip with deterministic timing. Its 772 flip-flops implement deep FIFO buffers and protocol state machines, while 11.4 ns tPD ensures protocol timing margins are met on T1/E1 and ISDN-PRI backplanes. 5-V ISP allows field upgrades without removing the line card, critical for deployed telecom infrastructure.
おすすめ
Legacy Avionics Display Controllers
The EPM9560GI280-15 suits legacy avionics display controllers that require ceramic PGA packages (hermetic, high-reliability), 5-V I/O tolerance for MIL-STD-1553 or ARINC 429 interfaces, and instant-on from EEPROM for fail-safe startup. Its 560 macrocells and 772 flip-flops support character generators, lookup tables, and timing generation for CRT/LCD avionics displays, while the ceramic PGA package withstands vibration and thermal cycling of -40 °C to 85 °C cockpit environments.
おすすめ
PCI Bus Interface and Arbitration
The EPM9560GI280-15 is well-suited for PCI bus interface and arbitration logic at 33 MHz because its 11.4 ns tPD and 145 MHz fMAX meet PCI 2.2 timing with comfortable margin. The 560 macrocells implement full target/initiator state machines, parity generation, and bus arbiter logic, while 216 user I/Os support multiple PCI slots or PCI-X bridges on legacy server motherboards. 5-V tolerant I/O is compatible with 5-V PCI signaling used in industrial SBCs.
おすすめ
Medical Imaging Signal Routing
The EPM9560GI280-15 fits medical imaging signal routing (ultrasound, X-ray) where deterministic timing of 11.4 ns tPD synchronizes analog front-end multiplexer control with ADC sampling clocks. Its 560 macrocells implement beamforming logic for ultrasound transducers, while 5-V tolerant I/O interfaces to legacy medical-instrumentation front ends. Ceramic PGA packaging provides the long-term reliability and solder-joint integrity required for FDA/IEC 60601 medical-device compliance.
おすすめ
Test & Measurement Equipment Front-End
The EPM9560GI280-15 supports test-and-measurement equipment front ends that require dense logic, fast deterministic timing, and 5-V I/O for legacy instrument buses (GPIB/IEEE-488, VXI). Its 560 macrocells implement trigger sequencing, time-base generation, and front-panel switching matrices, while 772 flip-flops support deep counters for frequency counters and time-interval analyzers. Ceramic PGA reliability and -40 to 85 °C operation suit benchtop and field-portable instrument use.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560GI280-15 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560GC280-15 | EPM9560GC280-15N | EPM9560GC280-20 | EPM9560GC280-20N | EPM9560ARC240-10 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 280-pin PGA (ceramic) | 280-pin PGA (ceramic) - same | 280-pin PGA (ceramic) - same | 280-pin PGA (ceramic) - same | 280-pin PGA (ceramic) - same | 240-pin PGA (ceramic) - smaller |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Speed Grade (tPD / fMAX) | -15 (11.4 ns / 145 MHz) | -15 (11.4 ns / 145 MHz) | -15 (11.4 ns / 145 MHz) | -20 (16.6 ns / 118 MHz) | -20 (16.6 ns / 118 MHz) | -10 (10 ns / 151 MHz) |
| Operating Temperature | -40 °C to 85 °C (Industrial) | 0 °C to 70 °C (Commercial) | 0 °C to 70 °C (Commercial Pb-free) | 0 °C to 70 °C (Commercial) | 0 °C to 70 °C (Commercial Pb-free) | -40 °C to 85 °C (Industrial) |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| In-System Programmability | 5.0-V ISP | 5.0-V ISP | 5.0-V ISP | 5.0-V ISP | 5.0-V ISP | 5.0-V ISP |
主な差別化要因
- Largest density MAX 9000 device with full 216 I/O （vs EPM9480RC240-15)
- Industrial temperature range vs commercial-grade variants （vs EPM9560GC280-15)
- Mid-tier speed grade balances performance and power （vs EPM9560GC280-20)
- Largest 280-pin ceramic PGA I/O exposure （vs EPM9560ABC356-10)
設計ノート
The 280-pin ceramic PGA package has high thermal mass but limited PCB-side heat dissipation. Estimated: at internal frequency 145 MHz with all 560 macrocells active (typical toggle rate 25%), power dissipation is approximately 1.8 W (per MAX 9000 datasheet Icc spec). Mount the device in a PGA socket with thermal vias under the socket to a copper pour, or use a heatsink for industrial-temperature operation above 70 °C ambient. Add 100 lfm airflow for closed-enclosure deployments.
The 280-pin PGA requires a through-hole socket; do not solder directly to the PCB because field-replacement of NRND parts is expected. Use a machined-pin PGA socket (e.g. 3M/Textool) for reliable insertion cycles; specify a socket with low-inductance (<5 nH) lead frame to preserve signal integrity on clocks >100 MHz. Decouple each VCC/VCCIO pin pair with 0.1 µF X7R ceramic placed within 5 mm of the pin via; add bulk 47 µF tantalum or polymer capacitor near the socket.
Do not assume new design-ins are supported; the MAX 9000 family is NRND and Quartus II legacy support is limited. For new designs, evaluate MAX II EPM570, MAX V 5M240ZT, or MAX 10 10M08 series which are active, lower power, and supported by current Quartus Prime toolchains. When upgrading an existing design, verify that the new toolchain supports the legacy MAX 9000 BSDL/POF files for JTAG ISP and boundary-scan testing.
Use JTAG pins (TCK, TMS, TDI, TDO, TRST) as dedicated I/O - do not share with user logic - so boundary-scan ISP works without board re-routing. Place a 4.7 kΩ pull-up on TCK and a 1 kΩ pull-up on TMS/TRST per IEEE 1149.1. Route JTAG signals to a 10-pin header in a star topology to avoid stub reflections; add series 33 Ω damping resistors on long JTAG traces (>50 mm).
コンプライアンス情報
CERAMIC PGA packages were historically exempt from RoHS lead-free conversion due to high-temp solder constraints; the 'N' suffix denotes Pb-free commercial variants where available (e.g. EPM9560GC280-15N). Reach and halogen status were not specified in distributor data; set to 'unknown'.
