EPM9560GC280-20N - 560 Macrocell MAX 9000 CPLD, 280-Pin CPGA | Altera
部品番号: EPM9560GC280-20N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $418 | $418.00 |
| 10 | $380 | $3,800.00 |
| 100 | $345 | $34,500.00 |
| 500 | $310 | $155,000.00 |
| 1,000 | $285 | $285,000.00 |
EPM9560GC280-20N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip with a central interconnect. CPLDs sit alongside FPGAs in the programmable logic hierarchy, offering predictable timing, instant-on behavior from EEPROM storage, and high I/O count — making them preferred for glue logic, bus interfacing, and state-machine control in systems where deterministic timing matters more than raw logic density.
Key features include 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, 4.75 V to 5.25 V supply operation, configurable I/O voltage at 3.3 V or 5 V, and counter speeds up to 144 MHz. The MAX architecture provides fast, predictable input-to-output combinational delays and supports PCI compliance, making the device suitable for high-performance bus-interface applications.
Architecturally, the EPM9560GC280-20N integrates Logic Array Blocks (LABs), an interconnect matrix, and I/O control blocks. Each macrocell contains a programmable AND/OR array with a configurable flip-flop, supporting D, T, JK, and SR flip-flop modes. The EEPROM configuration cell provides non-volatile storage, eliminating the need for an external boot PROM and enabling instant-on operation at power-up.
Typical applications include PCI bus interfaces, high-speed glue logic between microprocessors and peripherals, bus arbitration logic, DSP control interfaces, and legacy industrial-control replacement designs. The wide I/O count and JTAG ISP support make it especially attractive for prototyping and field-upgradable systems.
When designing with the EPM9560GC280-20N, ensure proper decoupling of each VCC and GND pin pair, and follow Altera's MAX 9000 application notes for JTAG chain configuration and signal-integrity layout. The 'N' suffix typically denotes an industrial temperature grade or lead-free finish — verify with the manufacturer datasheet for the specific grade of your part.
This page synthesizes distributor pricing, same-brand drop-in alternatives, and practical design notes not found in the manufacturer datasheet — providing an engineering-grade reference for the EPM9560GC280-20N that goes beyond what DigiKey, Mouser, or Octopart product pages offer individually.
ドロップイン代替品: EPM9560GC280-20N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560GC280-20N （同一形状・フットプリント） — 相違点: Package, Architecture, In-System Programmability, Usable Gates, Device Type.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560GC280-20
✅ ドロップイン✓ 在庫あり
$360 / 個
データシートを見る →EPM9560GC280-15N
✅ ドロップイン✓ 在庫あり
$125 / 個
データシートを見る →EPM9560GC280-15
✅ ドロップイン✓ 在庫あり
$115 / 個
データシートを見る →EPM9560ELI84-20
✅ ドロップイン✓ 在庫あり
$19.5 / 個
データシートを見る →EPM9560GC280-20N 最大定格＆電気的特性
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation |
| Technology | CMOS EEPROM-based |
| Usable Gates | 6,000 to 12,000 |
| Macrocells | 560 |
| User I/O Pins | 212 |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Maximum Counter Frequency | 144 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| I/O Voltage | 3.3 V or 5 V (configurable) |
| In-System Programmability | Yes (5.0-V ISP via IEEE 1149.1 JTAG) |
| パッケージ | 280-pin CPGA (Ceramic Pin Grid Array) |
| Configuration Memory | EEPROM (non-volatile, instant-on) |
| PCI Compliance | Yes |
EPM9560GC280-20N 280-pin cpga (ceramic pin grid array) ピン配置ガイド
EPM9560GC280-20N (280-pin cpga (ceramic pin grid array) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EPM9560GC280-20N.
詳細は データシート をご参照ください。
主な用途
EPM9560GC280-20N の用途: 6 件s: PCI Bus Interface Logic, High-Speed Processor-to-Peripheral Glue Logic, DSP and Microcontroller Address Decoding, Legacy Industrial Control Replacement, JTAG Boundary-Scan Test Infrastructure, Bus Arbitration and DMA Control.
PCI Bus Interface Logic
The EPM9560GC280-20N's 212 user I/O pins and PCI compliance make it well-suited for bridging processor buses to 33 MHz / 66 MHz PCI peripherals. With a 20 ns tPD and 144 MHz counter frequency, the device meets PCI 2.2 timing budgets for address decoding, command/byte-enable decoding, and target/initiator state machines. Place the CPLD between the host CPU and PCI bus to consolidate glue logic, decode CONFIG address space, and arbitrate IRQ lines — eliminating discrete 74-series logic and shrinking board area. Verified Web Data confirms the MAX 9000 family is officially PCI-compliant.
おすすめ
High-Speed Processor-to-Peripheral Glue Logic
The EPM9560GC280-20N's 560 macrocells and 20 ns tPD deliver deterministic combinational logic for processor-to-memory and processor-to-peripheral glue functions. The EEPROM-based MAX architecture provides instant-on behavior at power-up, eliminating boot-PROM delay for address decoding, chip-select generation, and wait-state insertion. Compared to discrete TTL/CMOS glue, the integrated CPLD reduces board real-estate, improves noise immunity, and is fully reprogrammable via the on-chip IEEE 1149.1 JTAG interface — enabling field upgrades without replacing the device.
おすすめ
DSP and Microcontroller Address Decoding
The 212 I/O pins of the EPM9560GC280-20N allow full address-bus decoding for memory-mapped peripherals in DSP and 32-bit microcontroller systems. Each macrocell contains a programmable AND/OR array with a configurable flip-flop supporting D, T, JK, and SR modes, enabling complex state-machine decode logic with predictable 20 ns tPD. Use it to decode chip-selects for external SRAM, Flash, and peripherals while offloading address-decode logic from the main CPU — improving system throughput and simplifying PCB routing.
おすすめ
Legacy Industrial Control Replacement
The EPM9560GC280-20N's 5.0-V core operation and 4.75-5.25 V supply tolerance make it ideal for replacing obsolete 74-series and PAL-based control logic in industrial automation systems where 5 V rails remain standard. With EEPROM non-volatile storage, the device retains its configuration through power cycles without external boot devices, supporting long-life factory-floor installations. The 280-pin CPGA ceramic package suits legacy through-hole industrial designs and conformal-coated assemblies where surface-mount CPLDs may be unsuitable.
おすすめ
JTAG Boundary-Scan Test Infrastructure
The EPM9560GC280-20N's built-in IEEE Std. 1149.1 JTAG interface allows it to serve as a JTAG chain master or slave in board-level boundary-scan test infrastructure. Use it to chain together multiple JTAG devices for in-system programming and bed-of-nails test access. The 144 MHz counter frequency and predictable timing support high-speed boundary-scan clocking, and the 5.0-V ISP feature enables field firmware updates via the same JTAG port used for production testing — minimizing field-service cost.
おすすめ
Bus Arbitration and DMA Control
The EPM9560GC280-20N's combination of 560 macrocells and 212 I/O pins supports multi-master bus arbitration, DMA handshake logic, and interrupt-priority encoding in shared-bus architectures. Each macrocell's flip-flop operates up to 144 MHz, enabling sub-microsecond arbitration latency for high-throughput systems. Use it to implement round-robin or priority-based arbiters, hand-off FIFOs, and request/grant state machines in backplane designs, multiprocessor systems, or RAID storage controllers — replacing multiple discrete PALs and latches.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560GC280-20N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560GC280-20 | EPM9560GC280-15N | EPM9560GC280-15 | EPM9560ELI84-20 |
|---|---|---|---|---|---|
| Package | 280-pin CPGA | 280-pin CPGA - same | 280-pin CPGA - same | 280-pin CPGA - same | 84-pin PLCC - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Pin-to-Pin Delay (tPD) | 20 ns | 20 ns | 15 ns (-25%) | 15 ns (-25%) | 20 ns |
主な差別化要因
- Pin-to-pin upgrade path to 15 ns speed grade （vs EPM9560GC280-15N)
- Non-volatile EEPROM configuration eliminates boot PROM （vs SRAM-based FPGA alternatives)
- 5.0-V ISP via built-in JTAG （vs Modern MAX II/MAX V CPLDs (3.3 V core))
設計ノート
The EPM9560GC280-20N operates from a single 4.75 V to 5.25 V supply. Per Altera MAX 9000 guidelines, place one 0.1 µF decoupling capacitor per VCC/GND pin pair on the 280-pin CPGA, plus a single 10 µF bulk tantalum capacitor near the device supply pin. ICC rises with output switching frequency — at full 144 MHz counter operation with 50% I/O toggle, expect peak transient currents of several hundred mA. Add bulk capacitance at the board entry point.
For the 280-pin CPGA ceramic package, use a socket or plated-through-hole footprint designed for PGA pin geometry (1.27 mm typical). Maintain continuous ground and power planes on adjacent inner layers for the high-pin-count BGA-style escape routing. JTAG signals (TCK, TMS, TDI, TDO) should be series-terminated with 33 Ω resistors if chain length exceeds 100 mm. Keep the JTAG port accessible at the board edge for ISP programming via the on-chip IEEE 1149.1 interface.
Do not confuse the EPM9560GC280-20N with the EPM9320GC280-20 (320 macrocells, lower density) — same package, different die. Verify the exact Altera ordering code on the top marking before substituting. The 'N' suffix may indicate industrial temperature or lead-free finish per Altera ordering information; consult the datasheet for the specific grade of your part. For legacy designs, confirm supply voltage (5 V) and I/O voltage (3.3 V vs 5 V) match the system before PCB integration.
The 212 user I/O pins of the EPM9560GC280-20N operate at PCI-compliant edge rates. For high-speed outputs above 50 MHz, use series damping resistors (22-33 Ω) to suppress ringing on long PCB traces. Configure I/O standards (3.3 V or 5 V) per the Altera Quartus pin-assignment file before compilation — mixing standards on the same bank can damage the device. The IEEE 1149.1 JTAG pins must remain stable during normal operation; do not use JTAG pins as general-purpose I/O.
コンプライアンス情報
RoHS, REACH, and lead-free status are not stated in the verified web data. The 'N' suffix on the part number may denote a lead-free finish — verify against the manufacturer datasheet ordering information. NRND (Not Recommended for New Designs) per Octopart distributor listing (2026-09-13).
