EPM9560SRC240-15 - MAX 9000 CPLD, 560 Gates, 240-Pin | Intel / Altera
部品番号: EPM9560SRC240-15 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $45 | $45.00 |
| 10 | $38.5 | $385.00 |
| 100 | $31.2 | $3,120.00 |
| 500 | $26.8 | $13,400.00 |
| 1,000 | $22.5 | $22,500.00 |
EPM9560SRC240-15 概要
A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic device that combines multiple PAL/GAL-like macrocells on a single die with an interconnect fabric. The MAX 9000 family sits in the broader taxonomy: programmable logic device (PLD) -> CPLD -> EPLD/CPLD -> high-density programmable logic. CPLDs are characterized by deterministic timing, predictable I/O placement, and zero-configuration EEPROM or EPROM cells, distinguishing them from SRAM-based FPGAs which require a separate boot PROM.
Key specifications of the EPM9560SRC240-15 include 560 usable gates, 16 Logic Array Blocks (LABs), 212 macrocells, and a maximum operating frequency (fMAX) consistent with the 15 ns tPD speed grade. The device operates from a single 5 V supply and is offered in the 240-pin surface-mount RQFP (S-prefix) package, with the RC240 variants being the pin-compatible ceramic PGA/quad equivalents in the same family.
Architecturally, the EPM9560 uses Altera's classic MAX (Multiple Array matriX) architecture with a global interconnect that routes signals between LABs. Each LAB contains 16 macrocells with individual product-term allocation, and the device is in-system programmable (ISP) via a JTAG/IEEE 1149.1 boundary-scan interface. The -15 speed grade denotes 15 ns maximum pin-to-pin delay, making it suitable for 66 MHz-class system bus applications.
Typical applications include 5V glue-logic consolidation, address decoding and bus-interface bridging, peripheral controller replacement (replacing dozens of 74LS/74F TTL devices), industrial control state machines, and telecom backplane glue logic. The instant-on, non-volatile nature of MAX 9000 makes it preferable to SRAM FPGAs in deterministic-startup applications such as military/aerospace and industrial control.
When designing with the EPM9560SRC240-15, note that the device is a legacy mature part. Lead-time and lifecycle status must be verified before new designs, as the part is approaching or has entered NRND/EOL status with major distributors. The S-prefix denotes the surface-mount RQFP variant, while the RC-prefix denotes the pin-compatible ceramic-quad variant.
This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the manufacturer datasheet. The EPM9560SRC240-15 belongs to the EPM9560 family, with speed grades -10, -12, -15, and -20 and package options including RQFP-208, RQFP-240, and PGA-280.
ドロップイン代替品: EPM9560SRC240-15 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560SRC240-15 （同一形状・フットプリント） — 相違点: Package, Macrocells, Device Type, Usable Gates.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560RI240-15
✅ ドロップイン✓ 在庫あり
$23.1 / 個
データシートを見る →EPM9560RI240-15N
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560SRC240-20
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM9560SRC240-12
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM9560SRC240-15 最大定格＆電気的特性
| Family | MAX 9000 |
| Device Type | EPLD / CPLD (Complex Programmable Logic Device) |
| Usable Gates | 560 |
| Logic Array Blocks (LABs) | 16 |
| Macrocells | 212 |
| Speed Grade | -15 (15 ns tPD) |
| Pin-to-Pin Logic Delay (tPD) | 15 ns (max) |
| Supply Voltage (VCC) | 5 V (nominal) |
| Programmability | In-system programmable via IEEE 1149.1 JTAG |
| Non-volatile | Yes (EPROM/EEPROM cells) |
| パッケージ | RQFP-240 (Surface Mount) |
| 実装タイプ | Surface Mount |
| Process Technology | CMOS EPROM |
EPM9560SRC240-15 rqfp-240 (surface mount) ピン配置ガイド
EPM9560SRC240-15 (rqfp-240 (surface mount) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EPM9560SRC240-15.
詳細は データシート をご参照ください。
主な用途
EPM9560SRC240-15 の用途: 6 件s: 5V Glue Logic Consolidation, Address Decoding and Bus Interface Bridging, Industrial Control State Machines, Telecom Backplane Glue Logic, Legacy Peripheral Controller Replacement, Military and Aerospace Deterministic-Start Logic.
5V Glue Logic Consolidation
The EPM9560SRC240-15 consolidates dozens of 74LS/74F/74HC discrete logic ICs into a single 5V CPLD, reducing PCB area and BOM cost in legacy industrial systems. With 560 usable gates, 16 LABs, and 212 macrocells, it has the logic density to absorb wide address decoders, chip-select generators, and bus-interface bridges that previously required multiple TTL packages. The 5V-tolerant I/O and instant-on EPROM cells make it suitable for power-sequenced industrial control boards where 3.3V CPLDs are incompatible. Designers typically target 50-60% macrocell utilization to leave room for ECO changes; the -15 ns speed grade supports up to 66 MHz system bus logic without violating setup/hold margins.
おすすめ
Address Decoding and Bus Interface Bridging
The EPM9560SRC240-15 is well-suited for ISA, VME, and PCI bus address-decoding and protocol-bridging applications thanks to its 16 LABs of combinational logic and 212 macrocells with predictable 15 ns pin-to-pin timing. Each macrocell can implement a wide decode with multiple product terms, replacing dozens of discrete AND/OR gates. The device's deterministic timing allows precise bus-arbiter design without the timing-closure issues common to FPGAs. The 240-pin RQFP package provides 200+ user I/O for wide bus interfaces such as 32-bit address plus 32-bit data plus control signals, all decoded in a single chip.
おすすめ
Industrial Control State Machines
The EPM9560SRC240-15 hosts large Moore/Mealy state machines for industrial machine controllers, replacing microcontroller firmware with deterministic hardware sequencing. With 212 macrocells and 15 ns tPD, complex multi-state sequencers for PLCs, motor controllers, and process-control valves run at full hardware speed without CPU intervention. The non-volatile EPROM cells provide instant-on at power-up, critical for safety interlocks where SRAM-based FPGAs must wait for configuration. Industrial-temp variants like EPM9560RI240-15 are specified for -40C to +85C operation in factory-floor environments.
おすすめ
Telecom Backplane Glue Logic
Telecom backplanes in legacy TDM, ATM, and SONET systems use the EPM9560SRC240-15 for backplane glue logic including clock distribution, bus arbitration, and line-card interface adaptation. The device's 560-gate capacity is ideal for bridging H.110 CT-bus, CompactPCI, and proprietary backplane buses while supporting 5V signaling levels common to telecom equipment. The -15 ns speed grade handles 8 kHz to 8 MHz telephony control signals with margin, and the 240-pin RQFP package enables high-density routing on backplane mezzanine cards. The non-volatile cells eliminate configuration-processor risk during power-cycle events.
おすすめ
Legacy Peripheral Controller Replacement
The EPM9560SRC240-15 is a popular replacement for aging SCSI, GPIB, VMEbus, and proprietary peripheral controllers in test-and-measurement equipment. By implementing the controller as a CPLD rather than discrete logic, designers reduce a $200 worth of 74F/74AS chips to a single $30-$45 part while gaining design flexibility. The 5V tolerance matches legacy peripheral interfaces that have no 3.3V equivalents, and the 15 ns tPD easily meets the 5-10 MHz peripheral bus rates. Designers also use the EPM9560SRC240-15 as a firmware-replacement for obsolete microcontrollers in fielded instruments, with the JTAG ISP interface enabling in-field reprogramming via boundary-scan.
おすすめ
Military and Aerospace Deterministic-Start Logic
The EPM9560SRC240-15 is used in military and aerospace systems where deterministic power-on behavior is required, as its non-volatile EPROM cells start in known state within nanoseconds rather than the milliseconds required by SRAM-based FPGAs. The 240-pin RQFP package is hermetically-sealable and meets the operating-temperature and reliability requirements of DO-254 and MIL-STD-454 designs. With 15 ns tPD, the device handles flight-control bus arbitration and sensor-signal routing without timing ambiguity. For new military programs, however, note that the EPM9560SRC240-15 is NRND and designers should consult Altera/Intel for current MIL-spec-equivalent recommendations.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560SRC240-15 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560RC240-15 | EPM9560RI240-15 | EPM9560SRC240-12 | EPM9560SRC240-20 |
|---|---|---|---|---|---|
| Package | RQFP-240 (Surface Mount) | PGA-240 (ceramic quad) - NOT drop-in footprint | RQFP-240 (Surface Mount) - same | RQFP-240 (Surface Mount) - same | RQFP-240 (Surface Mount) - same |
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Family | MAX 9000 | MAX 9000 - same | MAX 9000 - same | MAX 9000 - same | MAX 9000 - same |
| Speed Grade (tPD max) | 15 ns | 15 ns - identical | 15 ns - identical | 12 ns - faster | 20 ns - slower |
| Usable Gates | 560 | 560 - same | 560 - same | 560 - same | 560 - same |
| Macrocells | 212 | 212 - same | 212 - same | 212 - same | 212 - same |
| Logic Array Blocks | 16 | 16 - same | 16 - same | 16 - same | 16 - same |
主な差別化要因
- Surface-mount RQFP-240 package suitable for modern SMT assembly （vs EPM9560RC240-15)
- Balanced -15 ns speed grade (66 MHz class) （vs EPM9560SRC240-12 and EPM9560SRC240-20)
- Instant-on non-volatile EPROM configuration （vs FPGA alternatives (e.g., Cyclone, Spartan))
設計ノート
The EPM9560SRC240-15 in RQFP-240 package typically dissipates 0.5-1.5 W depending on switching activity. The RQFP package has a relatively high theta-JA (around 30-40 C/W) without forced airflow, so for industrial-temperature applications ensure the PCB thermal design keeps junction temperature below 125C. Estimated: at 1.0 W dissipation and theta-JA = 35 C/W, junction rise above ambient is 35C, so derate for ambient >90C. Add thermal vias under the die-attach pad and provide a minimum 2 oz copper pour for heat spreading.
For the EPM9560SRC240-15 RQFP-240 layout, place 0.1 uF decoupling capacitors as close as possible to every VCC pin, with one bulk 10-47 uF tantalum or ceramic capacitor near the device. The RQFP-240 has fine-pitch (typically 0.5 mm) leads on all four sides; use a 4-layer PCB with dedicated ground and power planes for signal-integrity and to minimize EMI. Provide a clock-distribution trace routed on the inner layer and kept away from I/O edges. JTAG TMS/TCK/TDO/TDI lines should be routed as a group with a 47 ohm series terminator on TCK.
Common design pitfalls for the EPM9560SRC240-15: (1) Mixing up RQFP-240 (SRC prefix, surface-mount) with PGA-240 (RC prefix, ceramic through-hole) - these are NOT footprint-compatible despite the same 240-pin count; (2) Assuming Quartus Prime supports MAX 9000 - it does NOT; you must use legacy MAX+PLUS II software or Quartus version 9.1 or earlier for design entry; (3) Forgetting that the EPM9560 is 5V-only - no 3.3V I/O tolerance; (4) Using the device in new designs without checking NRND/EOL status - it is NRND as of 2026-09-13, so production volumes are limited. Always verify pin-compatibility and timing margins against the latest datasheet revision before committing to a redesign.
コンプライアンス情報
RoHS and lead-free compliance for EPM9560SRC240-15 is [DATA_NEEDED] and not stated in the Verified Web Data. Most legacy 5V CPLDs in RQFP packages predate RoHS mandates. The N-suffix variants (e.g., EPM9560RI240-15N) are typically lead-free; verify with the distributor's Certificate of Compliance before RoHS-critical applications.
