FDMC89521L - Dual N-Channel 60V 8.2A MOSFET | onsemi
部品番号: FDMC89521L ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $1.42 | $1.42 |
| 10 | $1.21 | $12.10 |
| 100 | $0.95 | $95.00 |
| 500 | $0.78 | $390.00 |
| 1,000 | $0.64 | $640.00 |
| 3,000 | $0.52 | $1,560.00 |
FDMC89521L 概要
A dual MOSFET is a semiconductor device that integrates two transistors in a single package, commonly used to build complementary or synchronous switching stages. MOSFET arrays belong to the discrete semiconductor family, branching into power MOSFETs and, more specifically, trench-gate N-channel devices. Within a synchronous buck converter the low-side and high-side FETs sit next to each other on the PCB; a dual-packaged part halves the gate-drive loop and slashes the input-capacitor ripple current. Compared with two single SO-8 MOSFETs, an MLP-8 dual cut PCB area roughly in half and improves thermal spreading.
Key features include 60 V drain-source breakdown, 8.2 A continuous drain current at TA = 25 °C, 17 mΩ Rds(on) at Vgs = 10 V, low gate charge for fast switching, an integrated drain-to-source body diode for inductive commutation, and 1.9 W / 16 W power dissipation ratings at TA = 25 °C and TC = 25 °C respectively. The Power33 package exposes a large metal pad that pulls heat directly into the PCB copper pour.
The FDMC89521L uses onsemi's POWERTRENCH process, a shielded-gate trench technology that reduces on-resistance per unit area while minimizing Miller capacitance. The 17 mΩ Rds(on) is achieved at a relatively low gate charge, allowing the part to switch efficiently at 500 kHz to 1 MHz node-switching frequencies typical of point-of-load converters. The dual-die layout is symmetric so the two FETs share electrical and thermal characteristics, simplifying dual-channel driver designs.
Typical applications include synchronous buck DC-DC converters in telecom and networking equipment, motor-driver H-bridges for small BLDC motors, battery-management load switching, USB Type-C / PD power-path OR-ing, and point-of-load voltage regulator modules. The dual-FET configuration makes it especially useful in any topology where two MOSFETs are mounted next to each other on the same switching node.
When designing with this device, ensure the gate-drive voltage is at least 10 V for full Rds(on) performance. A 4.5 V drive is supported for low-voltage logic-level use but on-resistance roughly doubles. Pay attention to the exposed pad (Pin 1 / EP) - it MUST be soldered to a copper pour of at least 1 sq. inch to achieve the rated 1.9 W TA dissipation.
ドロップイン代替品: FDMC89521L — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: FDMC89521L （同一形状・フットプリント） — 相違点: Configuration, FET Type, MSL Level, Package, Technology.
クイック比較ツール — 並列比較する代替部品を選択:
FDM89521L
✅ ドロップイン📋 参考代替品（カタログ未掲載）
FDMA89521L
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
SI7922DN
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DMN3190LDW-7
✅ ドロップイン✓ 在庫あり
$0.1 / 個
データシートを見る →FDMC89521L 最大定格＆電気的特性
| Manufacturer | onsemi (Fairchild Semiconductor) |
| FET Type | 2 × N-Channel (Dual) |
| Drain-Source Voltage (Vdss) | 60 V |
| Continuous Drain Current (Id) @ TA=25C | 8.2 A |
| On-Resistance Rds(on) @ Vgs=10V | 17 mΩ |
| Gate-Source Voltage (Vgs) | ±20 V |
| Power Dissipation (TA=25C) | 1.9 W |
| Power Dissipation (TC=25C) | 16 W |
| Technology | POWERTRENCH shielded-gate trench MOSFET |
| パッケージ | 8-Power33 (MLP-8 / Power 33, 3 mm × 3 mm) |
| 実装タイプ | Surface Mount |
| 動作温度範囲 | -55C to +150C (Tj) |
| MSLレベル | 1 (per onsemi product page) |
| RoHS ステータス | Compliant |
| Body Diode | Integrated N-channel body diode |
| Configuration | Dual independent drain-source pairs |
FDMC89521L ピン構成
| ピン 1 | S1 — Source of FET1 (also exposed thermal pad) |
| ピン 2 | G1 — Gate of FET1 |
| ピン 3 | S2 — Source of FET2 |
| ピン 4 | G2 — Gate of FET2 |
| ピン 5 | D2 — Drain of FET2 |
| ピン 6 | S2 — Source of FET2 (redundant, connected to pin 3 internally) |
| ピン 7 | D1 — Drain of FET1 |
| ピン 8 | S1 — Source of FET1 (redundant, connected to pin 1 internally) |
Forward-Bias 安全動作領域 (per MOSFET, TA=25C)
主な用途
FDMC89521L の用途: 6 件s: Synchronous Buck DC-DC Converter, BLDC Motor Driver H-Bridge, USB Type-C / Power Delivery Load Switch, Battery Management Load Disconnect, Point-of-Load (POL) Module, Telecom 48 V Hot-Swap / OR-ing.
Synchronous Buck DC-DC Converter
The FDMC89521L excels as the integrated high-side and low-side MOSFET pair in synchronous buck converters for 12 V to 5 V/3.3 V point-of-load rails. Its 60 V Vdss gives ample margin for 24 V industrial buses and telecom intermediate rails, while the dual MLP-8 Power33 package places both FETs in tight proximity - halving the switching-loop area, reducing parasitic inductance, and suppressing voltage overshoot at the switching node. The 17 mΩ Rds(on) at Vgs = 10 V keeps conduction loss low at 8 A continuous load, and the POWERTRENCH process's low Qg enables 500 kHz to 1 MHz switching with acceptable driver losses. The exposed thermal pad pulls heat directly into PCB copper, supporting 1.9 W TA continuous dissipation when a minimum 1 sq-inch copper pour is used.
おすすめ
BLDC Motor Driver H-Bridge
In brushless DC (BLDC) motor drives up to 6 A phase current, the FDMC89521L provides two N-channel MOSFETs that pair up to form half-bridge or full H-bridge legs. The 60 V Vdss supports 24 V battery-fed and 36 V industrial-bus motors, and the 17 mΩ Rds(on) limits I²R losses during PWM commutation at 25 kHz to 100 kHz. Each MOSFET's integrated body diode handles inductive freewheeling during dead-time intervals, simplifying the gate-drive timing and eliminating external Schottky diodes in low-voltage designs. The compact Power33 footprint enables compact motor-driver PCBs for drones, robotics, and small e-mobility platforms where mass and PCB area are at a premium.
おすすめ
USB Type-C / Power Delivery Load Switch
USB Type-C and USB PD source/sink designs use back-to-back N-channel MOSFETs as load switches for Vbus hot-plug, OR-ing, and over-current protection. The FDMC89521L integrates two 60 V N-channel FETs in a 3×3 mm Power33 package, ideal for back-to-back Vbus switching up to 5 V/3 A consumer or 20 V/5 A PD profiles. The 17 mΩ on-resistance keeps voltage drop under 100 mV at full PD current, preserving PD voltage-tolerance budget. The exposed pad sinks heat efficiently when load transients occur, and the dual-FET configuration cuts PCB area versus two discrete DFN1006 or SOT-23 FETs - critical for compact power banks and laptop Type-C receptacles.
おすすめ
Battery Management Load Disconnect
Multi-cell battery packs (2S to 4S Li-ion, 12 V/24 V lead-acid replacements) require dual N-channel MOSFETs for low-side and high-side battery disconnect during over-current, over-temperature, or deep-discharge events. The FDMC89521L's 60 V Vdss covers 4S Li-ion (16.8 V max) with ample transient margin, and the 17 mΩ Rds(on) minimizes quiescent and load current conduction loss. The integrated body diodes enable natural freewheeling during switching transients, while the Power33 package is small enough for hand-held and wearable BMS boards. onsemi's POWERTRENCH technology guarantees consistent gate-threshold voltage for reliable turn-off under low-battery conditions.
おすすめ
Point-of-Load (POL) Module
Compact POL modules for FPGAs, ASICs, and DSPs in telecom and server applications use the FDMC89521L as the synchronous switch pair to step 12 V intermediate bus down to 0.8 V to 3.3 V core voltages. The 17 mΩ Rds(on) at Vgs = 10 V supports 8 A continuous load with minimal conduction loss, and the device's low Qg reduces driver-loss budget at multi-MHz switching frequencies favored by small POL inductors. The dual MLP-8 Power33 package simplifies reflow soldering and improves thermal spreading across the POL board, where every square millimeter counts toward high current density.
おすすめ
Telecom 48 V Hot-Swap / OR-ing
In telecom rectifier and battery-OR-ing circuits operating off a nominal 48 V bus, two N-channel MOSFETs form a high-side or low-side OR-ing switch that selects between redundant -48 V feeds or isolates a battery string. The FDMC89521L's 60 V Vdss rating handles 48 V nominal rails plus transient spikes up to 60 V during hot-plug events. The 17 mΩ Rds(on) minimizes voltage drop on the OR-ing path, and the dual-FET package reduces PCB area versus two discrete SO-8 parts. The exposed Power33 thermal pad conducts heat to the chassis-ground copper pour, keeping Tj within the 150 °C maximum during steady-state conduction.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: FDMC89521L — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | FDM89521L | FDMA89521L | SI7922DN | DMN3190LDW-7 |
|---|---|---|---|---|---|
| Brand | onsemi | onsemi (same) | onsemi (same) | Vishay Intertechnology | Diodes Incorporated |
| Package | Power33 (MLP-8, 3x3 mm) | Power33 (MLP-8, 3x3 mm) - same | Power33 (MLP-8, 3x3 mm) - same | Power33 (MLP-8, 3x3 mm) - same | Power33 (MLP-8, 3x3 mm) - same |
| Drain-Source Voltage (Vdss) | 60 V | 60 V | 60 V | 60 V | 30 V |
| Continuous Drain Current @ TA=25C | 8.2 A | 8.2 A | 8.2 A | 6.5 A | 8.0 A |
| Rds(on) @ Vgs=10V | 17 mΩ | 17 mΩ | 17 mΩ | 25 mΩ | 19 mΩ |
| Technology | POWERTRENCH | POWERTRENCH | POWERTRENCH | TrenchFET | Trench DMOS |
| Automotive Grade (AEC-Q101) | No (industrial/consumer) | No | Yes (AEC-Q101) | No | No |
主な差別化要因
- Higher continuous drain current at TA=25 °C than SI7922DN （vs SI7922DN)
- Higher Vdss rating than DMN3190LDW-7 for 24-48 V bus applications （vs DMN3190LDW-7)
- AEC-Q101 automotive option via FDMA89521L ordering code （vs FDS89521L (SO-8 alternative))
設計ノート
Estimated: at Vgs=10V with Id=8 A the FDMC89521L dissipates I²R = 8² × 0.017 = ~1.09 W per channel. On the standard JEDEC 1 sq-inch 2-oz copper pour the Power33 package hits theta_JA ≈ 50 C/W, producing a Tj rise of ~55 C at TA=25 C. For higher current or higher ambient applications, expand the copper pour to 2-3 sq-inches or use forced-air cooling to keep Tj below 125 C derating threshold.
Per onsemi application guidance, route the high-current switching-node traces between the drain of the high-side FET and source of the low-side FET to a minimum loop area, using 2-oz copper to carry 8 A continuous current with under 10 °C temperature rise. Place gate-drive resistors (10-100 Ω) and the bootstrap capacitor close to the gate and source pins of each MOSFET to minimize parasitic gate-drive inductance. Keep the gate trace away from the drain switching node to avoid Miller-induced turn-on.
The exposed thermal pad (Pin 1) MUST be soldered to the PCB copper pour - skipped solder joints increase thermal resistance by 30-50% and force aggressive Tj derating. Use multiple thermal vias (0.3 mm drill, 1 mm pitch) under the exposed pad to conduct heat into inner copper planes. Place the input ceramic bypass capacitor within 2 mm of the drain pad to suppress high-frequency switching noise.
Do not exceed the ±20 V Vgs absolute-maximum rating: gate-drive voltages above 20 V can permanently damage the gate oxide, especially in noisy switching environments where ringing peaks overshoot the steady-state gate-drive level. Add a gate-source Zener clamp (5.1 V) if ringing is observed, and ensure dead-time in complementary gate-drive circuits prevents shoot-through that could exceed the 16 W TC power-dissipation limit.
コンプライアンス情報
RoHS and lead-free confirmed per onsemi product page. AEC-Q101 grade available via FDMA89521L ordering code (not this exact suffix). Conflict-minerals statement per onsemi corporate policy.
