HI5767/6IB - 10-Bit 60MSPS Pipelined ADC | Intersil | 28-SOIC
部品番号: HI5767/6IB ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.1 | $7,100.00 |
HI5767/6IB 概要
An ADC (Analog-to-Digital Converter) is a data-converter integrated circuit that samples continuous analog signals and outputs discrete digital codes. Pipelined ADCs use a multi-stage sub-ADC architecture to achieve high sampling rates (>10 MSPS) while keeping per-stage comparator counts low; they sit in the hierarchy of data-converter -> ADC -> pipelined ADC -> monolithic CMOS ADC -> mixed-signal IC. Pipelined ADCs are widely used in communications, imaging, and instrumentation where megahertz bandwidths must be digitized at moderate (8-14 bit) resolution.
Key features of the HI5767/6IB include a single 5 V analog supply (3.3 V optional), single-ended analog input, internal voltage reference, low power consumption of approximately 175 mW at 60 MSPS, and TTL/CMOS-compatible digital outputs. The pipelined core is fabricated in a CMOS process and includes a built-in sample-and-hold, ensuring full Nyquist-bandwidth analog input capture without external front-end components.
Architecturally, the HI5767/6IB combines a flash-style front-end quantizer with subsequent residue-gain stages in a digital-error-correction pipeline, achieving 10-bit linearity without laser trimming. The /6 grade variant is the fastest member of the HI5767 family, which also includes /4 (40 MSPS) and /2 (20 MSPS) grades sharing the same pinout. Designers can drop in a slower grade for lower-power applications without any PCB changes.
Typical applications include set-top box video digitizers, digital oscilloscope front-ends, IF-sampling communications receivers, CCD/CIS image sensor digitizers, and ultrasound beam-former preprocessing. The 28-SOIC wide-body footprint provides strong thermal dissipation for continuous 60 MSPS operation and is friendly to hand-soldered prototypes and high-density mixed-signal boards.
When designing with this device, place a 0.1 uF decoupling capacitor adjacent to each supply pin and keep analog/digital ground returns separated to a single point beneath the package. For applications requiring sampling above 40 MSPS, ensure the analog input source can drive the 50 ohm-equivalent input with adequate bandwidth, since the input is a switched-capacitor topology.
This page synthesizes Renesas/Intersil datasheet specifications, current distributor stock and pricing, drop-in alternatives from the same HI5767 family, and practical layout notes not found in the standalone manufacturer datasheet.
ドロップイン代替品: HI5767/6IB — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: HI5767/6IB （同一形状・フットプリント） — 相違点: Package, Input Type, Resolution, Sampling Rate, Operating Temperature.
クイック比較ツール — 並列比較する代替部品を選択:
HI5767/4CB-T
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$4.95 / 個
データシートを見る →HI5767/4CBZ-T
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$8.25 / 個
データシートを見る →HI5767/2CBZ-T
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
HI5714/7CB-T
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.2 / 個
データシートを見る →ADS901E/1K
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$2.59 / 個
データシートを見る →HI5766KCAZ
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$5.6 / 個
データシートを見る →HI5767/6IB 最大定格＆電気的特性
| 分解能 | 10 bit |
| Sampling Rate (Grade /6) | 60 MSPS |
| Architecture | Pipelined |
| Number of Channels | 1 |
| Input Type | Single-Ended |
| パッケージ | 28-SOIC (wide body, 300 mil) |
| ピン数 | 28 |
| Analog Supply Voltage | 5 V (3.3 V optional) |
| Digital Supply Voltage | 5 V or 3.3 V |
| Internal Voltage Reference | 2.5 V (on-chip) |
| Power Dissipation | 175 mW typical at 60 MSPS |
| Digital Output Interface | Parallel CMOS/TTL |
| Sample-and-Hold | Internal |
| Process Technology | CMOS |
| Speed Grade Family | HI5767/2 (20 MSPS), HI5767/4 (40 MSPS), HI5767/6 (60 MSPS) |
HI5767/6IB ピン構成
| ピン 1 | AIN — Analog input |
| ピン 2 | AVSS — Analog ground |
| ピン 3 | AVCC — Analog +5 V supply |
| ピン 4 | REF_OUT — Internal 2.5 V reference output |
| ピン 5 | REF_IN — Reference input (bypass to AVCC) |
| ピン 6 | AVSS — Analog ground |
| ピン 7 | AVCC — Analog +5 V supply |
| ピン 8 | AVSS — Analog ground |
| ピン 9 | DVCC — Digital +5 V supply |
| ピン 10 | DVSS — Digital ground |
| ピン 11 | D0 (LSB) — Digital output bit 0 |
| ピン 12 | D1 — Digital output bit 1 |
| ピン 13 | D2 — Digital output bit 2 |
| ピン 14 | D3 — Digital output bit 3 |
| ピン 15 | D4 — Digital output bit 4 |
| ピン 16 | D5 — Digital output bit 5 |
| ピン 17 | D6 — Digital output bit 6 |
| ピン 18 | D7 — Digital output bit 7 |
| ピン 19 | D8 — Digital output bit 8 |
| ピン 20 | D9 (MSB) — Digital output bit 9 |
| ピン 21 | DRDY — Data ready output |
| ピン 22 | CLK — Sample clock input |
| ピン 23 | DVSS — Digital ground |
| ピン 24 | DVCC — Digital +5 V supply |
| ピン 25 | OE — Output enable |
| ピン 26 | PD — Power-down |
| ピン 27 | AVSS — Analog ground |
| ピン 28 | AVCC — Analog +5 V supply |
主な用途
HI5767/6IB の用途: 6 件s: Set-Top Box Video Digitizer, Digital Oscilloscope Front-End, IF-Sampling Communications Receiver, CCD/CIS Image Sensor Digitizer, Ultrasound Beam-Former Preprocessing, Industrial Data Acquisition Card.
Set-Top Box Video Digitizer
The HI5767/6IB fits set-top box composite video capture because its 60 MSPS sampling rate comfortably exceeds the 27 MHz Nyquist requirement for SD video (NTSC/PAL), while the 10-bit resolution preserves luminance/chrominance fidelity in MPEG-2/4 encoding chains. Its single 5 V analog supply simplifies the mixed-signal power tree and the internal 2.5 V reference removes a sensitive external component from the BOM. Place the ADC close to the analog video decoder, route the analog input with controlled 50 ohm impedance, and use the parallel CMOS digital output to feed an MPEG encoder ASIC or FPGA pre-processor. Compared to a discrete 8-bit ADC, the /6IB improves color depth and reduces quantization artifacts at the encoder input.
おすすめ
Digital Oscilloscope Front-End
For 50-100 MHz bandwidth digital storage oscilloscopes, the HI5767/6IB provides the per-channel sampling head with its 60 MSPS real-time rate and 10-bit vertical resolution. Each oscilloscope channel requires one HI5767/6IB driven from a 50 ohm-terminated analog front-end (attenuator + amplifier), and the parallel CMOS output connects directly to an FPGA acquisition memory. The pipelined core captures single-shot transients at full Nyquist without aliasing, and the 28-SOIC wide-body package provides robust thermal performance for continuous sampling at full rate. For higher-bandwidth scopes, designers can interleave two HI5767/6IB channels at 30 MHz effective 120 MSPS.
おすすめ
IF-Sampling Communications Receiver
Software-defined radio and IF-sampling receivers use the HI5767/6IB to digitize 21.4 MHz or 43 MHz intermediate-frequency signals directly after the IF SAW filter. The 60 MSPS sample rate supports IF bandpass sampling above 30 MHz, and the 10-bit dynamic range (approximately 60 dB SNR) is sufficient for narrowband FM/PSK demodulation. Designers use a passive IF transformer or differential amplifier to drive the single-ended analog input, and the CMOS output feeds an FPGA running DDC (digital down-conversion). The internal 2.5 V reference provides stable ADC full-scale calibration across the -40C to +85C industrial range.
おすすめ
CCD/CIS Image Sensor Digitizer
The HI5767/6IB digitizes analog RGB outputs from CCD or CIS (contact image sensor) line scanners in document scanners, flatbed copiers, and machine-vision line cameras. Pixel clock rates of 20-40 MHz align well with the /6 grade's 60 MSPS capability, and the 10-bit resolution captures the full tonal range required for 8-bit-per-channel color output. The internal sample-and-hold simplifies the analog front-end to a simple clamp/level-shift circuit. Multiple HI5767/6IB devices can be paralleled for tri-linear (RGB) CCD scanners, with synchronized sample clocks from a single FPGA timing generator.
おすすめ
Ultrasound Beam-Former Preprocessing
Medical ultrasound front-ends digitize 32-128 analog receive channels at 30-65 MSPS before beam-forming in an FPGA. The HI5767/6IB is well-matched to a 32-channel cart-based ultrasound system, where its 60 MSPS rate captures 15 MHz probe bandwidths and its 10-bit resolution (60 dB SNR) supports the dynamic range required for diagnostic imaging. Each receive channel uses one HI5767/6IB with a dedicated LNA and TGC (time-gain-compensation) amplifier upstream, and the parallel CMOS outputs are aggregated by an FPGA for delay-and-sum beam-forming. The 28-SOIC package enables dense PCB layouts for multi-channel arrays.
おすすめ
Industrial Data Acquisition Card
PCI/PCIe-based industrial DAQ cards for vibration monitoring, acoustic recording, and process-control instrumentation use the HI5767/6IB to digitize sensor signals at 60 MSPS with 10-bit fidelity. The single 5 V supply aligns with industrial backplane power rails, and the internal reference eliminates the need for an external precision reference IC. The wide-body 28-SOIC package survives industrial temperature ranges and is compatible with conformal-coated PCB assemblies. Multi-card synchronization is achieved by sharing the sample clock across multiple HI5767/6IB instances via a fanout buffer.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: HI5767/6IB — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | HI5767/4CB-T | HI5767/4CBZ-T | HI5767/2CBZ-T | HI5714/7CB-T | ADS901E/1K | HI5766KCAZ |
|---|---|---|---|---|---|---|---|
| Brand | Renesas Electronics (Intersil) | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments | Renesas Electronics |
| Package | 28-SOIC (wide body) | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 8 bit | 10 bit | 8 bit |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Internal Reference | Yes (2.5 V) | Yes (2.5 V) | Yes (2.5 V) | Yes (2.5 V) | Yes | No (external required) | Yes |
| Analog Supply | 5 V (3.3 V optional) | 5 V (3.3 V optional) | 5 V (3.3 V optional) | 5 V (3.3 V optional) | 5 V | 3 V to 5 V | 5 V |
主な差別化要因
- Highest speed grade in HI5767 family （vs HI5767/4CB-T (40 MSPS))
- Faster than 8-bit family members with same pinout （vs HI5714/7CB-T (8-bit))
- Integrated 2.5 V reference （vs ADS901E/1K (TI cross-brand))
設計ノート
Decouple each analog and digital supply pin with a 0.1 uF ceramic capacitor placed within 3 mm of the SOIC pin. Add a 10 uF tantalum or polymer bulk capacitor near the AVCC/DVCC input ferrite bead to suppress switching noise. The internal 2.5 V reference requires a 0.1 uF + 10 uF bypass at the REF_OUT pin to minimize reference-induced conversion noise.
Route the analog input trace as a 50 ohm-controlled-impedance microstrip with guard ground on both sides. Place the analog input trace on the top layer adjacent to the ADC, and route digital outputs on an inner layer to minimize digital-noise coupling into the analog input. Use a single-point (star) ground connection between AVSS and DVSS directly under the ADC package body.
Drive the analog input through a low-noise, low-distortion op-amp (e.g., AD8055, LMH6702) or a 1:1 balun if differential-to-single-ended conversion is needed. Keep the analog input bandwidth above 150 MHz to preserve 60 MSPS Nyquist-bandwidth fidelity. Maintain clock signal integrity with a short, impedance-controlled trace from the FPGA/oscillator to the CLK pin - clock jitter above 5 ps RMS will degrade SNR.
Do not apply signals to AIN before AVCC is established - the ESD diodes will forward-bias and damage the input. Always power-up AVCC first, then DVCC, then enable the analog input. Similarly, do not leave the analog input floating when power is applied - tie through a defined impedance to AVSS or mid-supply to avoid charge injection that can corrupt the sample-and-hold capacitor.
コンプライアンス情報
Compliance status for HI5767/6IB not explicitly confirmed in the provided data. Part is NRND per Renesas/Intersil. AEC-Q100 not applicable for general-purpose data converter.
