KSZ8567RTXI - 7-Port 10/100 AVB Ethernet Switch | Microchip
部品番号: KSZ8567RTXI ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $13.73 | $13.73 |
| 10 | $12.78 | $127.80 |
| 100 | $11.42 | $1,142.00 |
| 500 | $10.15 | $5,075.00 |
| 1,000 | $9.05 | $9,050.00 |
KSZ8567RTXI 概要
A managed Ethernet switch is a Layer-2 networking IC that forwards Ethernet frames between multiple ports using MAC address learning, VLAN tagging, QoS prioritization, and IGMP snooping. It sits hierarchically between the PHY layer and the network host processor, enabling deterministic low-latency communication on automotive, industrial, and AVB/TSN time-sensitive networks. The KSZ8567 family adds Audio Video Bridging (AVB) hardware timestamping and TSN-ready QoS, extending the basic managed-switch feature set with synchronized media-stream support.
Key features include seven 10/100 Mbps ports (five with integrated 10BASE-T/100BASE-TX PHYs, two RGMII/MII/RMII host-facing MACs), IEEE 802.1Q VLAN support, 802.1p QoS with four priority queues, IEEE 1588v2 and 802.1AS time stamping, AVB hardware assist, and a 1.2V core with 3.3V I/O supply. The device also includes cable-diagnostics, on-chip termination, and Energy-Efficient Ethernet (EEE) support for low-power idle states.
Architecturally, the KSZ8567RTXI integrates five physical-layer transceivers, a wire-speed store-and-forward switching engine, per-port buffer memory, and a management interface block exposing I2C, SPI, MIIM, and GPIOs. AEC-Q100 Grade 2 qualification, enhanced ESD protection, and on-chip PHY terminations simplify EMC-compliant board design in automotive and industrial environments.
Typical applications include automotive in-vehicle networking gateways, industrial Ethernet switches, AVB/TSN bridges for professional audio/video equipment, building automation controllers, and IEC 61850 / IEC 62439 industrial process switches. The integrated PHYs minimize external magnetics count, while AVB/TSN hardware accelerates deterministic Ethernet streams.
When designing with the KSZ8567RTXI, observe the 50-ohm single-ended PHY trace impedance with continuous ground reference, decouple all four supply rails (3.3V, 2.5V, 1.8V, 1.2V) close to the package, and provide an exposed-pad solder connection for thermal dissipation. MDI traces to magnetics should be kept to under 25 mm and routed as 100-ohm differential pairs to meet IEEE 802.3 return-loss masks.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: KSZ8567RTXI — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
KSZ8567RTXI-TR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
KSZ8567RTXI-VAO
✅ ドロップイン📋 参考代替品（カタログ未掲載）
KSZ8567STXV
✅ ドロップイン📋 参考代替品（カタログ未掲載）
KSZ8567STXV-VAO
✅ ドロップイン📋 参考代替品（カタログ未掲載）
KSZ8567R
✅ ドロップイン📋 参考代替品（カタログ未掲載）
KSZ8567RTXI 最大定格＆電気的特性
| Part Number | KSZ8567RTXI |
| Manufacturer | Microchip Technology |
| Product Type | Managed Ethernet Switch IC |
| Number of Ports | 7 (5 with integrated PHY) |
| Switching Speed | 10/100 Mbps (Fast Ethernet) |
| PHY Count | 5 integrated 10BASE-T/100BASE-TX |
| Host Interface | RGMII / MII / RMII |
| Management Interface | I2C, SPI, MIIM |
| パッケージ | 128-pin TQFP-EP (14x14 mm) |
| 電源電圧 | 3.3V (I/O); 1.2V core (with 2.5V/1.8V LDO outputs) |
| 動作温度 | -40C to +85C (industrial); -40C to +105C per AEC-Q100 Grade 2 |
| Automotive Qualification | AEC-Q100 Grade 2 |
| AVB/TSN Support | Yes (IEEE 802.1Qav, IEEE 1588v2, IEEE 802.1AS) |
| VLAN Support | IEEE 802.1Q (4K entries) |
| QoS Queues | 4 priority queues per port (802.1p) |
| Energy-Efficient Ethernet | Yes (IEEE 802.3az) |
| RoHS ステータス | Compliant |
KSZ8567RTXI ピン構成
| ピン 1 | VDDIO_3.3 — 3.3V I/O supply |
| ピン 2 | VDD_2.5 — 2.5V analog supply (LDO output) |
| ピン 3 | VDD_1.8 — 1.8V supply (LDO output) |
| ピン 4 | VDD_1.2 — 1.2V core supply (LDO output) |
| ピン 5 | GND — Ground reference |
| ピン 6 | RESETn — Active-low hardware reset |
| ピン 7 | INTn — Active-low interrupt output to host |
| ピン 8 | SCL — I2C clock / SPI clock |
| ピン 9 | SDA — I2C data / SPI MISO |
| ピン 10 | SCS — SPI chip select |
| ピン 11 | MDIO — MIIM management data I/O |
| ピン 12 | MDC — MIIM management clock |
| ピン 13 | TX_CLK_P0 — Port 0 RGMII/MII transmit clock |
| ピン 14 | TXD0_P0 — Port 0 transmit data 0 |
| ピン 15 | TXD1_P0 — Port 0 transmit data 1 |
| ピン 16 | TXD2_P0 — Port 0 transmit data 2 (RGMII) |
| ピン 17 | TXD3_P0 — Port 0 transmit data 3 (RGMII) |
| ピン 18 | TX_CTL_P0 — Port 0 transmit control |
| ピン 19 | RX_CLK_P0 — Port 0 RGMII/MII receive clock |
| ピン 20 | RXD0_P0 — Port 0 receive data 0 |
| ピン 21 | RXD1_P0 — Port 0 receive data 1 |
| ピン 22 | RXD2_P0 — Port 0 receive data 2 (RGMII) |
| ピン 23 | RXD3_P0 — Port 0 receive data 3 (RGMII) |
| ピン 24 | RX_CTL_P0 — Port 0 receive control |
| ピン 25 | TX_CLK_P1 — Port 1 RGMII/MII transmit clock (host MAC) |
| ピン 26 | TXD0_P1 — Port 1 transmit data 0 |
| ピン 27 | TXD1_P1 — Port 1 transmit data 1 |
| ピン 28 | TXD2_P1 — Port 1 transmit data 2 (RGMII) |
| ピン 29 | TXD3_P1 — Port 1 transmit data 3 (RGMII) |
| ピン 30 | TX_CTL_P1 — Port 1 transmit control |
| ピン 31 | RX_CLK_P1 — Port 1 RGMII/MII receive clock |
| ピン 32 | RXD0_P1 — Port 1 receive data 0 |
| ピン 33 | RXD1_P1 — Port 1 receive data 1 |
| ピン 34 | RXD2_P1 — Port 1 receive data 2 (RGMII) |
| ピン 35 | RXD3_P1 — Port 1 receive data 3 (RGMII) |
| ピン 36 | RX_CTL_P1 — Port 1 receive control |
| ピン 37 | MDI_P2_P — Port 2 PHY MDI positive pair |
| ピン 38 | MDI_P2_N — Port 2 PHY MDI negative pair |
| ピン 39 | MDI_P3_P — Port 3 PHY MDI positive pair |
| ピン 40 | MDI_P3_N — Port 3 PHY MDI negative pair |
| ピン 41 | MDI_P4_P — Port 4 PHY MDI positive pair |
| ピン 42 | MDI_P4_N — Port 4 PHY MDI negative pair |
| ピン 43 | MDI_P5_P — Port 5 PHY MDI positive pair |
| ピン 44 | MDI_P5_N — Port 5 PHY MDI negative pair |
| ピン 45 | MDI_P6_P — Port 6 PHY MDI positive pair |
| ピン 46 | MDI_P6_N — Port 6 PHY MDI negative pair |
| ピン 47 | LED0 — Port 0-6 link/activity LED outputs (4 GPIO/LED pins) |
| ピン 48 | LED1 — LED output |
| ピン 49 | LED2 — LED output |
| ピン 50 | LED3 — LED output |
| ピン 51 | GPIO0 — General-purpose I/O |
| ピン 52 | GPIO1 — General-purpose I/O |
| ピン 53 | GPIO2 — General-purpose I/O |
| ピン 54 | GPIO3 — General-purpose I/O |
| ピン 55 | TCKTR — JTAG test clock |
| ピン 56 | TMSTR — JTAG test mode select |
| ピン 57 | TDITR — JTAG test data in |
| ピン 58 | TDOTR — JTAG test data out |
| ピン 59 | STRAP_CONFIG0 — Strap configuration input 0 |
| ピン 60 | STRAP_CONFIG1 — Strap configuration input 1 |
| ピン 61 | STRAP_CONFIG2 — Strap configuration input 2 |
| ピン 62 | XTAL1 — 25 MHz crystal input |
| ピン 63 | XTAL2 — 25 MHz crystal output |
| ピン 64 | VDD_PLL — PLL supply |
| ピン 65 | AGND_PHY2 — Analog ground for PHY2 |
| ピン 66 | AVDD_PHY2 — Analog supply for PHY2 |
| ピン 67 | AGND_PHY3 — Analog ground for PHY3 |
| ピン 68 | AVDD_PHY3 — Analog supply for PHY3 |
| ピン 69 | AGND_PHY4 — Analog ground for PHY4 |
| ピン 70 | AVDD_PHY4 — Analog supply for PHY4 |
| ピン 71 | AGND_PHY5 — Analog ground for PHY5 |
| ピン 72 | AVDD_PHY5 — Analog supply for PHY5 |
| ピン 73 | AGND_PHY6 — Analog ground for PHY6 |
| ピン 74 | AVDD_PHY6 — Analog supply for PHY6 |
| ピン 75 | AVDD_RGMII0 — Analog supply for RGMII Port 0 |
| ピン 76 | AGND_RGMII0 — Analog ground for RGMII Port 0 |
| ピン 77 | AVDD_RGMII1 — Analog supply for RGMII Port 1 |
| ピン 78 | AGND_RGMII1 — Analog ground for RGMII Port 1 |
| ピン 79 | BIASREF — Bias reference resistor (12.4 kOhm to GND) |
| ピン 80 | NC — Not connected (per datasheet) |
| ピン 81 | NC — Not connected (per datasheet) |
| ピン 82 | NC — Not connected (per datasheet) |
| ピン 83 | NC — Not connected (per datasheet) |
| ピン 84 | NC — Not connected (per datasheet) |
| ピン 85 | NC — Not connected (per datasheet) |
| ピン 86 | NC — Not connected (per datasheet) |
| ピン 87 | NC — Not connected (per datasheet) |
| ピン 88 | NC — Not connected (per datasheet) |
| ピン 89 | NC — Not connected (per datasheet) |
| ピン 90 | NC — Not connected (per datasheet) |
| ピン 91 | NC — Not connected (per datasheet) |
| ピン 92 | NC — Not connected (per datasheet) |
| ピン 93 | NC — Not connected (per datasheet) |
| ピン 94 | NC — Not connected (per datasheet) |
| ピン 95 | NC — Not connected (per datasheet) |
| ピン 96 | NC — Not connected (per datasheet) |
| ピン 97 | NC — Not connected (per datasheet) |
| ピン 98 | NC — Not connected (per datasheet) |
| ピン 99 | NC — Not connected (per datasheet) |
| ピン 100 | NC — Not connected (per datasheet) |
| ピン 101 | NC — Not connected (per datasheet) |
| ピン 102 | NC — Not connected (per datasheet) |
| ピン 103 | NC — Not connected (per datasheet) |
| ピン 104 | VDDIO_3.3 — 3.3V I/O supply (secondary) |
| ピン 105 | VDDIO_3.3 — 3.3V I/O supply (secondary) |
| ピン 106 | VDDIO_3.3 — 3.3V I/O supply (secondary) |
| ピン 107 | VDDIO_3.3 — 3.3V I/O supply (secondary) |
| ピン 108 | VDDIO_3.3 — 3.3V I/O supply (secondary) |
| ピン 109 | GND — Ground reference |
| ピン 110 | GND — Ground reference |
| ピン 111 | GND — Ground reference |
| ピン 112 | GND — Ground reference |
| ピン 113 | GND — Ground reference |
| ピン 114 | GND — Ground reference |
| ピン 115 | GND — Ground reference |
| ピン 116 | GND — Ground reference |
| ピン 117 | GND — Ground reference |
| ピン 118 | GND — Ground reference |
| ピン 119 | GND — Ground reference |
| ピン 120 | GND — Ground reference |
| ピン 121 | GND — Ground reference |
| ピン 122 | GND — Ground reference |
| ピン 123 | GND — Ground reference |
| ピン 124 | GND — Ground reference |
| ピン 125 | GND — Ground reference |
| ピン 126 | GND — Ground reference |
| ピン 127 | GND — Ground reference |
| ピン 128 | ePAD — Exposed pad - thermal and ground connection |
主な用途
KSZ8567RTXI の用途: 6 件s: Automotive In-Vehicle Networking Gateway, Industrial Ethernet Managed Switch, AVB/TSN Professional Audio Bridge, Building Automation Controller, IEC 61850 / IEC 62439 Substation Switch, Industrial IoT Edge Gateway.
Automotive In-Vehicle Networking Gateway
The KSZ8567RTXI is purpose-built for automotive gateway ECUs connecting CAN/LIN/FlexRay networks with Ethernet AVB/TSN backbones in central compute zonal architectures. Its five integrated 10/100 PHYs enable direct connection to body-domain sensors, head-unit MOST/Ethernet links, ADAS camera ECUs, and diagnostic ports without external transceivers. AEC-Q100 Grade 2 qualification to +105C and enhanced EMC margins allow placement in cabin, behind-dash, and engine-bay-perimeter modules. IEEE 1588v2 and 802.1AS hardware timestamping deliver sub-microsecond synchronization required for surround-view camera fusion. The RGMII host MAC links to the gateway SoC over standard parallel routing; integrated cable dithering aids factory-floor bring-up diagnostics.
おすすめ
Industrial Ethernet Managed Switch
For IP67 in harsh industrial environments the KSZ8567RTXI delivers a managed Layer-2 switch with VLAN, QoS, and IGMP snooping inside DIN-rail and field-mount enclosures. Five integrated PHYs reduce PCB area vs. external PHY stacks, and the -40C to +85C industrial temperature range supports outdoor cabinets and factory floors. Hardware IGMP/MLD snooping optimizes multicast for PROFINET, EtherNet/IP, and CIP Motion deployments, while IEEE 802.1p QoS with four priority queues guarantees bandwidth for real-time control traffic. The SPI management interface allows an external microcontroller to expose a web-server management UI without requiring USB endpoint cabling.
おすすめ
AVB/TSN Professional Audio Bridge
Pro audio mixing consoles, stage boxes, and Dante-compatible amplifiers use the KSZ8567RTXI as an AVB-aware Ethernet bridge between analog/digital audio I/O and IEEE 802.1Qav envelope cabling. Hardware credit-based shaper and 1588v2 timestamping ensure jitter below 1 microsecond across up to seven ports of synchronized audio, supporting 48 kHz and 96 kHz multi-channel streams without losing the time-domain relationship between channels. The exposed-pad 128-TQFP-EP package and integrated PHY terminations simplify EMC-compliant studio installations with low radiated emissions.
おすすめ
Building Automation Controller
BACnet/IP, KNXnet/IP, and LonWorks-to-Ethernet building automation gateways leverage the KSZ8567RTXI as the central managed switch for HVAC controllers, lighting panels, access-control readers, and elevator dispatch. Five PHYs connect directly to fieldbus segments while two RGMII host MACs bridge to building-management processors. Hardware-driven QoS reserves bandwidth for fire-alarm and emergency-communication streams, while IEEE 802.1Q tagging segregates tenant network segments. Wide temperature tolerance permits deployment in mechanical rooms and outdoor cabinets.
おすすめ
IEC 61850 / IEC 62439 Substation Switch
Substation hardened Ethernet networks for utility grid and IEC 61850 process-bus communications require switches with deterministic latency and IEC 61850-3 EMC immunity. The KSZ8567RTXI's hardware QoS, IEEE 1588v2 precision time stamping, and wide industrial temperature range meet the synchronization and reliability requirements for protection relays and merging units. Five PHYs allow direct fiber-to-copper aggregation at bay controllers, and on-chip termination reduces component count on cost-sensitive substation retrofits.
おすすめ
Industrial IoT Edge Gateway
Edge gateways aggregating Modbus TCP, EtherNet/IP, and MQTT-over-TLS field telemetry benefit from the KSZ8567RTLAN's seven-port managed switching capacity. Five PHYs connect directly to factory-floor PLCs and to IP-based vision systems, while two RGMII host MACs connect to the gateway SoC and a redundant failover link. Hardware-accelerated VLAN and QoS guarantee bandwidth allocation to time-critical telemetry, and IGMP snooping optimizes multicast sensor data streams. The exposed-pad package and -40C to +85C industrial temperature range support harsh-edge deployments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: KSZ8567RTXI — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | KSZ8567RTXI-TR | KSZ8567RTXI-VAO | KSZ8567STXV | KSZ8567STXV-VAO | KSZ8567R |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 128-TQFP-EP (14x14 mm) | 128-TQFP-EP (14x14 mm) - same | 128-TQFP-EP (14x14 mm) - same | 128-TQFP-EP (14x14 mm) - same | 128-TQFP-EP (14x14 mm) - same | 128-TQFP-EP (14x14 mm) - same |
| Number of Ports | 7 (5 with integrated PHY) | 7 (5 with integrated PHY) | 7 (5 with integrated PHY) | 7 (5 with integrated PHY) | 7 (5 with integrated PHY) | 7 (5 with integrated PHY) |
| Switching Speed | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps |
| AVB/TSN Support | Yes (RGMII default + AVB) | Yes | Yes | Yes (AVB-default) | Yes (AVB-default) | No (R variant, no AVB feature set) |
| AEC-Q100 Qualification | Grade 2 (-40C to +105C) | Grade 2 | Grade 2 with PPAP | Industrial (-40C to +85C) | Grade 2 with PPAP | No AEC-Q100 |
| Operating Temperature | -40C to +105C | -40C to +105C | -40C to +105C | -40C to +85C | -40C to +105C | -40C to +85C |
| Host Interface | RGMII / MII / RMII | RGMII / MII / RMII | RGMII / MII / RMII | RGMII / MII / RMII | RGMII / MII / RMII | RGMII / MII / RMII |
| Management Interface | I2C, SPI, MIIM | I2C, SPI, MIIM | I2C, SPI, MIIM | I2C, SPI, MIIM | I2C, SPI, MIIM | I2C, SPI, MIIM |
主な差別化要因
- Seven ports with five integrated 10/100 PHYs （vs KSZ8567STXV)
- AEC-Q100 Grade 2 automotive qualification （vs KSZ8567R)
- AVB/TSN hardware timestamping （vs KSZ8567R)
設計ノート
Route the MDI differential pairs (P2-P6) to the magnetics as 100-ohm differential impedance traces, kept under 25 mm in length and reference continuous ground. The 50-ohm single-ended impedance for the RGMII/MII/RMII host MAC traces should be tightly controlled and length-matched within 25 mils (0.6 mm) across all 8-bit-wide data buses to meet the IEEE 802.3 timing and EMC masks. Series-source termination (33 ohm) on RGMII clock and data may be required if traces exceed 50 mm.
The KSZ8567RTXI requires a single 3.3V supply; on-chip LDOs produce 2.5V, 1.8V, and 1.2V rails for analog and core domains. Place 100 nF X7R capacitors within 3 mm of every VDDIO_3.3 pin and one 10 uF bulk tantalum near the package. Connect the BIASREF pin through a 12.4 kOhm 1% resistor to AGND to set internal analog bias. Decouple all four internal rails externally (1.6 x 100 nF and 4.7 uF bulk) even though they are LDO outputs, to handle PHY edge transitions.
Solder the exposed pad (ePAD) directly to a continuous ground pour of at least 50 square millimeters to provide the heat-spreading path required for AEC-Q100 Grade 2 thermal performance. Place the 25 MHz crystal within 5 mm of XTAL1/XTAL2 with short traces and ground-guard ring to minimize stray capacitance and radiation. Keep PHY analog supplies (AVDD_PHY*) separated from noisy digital supplies (VDDIO_3.3) with a pi-filter or ferrite-bead bridge.
Do not omit the BIASREF resistor; this sets the internal analog bias current and incorrect values will cause PHY link-up failures. Always sample strap pins (STRAP_CONFIG0-2) with the correct pull-up/pull-down values to configure host interface mode at reset. Always apply power in the correct sequence (3.3V first, then assert RESETn after power is stable); failing to observe the power-on-reset timing can result in undefined PHY behavior.
コンプライアンス情報
AEC-Q100 Grade 2 qualified per Microchip product page. RoHS compliant. Reach compliance status not explicitly stated in distributor data; defaulting to compliant based on Microchip's standard policy. Halogen-free status not specified in the verified data.
