LTC2270CUP - 16-Bit 20Msps Dual ADC | Analog Devices
部品番号: LTC2270CUP ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $110.5 | $110.50 |
| 10 | $102 | $1,020.00 |
| 100 | $95.4 | $9,540.00 |
| 500 | $90.1 | $45,050.00 |
| 1,000 | $82.93 | $82,930.00 |
LTC2270CUP 概要
An ADC (analog-to-digital converter) is a semiconductor device that converts real-world analog signals into discrete digital codes for downstream processing by DSPs, FPGAs, or microcontrollers. Within the signal chain hierarchy (sensor -> analog front end -> ADC -> DSP/FPGA -> actuator), the dual-channel 16-bit 20 Msps ADC occupies the bridge between the analog conditioning stage and digital processing. Pipelined ADCs such as the LTC2270CUP are favored for communications, IF-sampling, and instrumentation because they combine high sampling rates with resolutions above 14 bits, while successive-approximation ADCs serve lower-speed precision roles and delta-sigma ADCs serve high-resolution DC/low-bandwidth tasks.
Key features of the LTC2270CUP include 84.1 dB SNR and 99 dBc SFDR at 5 MHz input, an internal bandgap reference (or optional external reference), programmable gain from 0.5 dB to 1.5 dB in 0.5 dB steps, and a low-latency digital interface that latches each conversion on a single output clock rising edge. The differential inputs ease board-level EMI rejection, and the QFN-64 EP package offers a thermal resistance that supports full-rate operation across the 0 C to 70 C commercial range without external heatsinking.
In terms of architecture, two matched pipelined ADC cores share a single low-jitter clock distribution network and a common reference, ensuring that channel-to-channel gain, offset, and timing mismatches remain below the noise floor. This tracking is essential for diversity receivers, I/Q demodulation, and any system where correlated dual-channel acquisition is required (for example, quadrature sampling of complex baseband signals). The pipelined core provides digital error correction per stage and outputs true 16-bit data with no missing codes at room temperature.
Typical applications include cellular base-station diversity receivers, multiband software-defined radio IF strips, instrumentation and test equipment, low-latency digital oscilloscopes, medical imaging front ends, and industrial process control loops. Designers prefer this part when simultaneous sampling on two matched channels simplifies I/Q or diversity capture. The wideband noise floor and linearity also suit direct IF sampling of intermediate-frequency carriers up to several hundred megahertz.
When designing with the LTC2270CUP, ensure the input common-mode and coupling network match the recommended application circuit, place decoupling within a few millimeters of each supply pin, and bond the exposed pad to a continuous ground plane for thermal and electrical performance. The 1.5 dB programmable input gain allows trade-offs between noise figure and full-scale headroom for downstream FPGA decimation stages.
This page consolidates distributor pricing, drop-in compatible ADCs, recommended decoupling topology, and application guidance not contained in a single manufacturer datasheet - giving system engineers a single reference point for part selection and PCB bring-up.
ドロップイン代替品: LTC2270CUP — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2270CUP （同一形状・フットプリント） — 相違点: Number of Channels, Operating Temperature Range, Package, Resolution, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2270IUP
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$75.8 / 個
データシートを見る →LTC2270CUP#TRPBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2270CUP#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2270CUP 最大定格＆電気的特性
| 分解能 | 16 bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| サンプリングレート | 20 Msps (max) |
| ADC Architecture | Pipelined |
| Input Type | Differential |
| 入力電圧範囲 | 2 Vp-p differential (per channel) |
| Signal-to-Noise Ratio (SNR) | 84.1 dB |
| Spurious-Free Dynamic Range (SFDR) | 99 dBc |
| Conversion Latency | Single-clock pipelined (low-latency) |
| Reference | Internal (with external reference option) |
| Digital Output | CMOS, parallel |
| ピン数 | 64 |
| パッケージ | QFN-64 (9x9 mm) with exposed pad |
| 動作温度範囲 | 0 C to 70 C (commercial grade) |
| RoHS ステータス | Compliant (per #PBF / #TRPBF suffixes) |
| 実装タイプ | Surface Mount |
| Start Price (1ku) | $82.93 (per ADI product page) |
LTC2270CUP qfn-64 (9x9 mm) with exposed pad ピン配置ガイド
LTC2270CUP (qfn-64 (9x9 mm) with exposed pad パッケージ) のピン配置。 このアナログコンポーネントは、入力、出力、および電源ピンを備えています。オフセットナル、補償、イネーブルピンの設定については、メーカーのデータシートを参照してください。信号調整やアンプ回路に最適です。
詳細なピン配置データはありません: LTC2270CUP.
詳細は データシート をご参照ください。
主な用途
LTC2270CUP の用途: 7 件s: Cellular Base-Station Diversity Receivers, Software-Defined Radio (SDR) IF Strips, Test & Measurement Instrumentation, Medical Imaging Front Ends (Ultrasound, Beamforming), Industrial Process Control & Data Acquisition, Multi-Channel Digital Storage Oscilloscope (DSO) Front Ends, Software-Defined IF Sampling for Radar & Lidar.
Cellular Base-Station Diversity Receivers
Cellular base-station diversity receivers need two matched channels sampled simultaneously so that the FPGA's channel-combining math sees identical gain, offset, and timing on every pair of samples. The LTC2270CUP's dual 16-bit pipelined cores run from a common clock and reference, giving the matched pair essential for diversity combining. The 84.1 dB SNR and 99 dBc SFDR keep demodulator error vector magnitude low even for weak adjacent cells where noise dominates. Each channel accepts 2 Vp-p differential drive from a standard RF front-end demodulator, and the CMOS outputs land directly on a Stratix-class FPGA at 20 Msps. Compared with a single-channel high-speed ADC plus external splitter, the LTC2270CUP saves board area, removes the splitter-induced phase skew, and reduces BOM cost by approximately half on the data-converter side.
おすすめ
Software-Defined Radio (SDR) IF Strips
Software-defined radios at intermediate frequencies need matched I/Q capture so that the digital downconverter in the FPGA sees phase- and amplitude-balanced data on both branches. The LTC2270CUP's simultaneous dual-channel sampling preserves that balance up to 20 Msps, giving an effective I/Q bandwidth of about 5 MHz per channel. The internal bandgap reference keeps gain error below 0.1 percent across the operating range, while the 99 dBc SFDR keeps spurious images out of the digital spectrum and lets the DDC clean up only real signal content. Its small 64-QFN (9x9) footprint drops directly onto SDR reference designs and is supported by ADI's evaluation kit schematics. Designers combine this ADC with the LTC2175IUKG-12 14-bit 125 Msps ADC on the wider-bandwidth observation antenna path to build a two-tier SDR receiver.
おすすめ
Test & Measurement Instrumentation
Bench and production test instruments require high dynamic range together with deterministic channel-to-channel delay so that oscilloscope-style time-domain measurements stay coherent. The LTC2270CUP delivers 84.1 dB SNR at 5 MHz input, which lets a 16-bit digitizer resolve signals below the -100 dBc noise floor of many stimulus sources. Its single-clock-per-conversion pipelined architecture yields one fixed latency value, easing trigger timing math in the host FPGA or DSP. The 20 Msps rate handles all but the highest-bandwidth oscilloscope channels; designers use two LTC2270CUP channels for differential input probing and timing alignment. The exposed-pad QFN package also keeps junction temperature low in sealed bench-top chassis where free-air cooling is limited.
おすすめ
Medical Imaging Front Ends (Ultrasound, Beamforming)
Medical ultrasound and other beamforming front ends require many matched channels, low per-channel power, and predictable group delay across all channels. The LTC2270CUP's two pipelined cores per package fit naturally into dense 32- or 64-channel beamforming boards, where designers place one IC per transducer pair. The 84.1 dB SNR preserves Doppler sensitivity on slow blood-flow signals, and the CMOS outputs are directly compatible with downstream FPGAs that perform delay-and-sum beamforming. Per ADI's reference designs, the dual channel architecture halves board space and power compared to monolithic single-channel ADCs of similar resolution. The 0 C to 70 C commercial grade suits well-controlled equipment-room environments; the LTC2270IUP provides industrial-grade coverage when needed.
おすすめ
Industrial Process Control & Data Acquisition
Industrial process control systems run many channels of low-frequency analog signals (4-20 mA loops, thermistors, RTDs) into PLC-style data acquisition modules. Modern industrial DAQs favor simultaneous-sampling ADCs so that all inputs see the same point in time, eliminating skew artifacts in multi-variable control loops. The LTC2270CUP's two matched cores and 84.1 dB SNR deliver 16-bit precision at 20 Msps oversample rates, allowing digital averaging to push effective resolution well above 16 bits for slow signals. The exposed-pad QFN package makes the IC resistant to vibration and thermal cycling in factory-floor enclosures, and 5 V analog + 3.3 V digital supply rails are straightforward to derive from 24 V industrial buses using an ADP1755 LDO. Designers pair the ADC with a Cortex-M-class host to push digitized waveforms onto industrial Ethernet backbones.
おすすめ
Multi-Channel Digital Storage Oscilloscope (DSO) Front Ends
DSOs have always demanded low-noise, low-latency, multi-channel digitizers, and the LTC2270CUP's dual pipelined cores map neatly onto differential scope probe inputs. Designers typically fan a 4-channel scope's front end with two LTC2270CUPs, saving both board area and ADC cost versus four single-channel parts. The 99 dBc SFDR handles large input-signal swings without masking low-level harmonics, important for both power-electronics transient analysis and EMI compliance measurements. The exposed-pad QFN package is small enough that highly populated multi-channel front ends fit into compact modular oscilloscope heads. Per ADI's digital oscilloscope application notes, the LTC2270CUP's clean impulse response simplifies the FPGA's frequency-response calibration filters and improves low-noise floor measurements.
おすすめ
Software-Defined IF Sampling for Radar & Lidar
Phased-array radar and emerging lidar architectures have shifted signal conditioning into the digital domain, demanding ADCs that preserve phase integrity across multiple channels. The LTC2270CUP's matched dual channel cores, with their common clock and reference, hold inter-channel phase error well below one degree at the IF frequency of interest. Its 84.1 dB SNR preserves the noise floor of echos back to the radar's maximum unambiguous range, while the 20 Msps throughput accepts intermediate frequencies up to several megahertz. The small 64-QFN footprint helps fit many receive channels onto each antenna-array daughter board. Pair the ADC with the LTC2155CUP-12 14-bit 65 Msps device for the wider-bandwidth secondary receiver chain.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2270CUP — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2270IUP | LTC2270CUP#TRPBF | LTC2270CUP#PBF |
|---|---|---|---|---|
| Package | QFN-64 (9x9) | QFN-64 (9x9) | QFN-64 (9x9) | QFN-64 (9x9) |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 16 bits | 16 bits | 16 bits | 16 bits |
| Sampling Rate | 20 Msps | 20 Msps | 20 Msps | 20 Msps |
| Number of Channels | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) |
| SNR | 84.1 dB | 84.1 dB | 84.1 dB | 84.1 dB |
| SFDR | 99 dBc | 99 dBc | 99 dBc | 99 dBc |
| Operating Temperature Range | 0 C to 70 C (Commercial) | -40 C to 85 C (Industrial) | 0 C to 70 C (Commercial) | 0 C to 70 C (Commercial) |
| RoHS / Lead-Free | Yes (per #PBF / #TRPBF suffixes) | Yes | Yes | Yes |
主な差別化要因
- Dual simultaneous-sampling 16-bit channels in a single 9x9 mm QFN （vs LTC2206IUK (single-channel 16-bit 65 Msps ADC))
- Better SNR and SFDR than 14-bit ADCs at the same power level （vs LTC2249IUH (14-bit 80 Msps ADC))
- Lower bandwidth but tighter matched pair than a single high-speed ADC plus splitter （vs LTC2184IUP (16-bit 105 Msps single ADC))
設計ノート
Use a four-layer board with the top layer dedicated to analog signals and ADC inputs, an inner continuous ground plane, an analog power plane for OVDD/AVDD, and a digital power plane for the FPGA-facing outputs. Place 0.1 uF X7R ceramic decoupling capacitors within 3 mm of every supply pin and a single 4.7 uF tantalum or polymer bulk capacitor on each main supply rail. Route the analog input traces as tightly coupled differential pairs of matched length with no crossing over digital signals; the exposed pad must be stitched with multiple vias to the ground plane to keep the thermal resistance below 25 C/W at full 20 Msps continuous operation.
Do not allow CMOS digital outputs to share a connector pin or a long parallel trace with the analog inputs; the digital switching current returns can couple directly back into the ADC front end. Always provide a Pi filter or ferrite bead on the analog-to-digital supply crossing, and ensure the encode clock (ENC+/ENC-) is treated as a high-priority signal: short traces, matched length, series termination at the driver, and series damping near the ADC if the path exceeds 50 mm. Failing to terminate the encode clock properly causes noisy converted data at high input frequencies and is the most common lab bring-up issue.
Place the LTC2270CUP directly adjacent to its input transformer or driver op-amp to keep the analog trace loop area under 10 mm x 10 mm and minimize common-mode kickback. Per ADI's evaluation board layout guidelines, the analog ground and digital ground meet only at the exposed pad of the ADC, eliminating ground loops that would otherwise couple digital switching noise into the analog input network. Designers should also keep analog and digital sections physically separated by more than 5 mm so that radiated noise does not couple to the high-impedance analog front end.
Differential inputs require tight 100-ohm differential and 50-ohm per-side characteristic impedance, and any stubs created by an ADC sample-and-hold capacitor during the input track phase must be absorbed by the driver op-amp or balun. With an LTC6406-style ADC driver and a 1:1 input transformer, the 7th-harmonic spurious response typically remains below -100 dBFS. When sampling high-IF frequencies (above 100 MHz), verify that the encode clock jitter is below 0.5 ps RMS so that the ADC's SNR does not collapse from the published 84.1 dB.
コンプライアンス情報
Per the LTC2270CUP#PBF and #TRPBF ordering codes listed on DigiKey, the part is RoHS-compliant and lead-free. Halogen-free status is not explicitly stated in the distributor excerpt provided and is therefore marked unknown. AEC-Q100 qualification is not claimed for this commercial-grade (0 C-70 C) ADC; the analog IC family in general is not automotive-qualified.
