LTC3310SIV-1#PBF - 10A Silent Switcher 2 Step-Down DC/DC | ADI
部品番号: LTC3310SIV-1#PBF ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $8.45 | $8.45 |
| 10 | $7.61 | $76.10 |
| 100 | $6.78 | $678.00 |
| 500 | $6.1 | $3,050.00 |
| 1,000 | $5.42 | $5,420.00 |
LTC3310SIV-1#PBF 概要
What is a Silent Switcher 2 buck converter? A buck (step-down) DC/DC converter is a switching regulator that efficiently converts a higher DC voltage to a lower DC voltage by chopping the input with a power switch and smoothing with an LC filter. Silent Switcher 2 is Analog Devices' second-generation ultra-low-EMI architecture that integrates the bypass capacitors directly inside the package over the inductor (hot loop), virtually eliminating the high-frequency loop antenna and reducing radiated EMI by up to 20 dB compared with conventional buck layouts.
Key features include 10A continuous output current from a tiny 9 mm² footprint, programmable switching frequency up to 5 MHz, 95% peak efficiency at 1 MHz, and ±1% output voltage accuracy over line, load, and temperature. The LTC3310SIV-1#PBF also integrates internal MOSFETs plus bootstrap diodes, so no external Schottky or FETs are required, and it supports external clock synchronization for multi-rail systems.
The device uses a constant-frequency peak current-mode control architecture with internal compensation, simplifying loop design. The -1 variant accepts an external reference voltage on the VREF/ITH pin, allowing it to track a system reference or implement DDR termination. The internal MOSFETs use low-Qg, low-Rds(on) silicon for high efficiency even at light loads, and the IC includes input overvoltage, output overvoltage, and thermal shutdown protections.
Typical applications include point-of-load regulation for FPGAs, ASICs, and DSPs in optical transceivers and RF modules; DDR memory termination; telecom base-station digital rails; and any space-constrained 5V distributed-bus design where low EMI is mandatory. The compact 3mm x 3mm footprint also makes it well suited to handheld test and measurement instruments.
When designing with this part, place the input capacitors as close as possible to the VIN and GND pins, use a 0.47µH to 1µH low-DCR shielded inductor, and ensure the exposed pad has at least 4 thermal vias to the inner ground plane. The Silent Switcher 2 architecture eliminates many PCB layout EMI pitfalls but does not eliminate the need for a proper input capacitor return path.
ドロップイン代替品: LTC3310SIV-1#PBF — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC3310SIV-1#PBF （同一形状・フットプリント） — 相違点: Topology, Output Voltage Range, Package, Switching Frequency, Architecture.
クイック比較ツール — 並列比較する代替部品を選択:
LTC3310SIV#PBF
✅ ドロップイン✓ 在庫あり
$5.45 / 個
データシートを見る →LTC3310SEV-1#TRMPBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC3310SIV-1#TRMPBF
✅ ドロップイン✓ 在庫あり
$5.2 / 個
データシートを見る →LTC3310SIV#WPBF
✅ ドロップイン✓ 在庫あり
$5.5 / 個
データシートを見る →LTC3310HV#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC3310SIV-1#PBF 最大定格＆電気的特性
| トポロジー | Synchronous Buck (Step-Down) |
| 入力電圧範囲 | 2.25 V to 5.5 V |
| 出力電圧範囲 | 0.5 V to 5.5 V |
| 最大出力電流 | 10 A |
| Architecture | Silent Switcher 2 with internal bypass capacitors |
| Peak Efficiency | 95% (typical, 1 MHz, 5 V to 1.8 V) |
| スイッチング周波数 | Up to 5 MHz (programmable) |
| Output Voltage Accuracy | ±1% over line, load, and temperature |
| Reference | External reference (LTC3310S-1 variant) |
| Internal MOSFETs | Yes (high-side and low-side N-channel, with bootstrap diodes) |
| Control Mode | Peak current-mode with internal compensation |
| パッケージ | 18-LQFN (3 mm x 3 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| 動作接合温度 | -40 °C to +125 °C |
| MSLレベル | 1 (per JEDEC J-STD-020) |
| RoHS ステータス | Compliant |
| Clock Synchronization | Yes (external SYNC input) |
| Protections | Input OVP, output OVP, thermal shutdown, current limit |
LTC3310SIV-1#PBF ピン構成
| ピン 1 | EN — Precision enable with hysteresis; tie high to enable, use resistor divider for UVLO threshold |
| ピン 2 | VIN — Main input supply (2.25 V to 5.5 V); place decoupling close to this pin |
| ピン 3 | VIN — Main input supply (second pin to reduce parasitic inductance) |
| ピン 4 | BST — Bootstrap supply for high-side gate driver; connect to SW via 0.1 µF capacitor |
| ピン 5 | SW — Switch node (output of internal high-side / low-side MOSFET half-bridge) |
| ピン 6 | SW — Switch node (second pin for current handling) |
| ピン 7 | SW — Switch node (third pin for current handling) |
| ピン 8 | GND — Power ground for low-side MOSFET and gate driver |
| ピン 9 | GND — Power ground (second pin) |
| ピン 10 | GND — Signal ground reference (per datasheet) |
| ピン 11 | VFB/ITH/VREF — External reference input / compensation node (-1 variant uses external VREF) |
| ピン 12 | RT — Timing resistor to GND programs switching frequency from 500 kHz to 5 MHz |
| ピン 13 | SYNC — External clock synchronization input; tie to RT if unused |
| ピン 14 | PGOOD — Open-drain power-good output; pull up to INTVCC or external rail |
| ピン 15 | INTVCC — Internal 3.3 V LDO output; bypass with 1 µF ceramic to GND |
| ピン 16 | VIN — Input supply (third pin) |
| ピン 17 | BST — Bootstrap (second pin, optional dual connection) |
| ピン 18 | NC — No connect (per datasheet, unused pin reserved for factory test) |
| ピン EP | Exposed Pad — Thermal pad and ground; must be soldered to PCB ground plane with thermal vias |
主な用途
LTC3310SIV-1#PBF の用途: 6 件s: FPGA/ASIC Point-of-Load Regulation, DDR Memory VTT Termination, Optical Transceiver Modules, Telecom Base-Station Digital Rails, Portable Test & Measurement Instruments, Industrial IoT Edge Gateways.
FPGA/ASIC Point-of-Load Regulation
The LTC3310SIV-1#PBF delivers up to 10 A from a 3 mm x 3 mm footprint to power the core rails of FPGAs, ASICs, and DSPs in optical transceivers and RF modules. Its 95% peak efficiency at 5 V to 1.8 V and ±1% reference accuracy minimize both heat and supply-induced jitter in high-speed SERDES. The Silent Switcher 2 architecture lets the converter sit directly beside the load without input pi-filters, shrinking the BOM.
おすすめ
DDR Memory VTT Termination
The -1 suffix on the LTC3310SIV-1#PBF means it accepts an external reference on the VREF/ITH pin, which is exactly what DDR4 and DDR5 VTT termination requires. By tracking a half-VDDQ reference generated externally or by the LTC3310SIV#PBF (internal reference variant), the converter keeps VTT centered as VDDQ ramps through PVT. The 10 A capability easily sources and sinks the transient currents demanded by simultaneous switching outputs in DDR interfaces.
おすすめ
Optical Transceiver Modules
QSFP-DD and OSFP optical transceivers demand a compact, low-EMI buck to feed the DSP and driver TIAs from a 3.3 V module supply. The LTC3310SIV-1#PBF's 3 mm x 3 mm footprint and Silent Switcher 2 architecture allow it to be placed within 5 mm of the load without violating QSFP EMI masks. 10 A peak current handles the burst-mode transients of DSP wake events, while the external reference supports dynamic voltage scaling for power saving.
おすすめ
Telecom Base-Station Digital Rails
5G radio units and small-cell base stations require rugged 5 V-distributed-bus DC/DC converters with strict EMI margins. The LTC3310SIV-1#PBF's 2.25 V to 5.5 V input accepts 5 V bus directly, and its internal bypass capacitors reduce radiated EMI by up to 20 dB versus discrete designs, easing CISPR 24 / GR-1089 compliance. The 125 °C junction temperature rating supports outdoor sealed enclosures.
おすすめ
Portable Test & Measurement Instruments
Handheld oscilloscopes, portable logic analyzers, and battery-powered data-acquisition modules need an efficient, compact 5 V to 3.3 V or 5 V to 1.8 V rail that does not pollute sensitive analog front ends. The LTC3310SIV-1#PBF's Silent Switcher 2 architecture eliminates switching noise coupling into adjacent ADC input channels, and the 95% efficiency preserves battery runtime. Its 3 mm x 3 mm package fits inside slim probe housings.
おすすめ
Industrial IoT Edge Gateways
Edge gateways consolidate multiple sensors, radios, and processors on a 5 V or 12 V backplane and require low-EMI, high-current point-of-load converters. The LTC3310SIV-1#PBF's 10 A output, ±1% accuracy, and Silent Switcher 2 EMI performance make it well suited to feed SoC cores and DDR memory simultaneously. The exposed-pad package simplifies thermal management in fanless IP65 enclosures where ambient temperatures can reach 85 °C.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC3310SIV-1#PBF — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC3310SIV#PBF | LTC3310SEV-1#TRMPBF | LTC3310SIV-1#TRMPBF | LTC3310SIV#WPBF | LTC3310HV#PBF |
|---|---|---|---|---|---|---|
| Package | 18-LQFN (3 mm x 3 mm) with EP | 18-LQFN (3 mm x 3 mm) with EP - same | 18-LQFN (3 mm x 3 mm) with EP - same | 18-LQFN (3 mm x 3 mm) with EP - same | 18-LQFN (3 mm x 3 mm) with EP - same | LQFN-18 - same footprint family |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Output Current | 10 A | 10 A | 10 A | 10 A | 10 A | 10 A |
| Reference Type | External (VREF/ITH pin) | Internal 0.5 V | External (-1 variant) | External (-1 variant) | Internal 0.5 V | Internal 0.5 V |
| Operating Junction Temperature | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C (E-grade characterized) | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C |
| Switching Frequency (max) | 5 MHz | 5 MHz | 5 MHz | 5 MHz | 5 MHz | 5 MHz |
| Peak Efficiency | 95% | 95% | 95% | 95% | 95% | 94% |
| EMI Architecture | Silent Switcher 2 | Silent Switcher 2 | Silent Switcher 2 | Silent Switcher 2 | Silent Switcher 2 | Silent Switcher 2 |
| Packaging Format | Tray | Tray | Tape & Reel | Tape & Reel | Tray | Tray |
主な差別化要因
- External reference tracking enables DDR VTT termination （vs LTC3310SIV#PBF (non- -1 variant))
- Silent Switcher 2 architecture eliminates input pi-filter （vs LTC3310HV#PBF (same family, older generation))
- Smallest 10 A 3 mm x 3 mm footprint with 5 MHz switching （vs LTC8645SEV#PBF (12 A, slightly larger package))
設計ノート
Estimated: at VIN = 5 V, VOUT = 1.8 V, IOUT = 10 A, the LTC3310SIV-1#PBF dissipates approximately (5 - 1.8) × 10 × (1 - 0.95)/0.95 = 1.7 W. The 18-LQFN exposed pad has a typical θJA near 35 °C/W on a 4-layer 1 oz PCB with 4 thermal vias, so junction rises about 60 °C above ambient - acceptable up to ~65 °C ambient. At 5 V to 3.3 V the dissipation drops to ~0.5 W, so no heatsinking is required. Place input ceramics within 2 mm of VIN/GND pins to keep the hot loop tight.
The Silent Switcher 2 architecture places bypass capacitors directly above the inductor on the package substrate, so the designer does not need to mirror them on the PCB. However, you must still place the input decoupling (typically two 22 µF 0402 ceramics) within 1-2 mm of the VIN and GND pins, and the exposed pad must be soldered to a continuous ground copper pour with at least 4 thermal vias to the inner ground plane. Vias should be 0.3 mm diameter, 1 oz plating, on a 1.0 mm pitch.
Three pitfalls to avoid: (1) Do not leave BST floating - it needs a 0.1 µF ceramic to SW or the high-side gate will not enhance. (2) Tie SYNC to GND if unused, otherwise the part may lock onto internal noise. (3) On the -1 variant, never leave VREF/ITH floating - it must be driven by a buffered reference or the output will drift to the maximum duty cycle. Reference datasheet page 5 for the recommended external reference buffer circuit.
コンプライアンス情報
RoHS and REACH compliance per Analog Devices product page. Not AEC-Q100 qualified; choose LTC3310SEV-1#TRMPBF for automotive-grade requirements. Halogen-free status not stated in verified data.
