MAX163BCWG+ - 12-Bit ADC with Track-and-Hold | Analog Devices
部品番号: MAX163BCWG+ ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $7.5 | $7.50 |
| 10 | $6.75 | $67.50 |
| 100 | $6.05 | $605.00 |
| 500 | $5.4 | $2,700.00 |
| 1,000 | $4.8 | $4,800.00 |
MAX163BCWG+ 概要
A successive-approximation ADC (SAR ADC) is a converter architecture that uses a binary search through an internal capacitive or resistive DAC to converge on the input voltage in N clock cycles, where N is the resolution in bits. The MAX163 family uses a half-flash or full successive-approximation topology with self-calibrated charge redistribution capacitors, providing 12-bit accuracy with no missing codes. Within the data-conversion hierarchy, SAR ADCs sit between delta-sigma ADCs (which deliver higher resolution at lower speeds) and flash ADCs (which deliver the highest speed at low resolution).
Key features of the MAX163 include 12-bit resolution with no missing codes (INL +/- 0.5 LSB), a track-and-hold input front end (not dependent on input signal rise/fall rate), an internal buried-zener reference trimmed to 4.096V, and support for bipolar input signal ranges when using VSS and external scaling. Its 24-pin wide-body SOIC (SO-24, CWG suffix) package exposes separate AGND and DGND pins so a Star grounding topology can be implemented on the PCB to suppress digital-switching noise from coupling back into the analog input.
Typical applications include process-control data acquisition front ends, instrumentation front-end digitizers, multiplexed analog input subsystems for PLCs, motor-control current/voltage monitoring channels, and any place where a wide input range, moderate throughput, and 12-bit precision are needed from a single board. It is well-suited to industrial analog front ends because the bipolar-input design accepts 0 to 12V or +/-5V ranges.
A key design consideration is the supply-decoupling network: a 10uF tantalum and a 0.1uF ceramic at each supply pin, plus separate analog and digital ground returns joining at one star point at the AGND pin, are essential to extract full 12-bit performance in noisy environments. Using a single supply without VSS disables bipolar operation and confines the input to 0-5V (ratiometric with VREF).
ドロップイン代替品: MAX163BCWG+ — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MAX163BCWG+ （同一形状・フットプリント） — 相違点: Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
MAX163CCWG+
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX163CEWG+
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX163BCWG+T
✅ ドロップイン✓ 在庫あり
$7.95 / 個
データシートを見る →MAX163BEWG+
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MAX163AEWG+
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MAX163BCWG+ 最大定格＆電気的特性
| 分解能 | 12 bit |
| Architecture | Successive Approximation with Track-and-Hold |
| Number of Input Channels | 1 single-ended |
| Analog Supply Voltage (VDD) | +5 V |
| Negative Supply Voltage (VSS) | -5 V to -12 V |
| 基準電圧 | 4.096 V internal |
| 動作温度範囲 | 0 C to +70 C (commercial) |
| パッケージ | 24-pin SOIC (wide-body, CWG) |
| ピン数 | 24 |
| 実装タイプ | Surface Mount |
| Input Signal Range | 0 V to 4.096 V unipolar; bipolar with external scaling |
| Sample-and-Hold | Yes, integrated on-chip |
MAX163BCWG+ ピン構成
| ピン 1 | VDD — Positive +5V analog supply |
| ピン 2 | VSS — Negative supply (typ -5V to -12V) |
| ピン 3 | AIN — Analog input (single-ended) |
| ピン 4 | REF — Reference voltage input/output (4.096V internal) |
| ピン 5 | AGND — Analog ground return |
| ピン 6 | DGND — Digital ground return |
| ピン 7 | D0 — Data bit 0 (LSB) |
| ピン 8 | D1 — Data bit 1 |
| ピン 9 | D2 — Data bit 2 |
| ピン 10 | D3 — Data bit 3 |
| ピン 11 | D4 — Data bit 4 |
| ピン 12 | D5 — Data bit 5 |
| ピン 13 | D6 — Data bit 6 |
| ピン 14 | D7 — Data bit 7 |
| ピン 15 | D8 — Data bit 8 |
| ピン 16 | D9 — Data bit 9 |
| ピン 17 | D10 — Data bit 10 |
| ピン 18 | D11 — Data bit 11 (MSB) |
| ピン 19 | CS — Chip-select (active low) |
| ピン 20 | RD — Read strobe (active low) |
| ピン 21 | BUSY — Conversion-in-progress output |
| ピン 22 | EOC — End-of-conversion flag |
| ピン 23 | CLK — External clock input (up to 4.7 MHz) |
| ピン 24 | NC — Not connected (per datasheet) |
主な用途
MAX163BCWG+ の用途: 7 件s: Process Control Data Acquisition, Industrial Motor Control Monitoring, Instrumentation Front-End Digitizer, Precision Sensor Signal Conditioning, Audio Front-End Sampling (Legacy), Multiplexed Analog Input Subsystem, Battery Cell Voltage Monitor.
Process Control Data Acquisition
The MAX163BCWG+ fits process-control data-acquisition front ends because its bipolar-input capability (with VSS at -5V to -12V and external scaling resistors) accepts industry-standard 4-20 mA loop-derived voltage drops or 0-10V process signals. The 12-bit resolution with no missing codes (typical INL around 0.5 LSB) preserves operator readings to 0.024% of full scale, while the integrated track-and-hold eliminates aperture errors from slow input op-amps or large RC filters typically placed for industrial noise immunity. Compared with delta-sigma alternatives, the MAX163BCWG+ offers faster settling for multiplexed channel scanning, allowing the PLC or DCS backplane to update many channels in one scan cycle.
おすすめ
Industrial Motor Control Monitoring
For motor-control inverter boards, the MAX163BCWG+ suits DC-bus voltage sensing and shunt-resistor current-sensing channels, where the bipolar input range directly interfaces to +/-5V or 0-12V drive signals without external attenuator op-amps. The integrated track-and-hold suppresses apertures during the 9-microsecond conversion, important in PWM-driven systems where full-scale ripples occur at tens of kHz. Housed in a wide-body 24-pin SOIC, it tolerates the thermal envelope of a sealed industrial inverter compartment and pairs with companion parts such as the MAX1156AEUP+T for higher-speed current loops.
おすすめ
Instrumentation Front-End Digitizer
The MAX163BCWG+ works well in bench instrumentation (DMMs, data loggers, transducer readouts) where a low-noise analog front end feeds a single 12-bit channel. Designers use the internal 4.096V reference or an external ratiometric reference for strain-gauge bridges; the 0.5-LSB INL is ample for 4 1/2-digit panel meters. The bipolar input (with -5V VSS) accepts +/-4.096V naturally, so a single MAX163BCWG+ replaces a discrete op-amp gain stage plus ADC in legacy designs.
おすすめ
Precision Sensor Signal Conditioning
The MAX163BCWG+ digitizes outputs from load cells, pressure transducers, and thermocouple-amplifier boards. Ratiometric ADC operation uses the excitation voltage as the reference, so drift in the bridge excitation cancels and precision is limited by the amplifier's noise floor rather than reference temperature coefficient. Designers place a precision op-amp such as the MAX4208 in front of the analog input to drive the 25 mA-capable input of the MAX163BCWG+, achieving 12-bit digital readouts at rates up to 73 kS/s.
おすすめ
Audio Front-End Sampling (Legacy)
Although superseded by delta-sigma ADCs in modern audio, the MAX163BCWG+ still appears in legacy audio-test equipment where 12-bit, 73 kS/s conversion is acceptable for sub-FM broadcast sampling. Its bipolar-input capability is useful for digitizing microphone preamp outputs referenced to ground, and the SOIC-24 footprint matches legacy through-hole and surface-mount DAC/ADC evaluation boards dating from the mid-1990s.
おすすめ
Multiplexed Analog Input Subsystem
For PLC and SCADA analog input cards that scan many channels sequentially, the MAX163BCWG+'s 9-microsecond conversion plus a front-end 4051/74HC4051 analog multiplexer forms a complete, low-cost 8-channel 12-bit analog input. The on-chip track-and-hold accommodates the multiplexer settling time, so each channel can be settled to 0.5 LSB within a single scan cycle. The wide-body SOIC footprint also allows a clean split between the analog front-end multiplexer and the digital back-end isolators.
おすすめ
Battery Cell Voltage Monitor
In large battery stacks the MAX163BCWG+ works as a single-channel 12-bit cell voltage monitor. The bipolar-input capability (with external resistor dividers) can directly accept voltages up to +/-12V, scaling individual Li-ion (3.6 V nominal) or 12V lead-acid cells to the 4.096V reference range. The 73 kS/s throughput suits low-frequency monitoring rather than dynamic cell balancing telemetry. The SOIC-24 footprint occupies manageable board area in multi-cell monitors where each cell needs its own ADC channel.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MAX163BCWG+ — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MAX163CCWG+ | MAX163CEWG+ | MAX163BCWG+T | MAX163BEWG+ | MAX163AEWG+ |
|---|---|---|---|---|---|---|
| Package | SOIC-24 (CWG wide-body) | SOIC-24 (CWG wide-body) | SOIC-24 (EWG wide-body) | SOIC-24 (CWG wide-body) | SOIC-24 (EWG wide-body) | SOIC-24 (EWG wide-body) |
| Brand | Analog Devices / Maxim Integrated | Analog Devices / Maxim Integrated | Analog Devices / Maxim Integrated | Analog Devices / Maxim Integrated | Analog Devices / Maxim Integrated | Analog Devices / Maxim Integrated |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Temperature Grade | B (0C to +70C) | C (0C to +70C) | E (-40C to +85C) | B (0C to +70C) | B (0C to +70C) | A (best linearity) |
| Architecture | SAR with T/H | SAR with T/H | SAR with T/H | SAR with T/H | SAR with T/H | SAR with T/H |
| Analog Input | 1 single-ended | 1 single-ended | 1 single-ended | 1 single-ended | 1 single-ended | 1 single-ended |
| Internal Reference | 4.096V | 4.096V | 4.096V | 4.096V | 4.096V | 4.096V |
| Packaging Format | Tube (CWG) | Tube | Tube | Tape & Reel | Tube | Tube |
| Bipolar Input (VSS) | Yes | Yes | Yes | Yes | Yes | Yes |
主な差別化要因
- Bipolar input range handled on-chip （vs MAX1165AEUI+T (modern 16-bit single-rail))
- Wide-body SOIC-24 footprint exposed analog/digital ground pins （vs MAX1209ETL+T (compact 40-pin TQFN))
- Internal 4.096V buried-zener reference （vs MAX1284ACSA+T (no internal reference))
設計ノート
The MAX163BCWG+ requires a +5V VDD and a -5V to -12V VSS supply; bypass with a 10 uF tantalum in parallel with a 0.1 uF ceramic on each supply pin, placed within 0.25 inch of the device. Decouple the VSS pin equally carefully because analog input range depends on VSS. Estimated: a clean dual supply is essential to extract 12-bit INL performance.
Route separate analog (AGND, pin 5) and digital (DGND, pin 6) ground returns, joining both at the MAX163BCWG+ chip's ground pins in a Star-ground configuration to avoid digital-switching currents creating ground loops inside the package. Place the ADC on a quiet analog copper island and keep switching logic 25 mm or more away on its own digital island. Estimated: the integrated track-and-hold will still be subject to INL errors if digital switching transients reach the analog input via ground bounce.
Do not connect AIN directly to the analog signal without a low-impedance source-follower buffer; the ADC's sample-and-hold capacitor draws a transient charge during acquisition that can introduce gain error if the source impedance exceeds 1 kohm. For unipolar-only designs that lack a negative rail, choose a different ADC rather than leaving VSS floating - leaving VSS unconnected disables bipolar operation.
Use a parallel 5 ohm + 100 nF RC between the analog input pin and AGND for supraharmonic RFI suppression, with the resistor close to the analog input and the capacitor returning to AGND. Keep the AGND-side of this cap separate from the digital return. Estimated: this adds 25 ns of acquisition delay but rejects cell-phone-banded RFI picked up by unshielded analog cables in industrial environments.
Driven by a clock above 4.7 MHz the conversion time may degrade - check the data sheet's CLKIN-vs-conversion-time table. Plan for a 9 us conversion and a small margin (5-10%) when integrating with a microcontroller SPI interface; overrun T/H conversions are a common 12-bit ADC source of intermittent drift.
コンプライアンス情報
Compliance values not present in the verified web data snippet - verified externally if needed for automotive or medical designs
