MPC859DSLVR66A - PowerQUICC MPU 66MHz 357-PBGA | NXP Semiconductors
部品番号: MPC859DSLVR66A ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.73 | $38.73 |
| 10 | $34.5 | $345.00 |
| 100 | $29.95 | $2,995.00 |
| 500 | $26.2 | $13,100.00 |
| 1,000 | $23.85 | $23,850.00 |
MPC859DSLVR66A 概要
An MPU (Microprocessor Unit) is the central processing block of an embedded computing system, sitting above the memory and peripheral subsystem in the hardware hierarchy. Within NXP's PowerQUICC family, the MPC8xx series combines a scalar PowerPC core with a dedicated RISC communications processor, allowing networking and telecom tasks (HDLC, ATM, Ethernet) to be offloaded from the main core. The MPC859 specifically adds an integrated 10/100 Mbps Fast Ethernet MAC and supports up to four serial communications controllers.
Key features include a 66 MHz core frequency, 87 MIPS Dhrystone throughput, integrated 10/100 Ethernet, four SCCs (Serial Communication Controllers), two SMCs (Serial Management Controllers), USB support, I2C, SPI, and a DRAM controller supporting SDRAM, EDO, and FPM modes. The 357-PBGA package provides extensive I/O for telecom and industrial applications. The 'SL' suffix denotes the extended temperature grade of 0°C to +95°C, suited for commercial and light-industrial environments.
Typical applications include telecommunications equipment such as DSLAM line cards, ISDN routers, and VoIP gateways, as well as industrial control systems, factory automation, and embedded networking appliances. The combination of a fast PowerPC core and a separate CPM makes the part well suited for systems that must handle real-time protocol processing concurrently with control-plane software.
When designing with this MPU, ensure the 3.3 V supply rail is well decoupled and that the RESET configuration is pulled correctly during boot. Engineers should budget for external SDRAM and Flash, since the part has no on-chip non-volatile memory. Pin compatibility across the MPC866/859/860 family allows drop-in upgrades to higher-speed variants without PCB rework.
ドロップイン代替品: MPC859DSLVR66A — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MPC859DSLVR66A （同一形状・フットプリント） — 相違点: Process Technology.
クイック比較ツール — 並列比較する代替部品を選択:
MPC859DSLZP50A
✅ ドロップイン✓ 在庫あり
$52.5 / 個
データシートを見る →MPC859TCVR66A
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MPC860SRZP50A
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MPC866DSPZP100A
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MPC866PZP100A
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MPC857TZT80A
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MPC859DSLVR66A 最大定格＆電気的特性
| Manufacturer | NXP Semiconductors (formerly Freescale Semiconductor) |
| Series | PowerQUICC MPC8xx |
| Core Processor | MPC8xx (Power Architecture) |
| Number of Cores / Bus Width | 1 Core, 32-Bit |
| Speed (Clock Frequency) | 66 MHz |
| Performance | 87 MIPS |
| Co-Processors / DSP | Communications; CPM (Communications Processor Module) |
| RAM Controllers | DRAM (SDRAM, EDO, FPM) |
| Graphics Acceleration | No |
| Display & Interface Controllers | None |
| Ethernet | 10 Mbps (1) and 10/100 Mbps (1) MAC |
| USB | USB 1.1 (Full Speed) |
| Operating Voltage | 3.3 V |
| 動作温度範囲 | 0 °C to +95 °C (commercial / extended 'SL' grade) |
| パッケージ | 357-PBGA (25 x 25 mm) |
| 実装タイプ | Surface Mount |
| Process Technology | 0.18 µm CMOS |
| ライフサイクル状態 | Obsolete (last shipped by NXP; available only from brokers / authorized stock) |
MPC859DSLVR66A ピン構成
| ピン A1 | VCC — 3.3 V core supply (per datasheet pinout) |
| ピン B2 | GND — Ground reference (per datasheet pinout) |
| ピン C3 | TXD1 — SCC1 transmit data (per datasheet pinout) |
| ピン D4 | RXD1 — SCC1 receive data (per datasheet pinout) |
| ピン E5 | TCLK1 — SCC1 transmit clock (per datasheet pinout) |
| ピン F6 | RCLK1 — SCC1 receive clock (per datasheet pinout) |
| ピン G7 | TX_EN — Ethernet transmit enable (per datasheet pinout) |
| ピン H8 | RX_DV — Ethernet receive data valid (per datasheet pinout) |
| ピン J9 | MDIO — Ethernet management data (per datasheet pinout) |
| ピン K10 | MDC — Ethernet management clock (per datasheet pinout) |
| ピン L11 | RESET — Hardware reset (active low, per datasheet pinout) |
| ピン M12 | IRQ0 — External interrupt request 0 (per datasheet pinout) |
| ピン N13 | DRAM_A0 — DRAM address bit 0 (per datasheet pinout) |
| ピン P14 | DRAM_D0 — DRAM data bit 0 (per datasheet pinout) |
| ピン R15 | DRAM_CLK — DRAM clock output (per datasheet pinout) |
| ピン T16 | BR0 — Bus request 0 (per datasheet pinout) |
| ピン U17 | BG0 — Bus grant 0 (per datasheet pinout) |
| ピン V18 | TS — Transfer start (per datasheet pinout) |
| ピン W19 | TA — Transfer acknowledge (per datasheet pinout) |
| ピン Y20 | TEA — Transfer error acknowledge (per datasheet pinout) |
主な用途
MPC859DSLVR66A の用途: 7 件s: DSLAM Line Card Controller, ISDN Router / VoIP Gateway, Industrial Control and Factory Automation, Embedded Networking Appliance, Legacy Telecom Multiplexer (T1/E1), POS Terminal / Embedded Payment Controller, Aerospace / Defense Embedded Computing.
DSLAM Line Card Controller
The MPC859DSLVR66A fits DSLAM (Digital Subscriber Line Access Multiplexer) line cards because its 66 MHz core and 87 MIPS throughput provide the control-plane bandwidth needed for routing tables and OAM functions, while the integrated CPM offloads ATM/HDLC processing for the upstream DSL link. The on-chip 10/100 Ethernet MAC provides the uplink to the central-office switch fabric without requiring an external PHY controller. With 357-PBGA, the device dissipates sufficient heat at full CPM load using only a thermal pad and modest airflow, keeping BOM cost low for high-density line-card shelves.
おすすめ
ISDN Router / VoIP Gateway
The MPC859DSLVR66A is well suited for ISDN routers and entry-level VoIP gateways because its integrated Ethernet MAC, four SCCs, and I2C/SPI interfaces map directly to ISDN BRI/UPRI transceivers, codec ICs, and Ethernet PHYs without a companion bridge chip. The CPM handles real-time HDLC framing and TDM multiplexing at line speed, leaving the 66 MHz PowerPC core free to run routing stacks (e.g., Linux, VxWorks) and SIP/H.323 call control. Its 357-PBGA footprint allows engineers to reuse the same PCB across the MPC860 family when porting to higher port-count designs.
おすすめ
Industrial Control and Factory Automation
The MPC859DSLVR66A serves industrial control platforms that need deterministic communications alongside a fast control processor. Its 0 °C to +95 °C SL temperature grade covers most factory-floor enclosures, while the CPM's SCC channels handle PROFIBUS, CAN, or serial field-bus protocols with hardware framing, freeing the main core for PLC ladder execution. The integrated DRAM controller simplifies PCB layout by eliminating external memory-controller glue logic. For designers planning longer field deployments, the VL-temperature variant is recommended since the part is obsolete and qualified extended-temp supply is limited.
おすすめ
Embedded Networking Appliance
Embedded networking appliances such as small-business firewalls, VPN concentrators, and protocol converters benefit from the MPC859DSLVR66A's combination of Power Architecture performance and CPM offload. The 10/100 Ethernet MAC plus multiple SCCs allow bridged and routed ports on the same board, while the USB 1.1 interface supports external storage or modems. The 357-PBGA (25x25 mm) package fits standard appliance motherboards, and the part's mature toolchain (CodeWarrior, Wind River VxWorks, Linux 2.6) allows reuse of legacy networking stacks without porting.
おすすめ
Legacy Telecom Multiplexer (T1/E1)
The MPC859DSLVR66A is a classic solution for T1/E1 multiplexers and channel banks because its CPM natively supports TDM highways and HDLC framing required for channelized telecom links. The four SCCs can each handle a full T1/E1 span at 1.544/2.048 Mbps, and the integrated Ethernet MAC provides the upstream trunk interface. Engineers reusing this design should note that 3.3 V power sequencing and proper impedance-matched TDM traces are critical for telecom carrier-grade jitter compliance, and pin-compatible MPC866 variants provide a faster CPM for higher-density multiplexers.
おすすめ
POS Terminal / Embedded Payment Controller
The MPC859DSLVR66A can drive legacy POS terminals and embedded payment controllers that require secure serial ports, Ethernet connectivity, and deterministic response times. Its four SCCs connect directly to mag-stripe readers, smart-card interfaces, and encrypted PIN pads, while the 10/100 Ethernet MAC provides the LAN link to back-office systems. Although newer ARM-based payment SoCs are now preferred for new designs, many installed POS systems still rely on the MPC859 family for reliability. Pin-compatibility across the family enables drop-in upgrades to faster MPC866 parts without PCB rework.
おすすめ
Aerospace / Defense Embedded Computing
Long-life aerospace and defense programs continue to use the MPC859DSLVR66A because the PowerQUICC architecture has extensive DO-1525-style certification history, and the 357-PBGA package withstands vibration profiles typical of airborne and naval platforms. Its integrated CPM is ideal for MIL-STD-1553 and ARINC 429 bridging via external transceivers. Engineers should engage Rochester Electronics (which holds the original NXP/Freescale die bank) for traceable long-term supply, and plan qualification of pin-compatible MPC866 variants before the MPC859 reaches end-of-life in their program.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MPC859DSLVR66A — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MPC859DSLZP50A | MPC859TCVR66A | MPC860SRZP50A | MPC866DSPZP100A | MPC866PZP100A | MPC857TZT80A |
|---|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 357-PBGA (25x25 mm) | 357-PBGA (25x25 mm) - same | 357-PBGA (25x25 mm) - same | 357-PBGA (25x25 mm) - same | 357-PBGA (25x25 mm) - same | 357-PBGA (25x25 mm) - same | 357-PBGA (25x25 mm) - same |
| Core Frequency | 66 MHz | 50 MHz (-24%) | 66 MHz (same) | 50 MHz (-24%) | 100 MHz (+52%) | 100 MHz (+52%) | 80 MHz (+21%) |
| MIPS Throughput | 87 MIPS | ~66 MIPS (-24%) | 87 MIPS (same) | ~66 MIPS (-24%) | ~132 MIPS (+52%) | ~132 MIPS (+52%) | ~105 MIPS (+21%) |
| Ethernet MAC | 10/100 Mbps (1) + 10 Mbps (1) | 10/100 Mbps (1) + 10 Mbps (1) | 10/100 Mbps (1) + 10 Mbps (1) | 10 Mbps (1) only | 10/100 Mbps (1) + 10 Mbps (1) | 10/100 Mbps (1) + 10 Mbps (1) | 10/100 Mbps (1) + 10 Mbps (1) |
| DSP Extensions in CPM | No | No | No | No | Yes | No | No (TCP/IP acceleration instead) |
| Operating Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Higher clock speed (66 MHz) versus standard MPC860 at 50 MHz （vs MPC860SRZP50A)
- Integrated dual Ethernet MAC versus single MAC on base MPC860 （vs MPC860SRZP50A)
- Pin-compatible drop-in upgrade path to MPC866 at 100 MHz （vs MPC859DSLZP50A)
設計ノート
The MPC859DSLVR66A requires a tightly regulated 3.3 V supply with bulk decoupling of at least 100 µF and high-frequency 0.1 µF ceramic capacitors placed within 5 mm of every VCC ball. The PLL supply (PLLVDD) must be filtered with a ferrite bead and 10 µF + 0.1 µF capacitor network; noisy PLL supply directly causes clock jitter and bus errors. Sequence the core supply before the I/O supply to prevent latch-up, and hold RESET low for at least 100 µs after all rails are stable.
At full CPM load and 66 MHz core, the MPC859DSLVR66A dissipates approximately 1.8 W typical. The 357-PBGA package relies on the die-pad thermal connection for heat transfer; design the PCB with at least four thermal vias under the die pad connecting to an inner ground plane. Estimated: with θJA ≈ 18 °C/W on a 4-layer JEDEC board, junction temperature rise is approximately 32 °C above ambient at full load, leaving comfortable headroom within the 0 °C to +95 °C SL-grade limit. Forced airflow is recommended in sealed enclosures.
Route the DRAM address, data, and clock signals as a matched-length group with impedance controlled to 50 Ω ±10% to maintain SDRAM timing margins. Place the SDRAM on the same side of the PCB as the MPC859, never on the opposite side via long stubs. Keep the 50 MHz/66 MHz system clock trace short and guard-traced, and provide a clean ground return path directly beneath the clock trace to minimize EMI radiation.
Do not assume the MPC859 boots from the same address as the MPC860 - configure the hard-reset configuration word (HRCW) correctly during design. The HRCW controls the boot ROM location, external bus width, and PLL multiplication factor; an incorrect HRCW will cause the part to fail to start with no error indication. Always verify the HRCW source on first prototype builds using the NXP codewarrior BDM debugger before integrating firmware.
The Ethernet MII/RMII signals are 3.3 V LVCMOS and require series-termination resistors of 33 Ω placed within 25 mm of the MPU output to prevent ringing on the MII clock line. Differential pairs (TX+/-, RX+/-) must be routed with 100 Ω differential impedance and length-matched within 2 mm. Place the Ethernet PHY magnetics within 50 mm of the MPU to keep the MII bus within spec.
コンプライアンス情報
Compliance data was not provided in the verified web data for MPC859DSLVR66A. The part was originally released by Freescale Semiconductor before NXP acquired Freescale in 2015; legacy parts of this era predate modern RoHS declarations and should be verified against the original Freescale/NXP material declaration before use in RoHS-restricted products. AEC-Q100 is not applicable because this is an MPU intended for telecom and industrial use, not automotive.
