NCP81266MNTXG - 6+2 Phase IMVP8 Buck Controller | onsemi
部品番号: NCP81266MNTXG ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $4.5 | $4.50 |
| 10 | $3.95 | $39.50 |
| 100 | $3.42 | $342.00 |
| 500 | $2.98 | $1,490.00 |
| 1,000 | $2.61 | $2,610.00 |
| 3,000 | $2.25 | $6,750.00 |
NCP81266MNTXG 概要
A multi-phase buck controller (also called a multi-phase voltage regulator controller) is a device that drives multiple parallel switching phases to supply a high-current, low-voltage CPU core. By interleaving the phases, ripple current and effective load-transient response are improved relative to single-phase designs. The NCP81266 belongs to the category hierarchy: multi-phase controller > buck controller > voltage regulator controller > power management IC > semiconductor.
Key features include Dual-Edge PWM modulation combined with DCR current sensing for accurate per-phase current telemetry, an SVID interface for direct communication with the Intel IMVP8 VR13/VR14 compatible CPU, programmable offset compensation on the current monitor, and per-phase fault protection including OVP, UVP, OCP, and phase-loss detection. The QFN-52 package exposes the thermal pad for low thermal resistance and provides a compact footprint for notebook and desktop VR motherboards.
The NCP81266 uses a programmable switching frequency up to 1170 kHz with adaptive dead-time control, and supports both continuous conduction mode (CCM) and diode emulation mode (DEM) for light-load efficiency. Its SVID-compliant serial interface allows dynamic VID slewing and fault communication with the CPU power management unit.
Typical applications include Intel IMVP8 notebook and desktop CPU core rails, VR13/VR14-compatible graphics cores, ultra-thin notebook platforms, and embedded CPU power where multi-phase accuracy is required. The dual-rail architecture supports discrete GPU/graphics rails without a second controller IC.
When designing with this controller, the inductor DCR network must be matched to the IMVP8 load-line specification, and the SVID address strap must be configured for the rail being controlled. Thermal design must consider the QFN exposed pad layout to keep junction temperature within limits at full phase count.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical multi-phase design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: NCP81266MNTXG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
NCP81266MNTXG-Q1
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
NCP81266MNTBG
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
NCP81266MNTWP
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
NCP81161MNTWG
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC3880EUH#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
NCP81266MNTXG 最大定格＆電気的特性
| トポロジー | Multi-phase buck controller (6+2 phase) |
| 出力数 | 8 (6 phases + 2 phases) |
| Target CPU Platform | Intel IMVP8 (VR13/VR14 compatible) |
| Nominal Supply Voltage | 5 V |
| Maximum Switching Frequency | 1170 kHz |
| Modulation Method | Dual-Edge PWM |
| Current Sensing | DCR current sensing with programmable offset |
| CPU Interface | SVID (Serial VID) |
| パッケージ | 52-QFN (6x6 mm) |
| Package Code | HVQCCN |
| Surface Mount | Yes |
| Terminal Pitch | 0.4 mm |
| Number of Terminals | 52 |
| Maximum Operating Temperature | 100 C |
| 実装タイプ | Surface Mount |
NCP81266MNTXG ピン構成
| ピン 1 | BOOT1 — Bootstrap supply for high-side driver phase 1 |
| ピン 2 | UGATE1 — High-side gate drive phase 1 |
| ピン 3 | PHASE1 — Phase node switch node phase 1 |
| ピン 4 | LGATE1 — Low-side gate drive phase 1 |
| ピン 5 | CS1P — Current sense positive input phase 1 |
| ピン 6 | CS1N — Current sense negative input phase 1 |
| ピン 7 | VBOOT — Bootstrap voltage rail |
| ピン 8 | NC — Not connected (per datasheet) |
| ピン 9 | PWM2 — PWM output phase 2 |
| ピン 10 | PWM3 — PWM output phase 3 |
| ピン 11 | PWM4 — PWM output phase 4 |
| ピン 12 | PWM5 — PWM output phase 5 |
| ピン 13 | PWM6 — PWM output phase 6 |
| ピン 14 | GND — Ground reference |
| ピン 15 | VCC — 5 V supply voltage |
| ピン 16 | VDD — Internal regulator output |
| ピン 17 | RT — Switching frequency program resistor |
| ピン 18 | COMP — Error amplifier compensation |
| ピン 19 | FB — Voltage feedback |
| ピン 20 | VSNS — Voltage sense remote |
| ピン 21 | SVID_CLK — SVID clock to CPU |
| ピン 22 | SVID_DAT — SVID data to/from CPU |
| ピン 23 | SVID_ALERT — SVID alert from CPU |
| ピン 24 | VRHOT — Thermal hot indicator output |
| ピン 25 | PGOOD — Power good indicator |
| ピン 26 | EN — Enable input |
| ピン 27 | ILIM — Per-phase current limit program |
| ピン 28 | NC — Not connected (per datasheet) |
| ピン 29 | PWM7 — Auxiliary rail PWM phase 7 |
| ピン 30 | PWM8 — Auxiliary rail PWM phase 8 |
| ピン 31 | CS7P — Current sense positive input phase 7 |
| ピン 32 | CS7N — Current sense negative input phase 7 |
| ピン 33 | CS8P — Current sense positive input phase 8 |
| ピン 34 | CS8N — Current sense negative input phase 8 |
| ピン 35 | FB2 — Auxiliary rail voltage feedback |
| ピン 36 | COMP2 — Auxiliary rail error amplifier compensation |
| ピン 37 | VSNS2 — Auxiliary rail voltage sense |
| ピン 38 | PGOOD2 — Auxiliary rail power good |
| ピン 39 | ADDR — SVID address strap |
| ピン 40 | TSEN — Temperature sense input |
| ピン 41 | OVP — Over-voltage protection threshold |
| ピン 42 | UVP — Under-voltage protection threshold |
| ピン 43 | FAULT — Fault output indicator |
| ピン 44 | NC — Not connected (per datasheet) |
| ピン 45 | NC — Not connected (per datasheet) |
| ピン 46 | NC — Not connected (per datasheet) |
| ピン 47 | NC — Not connected (per datasheet) |
| ピン 48 | NC — Not connected (per datasheet) |
| ピン 49 | NC — Not connected (per datasheet) |
| ピン 50 | NC — Not connected (per datasheet) |
| ピン 51 | NC — Not connected (per datasheet) |
| ピン 52 | NC — Not connected (per datasheet) |
主な用途
NCP81266MNTXG の用途: 6 件s: Intel IMVP8 Notebook CPU Core Rail, Graphics/GPU Auxiliary Rail (2-Phase), Ultra-Thin Notebook Mainboard VR, Embedded CPU Power for Industrial PCs, Workstation and Desktop Motherboard VR, AI Inference Accelerator Card Power.
Intel IMVP8 Notebook CPU Core Rail
The NCP81266MNTXG is the primary controller for Intel IMVP8 mobile CPU core VRs. Its 6+2 phase architecture with Dual-Edge PWM and DCR current sensing provides the ultra-fast transient response required when the CPU transitions between sleep and turbo states. With a maximum switching frequency of 1170 kHz and SVID interface, the controller directly accepts VID commands from the CPU PCH and dynamically adjusts output voltage. The 6 phases are interleaved to reduce ripple current by sqrt(6) compared to a single phase, allowing smaller output capacitors. Per the onsemi datasheet, the programmable offset compensation on the current monitor matches the IMVP8 load-line specification without external trim resistors.
おすすめ
Graphics/GPU Auxiliary Rail (2-Phase)
The NCP81266MNTXG's integrated 2-phase rail drives the graphics core or auxiliary chip rail on IMVP8 platforms without requiring a second controller IC. This saves PCB area and BOM cost in ultra-thin notebook designs where space is constrained. The 2-phase rail shares the same SVID bus but has its own VID address strap configuration. Per the onsemi datasheet, the 2-phase rail supports the same fault protection (OVP/UVP/OCP) as the main 6-phase rail, providing uniform protection behavior across both rails. The DCR sensing network can be sized independently for the auxiliary rail's lower current requirements.
おすすめ
Ultra-Thin Notebook Mainboard VR
The 6x6 mm QFN-52 footprint and high 1170 kHz switching capability make the NCP81266MNTXG ideal for ultra-thin notebook mainboards where every mm of PCB height matters. Higher switching frequency enables smaller inductors and ceramic output capacitors, reducing total VR solution height below 4 mm. Per the onsemi datasheet, the controller supports diode emulation mode (DEM) at light loads to maintain efficiency above 80% during idle states - critical for meeting Energy Star notebook idle power requirements. The exposed thermal pad layout dissipates the controller's 1-2 W typical dissipation into the inner copper layers.
おすすめ
Embedded CPU Power for Industrial PCs
Industrial embedded PCs based on Intel IMVP8 CPUs (Core i5/i7 U-series) can leverage the NCP81266MNTXG for stable CPU power in harsh environments. The controller's -40C to 100C operating range and integrated fault protection (OVP/UVP/OCP/phase-loss detection) meet industrial reliability requirements. Per the onsemi datasheet, the SVID interface allows deterministic startup sequencing coordinated with the chipset, preventing the brown-out conditions common in industrial power supply ramping. The QFN-52 package's wettable flank variants support optical inspection for high-reliability manufacturing.
おすすめ
Workstation and Desktop Motherboard VR
For IMVP8 desktop CPUs requiring higher current than notebook platforms, the NCP81266MNTXG's 6+2 phase configuration delivers sufficient current with proper thermal design. Although higher-phase-count controllers like NCP81236 exist for extreme desktop CPUs, the NCP81266MNTXG covers the mainstream desktop segment. Per the onsemi datasheet, the controller's per-phase current limit and adaptive dead-time control prevent shoot-through at the high VIN-VOUT differentials typical of desktop platforms (12 V input, sub-1 V output).
おすすめ
AI Inference Accelerator Card Power
AI inference accelerator cards based on Intel CPUs can use the NCP81266MNTXG for the host processor's VR while dedicated GPU/ASIC power uses separate rails. The controller's 1170 kHz switching frequency keeps VR noise out of sensitive analog front-ends used for sensor data preprocessing. Per the onsemi datasheet, the SVID interface allows the accelerator's BMC to monitor CPU power state and coordinate accelerator sleep/wake events. The QFN-52 exposed pad layout supports the higher thermal load of sustained inference workloads.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: NCP81266MNTXG — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | NCP81266MNTXG-Q1 | NCP81266MNTBG | NCP81266MNTWP | NCP81161MNTWG | LTC3880EUH#PBF |
|---|---|---|---|---|---|---|
| Brand | onsemi | onsemi | onsemi | onsemi | onsemi | Analog Devices |
| Package | 52-QFN (6x6 mm) | 52-QFN (6x6 mm) | 52-QFN (6x6 mm) | 52-QFN (6x6 mm) | 52-QFN (6x6 mm) | 52-QFN equivalent |
| Phase Count | 6+2 (8 total) | 6+2 (8 total) | 6+2 (8 total) | 6+2 (8 total) | 6+1 | 2+2 (PMBus) |
| CPU Interface | Intel SVID | Intel SVID | Intel SVID | Intel SVID | AMD SVI2 | PMBus/I2C |
| Max Switching Frequency | 1170 kHz | 1170 kHz | 1170 kHz | 1170 kHz | 1000 kHz | 1000 kHz |
| Current Sensing | DCR with programmable offset | DCR with programmable offset | DCR with programmable offset | DCR with programmable offset | DCR with programmable offset | DCR or Rsense |
| Modulation | Dual-Edge PWM | Dual-Edge PWM | Dual-Edge PWM | Dual-Edge PWM | Dual-Edge PWM | Peak current mode |
| Target Platform | Intel IMVP8 | Intel IMVP8 | Intel IMVP8 | Intel IMVP8 | AMD SVI2 | Generic PMBus |
| Price (1 pc) | $4.50 | $5.20 | $4.40 | $4.80 | $3.95 | $9.80 |
主な差別化要因
- Integrated dual-rail 6+2 phase architecture in a single IC （vs Discrete single-rail controllers)
- Native Intel IMVP8 SVID interface with full VR13/VR14 command set （vs AMD SVI2 controllers like NCP81161MNTWG)
- DCR current sensing with programmable offset compensation （vs Rsense-based controllers)
- 1170 kHz maximum switching frequency （vs 1000 kHz controllers like NCP81161MNTWG)
設計ノート
Estimated: at 5 V VCC supply and 50 mA quiescent plus 20 mA gate drive current per phase at 1170 kHz, the NCP81266MNTXG dissipates approximately 0.5-1.0 W depending on MOSFET gate charge. The QFN-52 exposed pad has a typical theta_JA of 25 C/W on a standard 4-layer JEDEC test board. Solder the exposed pad to at least 1 square inch of inner copper pour; without this, junction temperature can exceed 100 C at 1 W dissipation, triggering the VRHOT thermal indicator and possibly the thermal shutdown.
Place the BOOT capacitors (typically 100 nF ceramic) within 5 mm of the BOOT pin and corresponding PHASE pin to minimize parasitic inductance in the high-side gate drive loop. Keep the SVID traces (SVID_CLK, SVID_DAT, SVID_ALERT) routed as a 3-wire bus with 50 ohm characteristic impedance and isolated from the switching node traces by at least 3 mm to avoid coupling noise into the protocol. The CS1P/CS1N differential traces to the inductor DCR network must be a Kelvin connection - route them as a parallel pair directly across the inductor's DCR sense points.
Do not assume the SVID address strap (ADDR pin) defaults correctly - the IMVP8 specification requires different addresses for the main core rail and the graphics rail. Incorrect strapping causes the CPU to address the wrong rail and fail to power up. Per the onsemi datasheet, also ensure the RT resistor value matches the desired switching frequency within 1% tolerance; otherwise phase interleaving can drift out of the optimal 60-degree spacing and increase output ripple by 20-30%. The COMP and COMP2 compensation networks must be sized for the specific output L-C filter, not copied from the reference design.
Route the high-side gate drive traces (UGATE1-6) and low-side gate drive traces (LGATE1-6) as microstrip lines over the inner ground plane with controlled impedance; gate drive ringing causes shoot-through and efficiency loss. Keep the PHASE1-6 switching node traces as short and wide as possible - each millimeter of trace adds ~1 nH of parasitic inductance that resonates with the MOSFET Coss and creates voltage overshoot exceeding the BOOT voltage rating. Place the input ceramic capacitors (typically 4 x 22 uF MLCC) within 3 mm of the high-side MOSFET drains.
コンプライアンス情報
RoHS and REACH compliant per onsemi product page. The -Q1 variant is AEC-Q100 qualified for automotive; the standard MNTXG variant is not. Lead-free and halogen-free per onsemi environmental compliance data.
