PI3525-01-LGIZ - 48V to 5V/20A ZVS Buck Regulator SiP | Vicor
部品番号: PI3525-01-LGIZ ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $25.13 | $25.13 |
| 10 | $22.61 | $226.10 |
| 100 | $20.1 | $2,010.00 |
| 500 | $18.2 | $9,100.00 |
| 1,000 | $16.45 | $16,450.00 |
PI3525-01-LGIZ 概要
A ZVS buck regulator is a non-isolated, hard-switched synchronous step-down DC-DC converter whose high-side and low-side MOSFETs transition only when the switching-node voltage is at or near 0 V. This eliminates switching losses in the high-frequency domain and dramatically reduces EMI harmonics compared with conventional PWM buck converters. The ZVS buck sits inside the broader hierarchy: buck converter -> DC-DC switching regulator -> non-isolated POL converter -> power management IC. Vicor's PI33xx/PI35xx family are surface-mount SiPs designed for distributed power architectures where 48 V is stepped down locally at the point-of-load.
Key parametric features of the PI3525-01-LGIZ include 20 A continuous output current, 36-60 V input, programmable output (around 5 V for the -01 variant), >96% peak efficiency, parallel single-wire current sharing for higher-power rails, and over-current, over-temperature, and over-voltage protection. The 110-BLGA SiP footprint exposes a thermal pad that conducts heat directly into the PCB copper pours, eliminating the need for an external heatsink in properly laid-out boards.
Typical applications include 48 V telecom and datacom point-of-load conversion, industrial 48 V battery-fed motor and sensor rails, and high-current FPGA/DSP/processor core supplies where the upstream 48 V bus already exists. The -00/-01/-02 variants differ in factory output trim (5 V/12 V/15 V nominal respectively), allowing the same PCB layout to address multiple rails.
When designing with the PI3525-01-LGIZ, observe Vicor's recommended PCB layout (LGA land pattern, thermal via array under the package, and 4-layer board minimum with continuous inner copper planes). Use the TR pin to enable single-wire current sharing between paralleled units; route the share trace as a short, noise-immune differential pair to avoid ground-loop coupling.
This page synthesizes distributor pricing from DigiKey and Mouser, plus drop-in Vicor-family alternatives (PI3525-00-LGIZ, PI3526/PI3545 variants) that share the same 110-BLGA SiP footprint, offering a single-perspective view not assembled in the manufacturer datasheet alone.
ドロップイン代替品: PI3525-01-LGIZ — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
PI3525-00-LGIZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PI3525-02-LGIZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PI3526-01-LGIZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PI3545-00-LGIZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PI3525-01-LGIZ-R
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PI3525-01-LGIZ 最大定格＆電気的特性
| トポロジー | ZVS Buck (synchronous step-down, non-isolated) |
| Family | PI33xx / PI35xx ZVS Buck Regulator |
| 入力電圧範囲 | 36 V to 60 V |
| Output Voltage (factory trim, -01) | 5 V nominal (adjustable) |
| Continuous Output Current | 20 A |
| Peak Efficiency | >96% (typical at 48 Vin / 5 Vout) |
| Current Sharing | Single-wire parallel current sharing |
| Protection Features | OCP, OVP, OTP, input UVLO |
| 動作温度 | -40C to +125C (junction) |
| パッケージ | 110-BLGA System-in-Package (LGA SiP) |
| 実装タイプ | Surface Mount (LGA land pattern + thermal via array) |
| RoHS ステータス | Compliant (lead-free) |
| Isolation | Non-isolated (POL) |
PI3525-01-LGIZ 110-blga system-in-package (lga sip) ピン配置ガイド
PI3525-01-LGIZ (110-blga system-in-package (lga sip) パッケージ) のピン配置。 このパワーデバイスは、ゲート、ドレイン、ソース端子を備えています。非極性パッケージの場合、正確なピン1の向きとフットプリントの詳細については、メーカーのデータシートを参照してください。主な用途には、電源設計、モータ駆動、負荷スイッチングがあります。
詳細なピン配置データはありません: PI3525-01-LGIZ.
詳細は データシート をご参照ください。
主な用途
PI3525-01-LGIZ の用途: 6 件s: 48 V Telecom Point-of-Load Conversion, Industrial 48 V Battery-Fed Motor/Sensor Rails, Datacom Server and Storage Core Rails, 48 V PoE and Networking Equipment, Test and Measurement Instrumentation, High-Density FPGA/DSP Core Pre-Rails.
48 V Telecom Point-of-Load Conversion
The PI3525-01-LGIZ is purpose-built for stepping down a 48 V telecom backplane rail to a 5 V point-of-load rail at the card edge. With 36-60 V input headroom, 20 A continuous output, and >96% peak efficiency from zero-voltage-switching topology, it eliminates bulky intermediate 12 V buses in modern OCP and distributed-architecture datacom hardware. Place the SiP at the edge of the card with input bulk caps close to its input balls and output ceramic plus polymer bulk caps within 5 mm of the output balls to suppress switching-node ringing. The single-wire current-share pin allows two units to deliver up to 40 A for ASIC core rails without derating. Compared with a discrete two-stage 48V->12V->5V design, the ZVS buck SiP saves roughly 30% PCB area and one conversion stage, materially improving system efficiency at full load.
おすすめ
Industrial 48 V Battery-Fed Motor/Sensor Rails
Industrial battery banks and 48 V zonal architectures feed motion-control drivers, sensors, and PLC I/O that typically need regulated 5 V or 12 V rails. The PI3525-01-LGIZ's 36-60 V input window tracks a discharging 48 V battery across its full state-of-charge curve, while its -40C to +125C junction range and integrated OVP/OCP/OTP protection tolerate harsh factory-floor transients. The non-isolated POL topology suits systems where upstream isolation already exists; designers should place a TVS diode and reverse-polarity protection on the input. Efficiency above 96% translates directly into longer battery runtime and reduced heatsinking. Use the enable pin for sequenced power-up of motor drivers and analog front-ends.
おすすめ
Datacom Server and Storage Core Rails
Hyperscale server and storage platforms increasingly adopt 48 V direct-to-board power delivery to reduce I*R losses in busbars and reduce motherboard copper weight. The PI3525-01-LGIZ converts that 48 V bus to a 5 V intermediate rail feeding downstream multi-phase VRMs that power CPUs, GPUs, and NVMe controllers. With 20 A continuous current and parallel current-sharing support, designers can scale to 40-60 A rails by paralleling two or three SiPs on a shared thermal copper pour. The ZVS topology keeps EMI within server-rack limits without exotic filtering, while the 110-BLGA SiP's thermal pad conducts heat directly into the inner copper planes for sustained 20 A operation. Place the SiP adjacent to the downstream VRM input pins to minimize the high-current trace length.
おすすめ
48 V PoE and Networking Equipment
PoE-powered networking switches, 5G small-cell base stations, and outdoor radios use 48 V input from the building bus or remote power-injector. The PI3525-01-LGIZ accepts the full 36-60 V PoE/PoE+ window and produces a clean 5 V at 20 A for switch ASICs, PHYs, and fan controls. Zero-voltage switching eliminates the high-frequency harmonics that would otherwise require extra EMI filtering to meet FCC Part 15 and EN 55032 limits. The small 110-BLGA SiP footprint lets designers integrate multiple rails (5 V, 12 V, 15 V) on a compact switch blade by mixing PI3525-01, -00, and -02 variants. Use an upstream TVS plus fuse on the 48 V input for surge and over-current compliance with PoE power-up sequences.
おすすめ
Test and Measurement Instrumentation
Bench-top and ATE power supplies, oscilloscope front-ends, and precision data-acquisition instruments need low-noise, high-current 5 V rails that are tightly regulated and quiet. The PI3525-01-LGIZ's ZVS topology produces a relatively clean switching waveform with little ringing, and its high efficiency keeps thermal management simple in densely packed instruments. The 20 A continuous output is sufficient to power multi-channel ADC front-ends, FPGA processing boards, and display backlight drivers in a single ATE mainframe slot. Pair the SiP with a downstream linear LDO (e.g., a TPS7A47xx) if the load requires sub-millivolt noise floors for precision measurement. The -40C to +125C junction range supports chassis with restricted airflow.
おすすめ
High-Density FPGA/DSP Core Pre-Rails
Modern FPGAs and DSPs drawing 15-30 A at 0.85 V are fed by multi-phase VRMs whose input is typically 5 V or 12 V. The PI3525-01-LGIZ can provide that 5 V pre-rail from a 48 V bus with >96% efficiency, drastically reducing the input current demanded from the 48 V source compared with a 12 V pre-rail architecture. Placing the SiP adjacent to the multi-phase VRM input minimizes trace inductance and improves transient response. The single-wire current-share pin enables paralleling two units for higher-current pre-rails needed by high-density FPGAs. The integrated OVP/OTP protections shield expensive FPGA silicon from downstream faults.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: PI3525-01-LGIZ — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | PI3525-00-LGIZ | PI3525-02-LGIZ | PI3526-01-LGIZ | PI3545-00-LGIZ |
|---|---|---|---|---|---|
| Brand | Vicor | Vicor | Vicor | Vicor | Vicor |
| Package | 110-BLGA SiP | 110-BLGA SiP (same) | 110-BLGA SiP (same) | 110-BLGA SiP (same) | 110-BLGA SiP (same) |
| Input Voltage Range | 36 V to 60 V | 36 V to 60 V | 36 V to 60 V | 36 V to 60 V | 36 V to 60 V |
| Continuous Output Current | 20 A | 20 A | 20 A | ~30 A | ~30 A |
| Topology | ZVS Buck (SiP) | ZVS Buck (SiP) | ZVS Buck (SiP) | ZVS Buck (SiP) | ZVS Buck (SiP) |
| Current Sharing | Single-wire (TR pin) | Single-wire (TR pin) | Single-wire (TR pin) | Single-wire (TR pin) | Single-wire (TR pin) |
| Automotive (AEC-Q100) | Not qualified | Not qualified | Not qualified | Not qualified | Not qualified |
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant |
主な差別化要因
- ZVS topology delivers >96% peak efficiency from 48V to 5V （vs PI3525-00-LGIZ)
- Single-wire current sharing for parallel operation up to 40 A （vs PI3525-02-LGIZ)
- 20 A continuous in the 110-BLGA SiP footprint （vs PI3526-01-LGIZ)
設計ノート
Estimated: at 48 Vin -> 5 Vout and 20 A load, the PI3525-01-LGIZ dissipates roughly 4 W assuming 96% efficiency. The 110-BLGA SiP dissipates heat through its bottom thermal pad into the PCB copper; a 4-layer board with a continuous 2 oz inner copper pour and a thermal via array (0.3 mm drill, 1.2 mm pitch, filled) keeps the junction below 100C at full load. Without proper thermal via stitching the SiP will throttle via OTP.
Follow Vicor's recommended 110-BLGA land pattern from the mechanical drawing. Place input bulk capacitors within 5 mm of the input balls and output ceramic plus polymer bulk caps within 5 mm of the output balls. Use 4-layer stack-up with continuous inner ground/power planes; do not route sensitive analog signals under the SiP. The thermal via array must be plated and plugged or capped to prevent solder wicking during reflow.
Route the TR current-share pin as a short, isolated trace when paralleling units; avoid routing it near switching nodes. Keep the SGND (signal ground) bond to the power ground plane at a single point near the SiP. Minimize the high-current switching loop area (input cap -> high-side FET -> low-side FET -> input cap) to suppress EMI and ringing. Place a small RC snubber across the switching node if the layout forces a long loop.
Do not exceed 60 V on the input - the SiP has no over-voltage clamp above this threshold and may be permanently damaged. Do not hot-plug the input without proper inrush control: add a soft-start or hot-swap controller upstream. Do not operate without the minimum required external capacitors - the SiP relies on output capacitance for control-loop stability. Avoid mixing factory trim variants (-00/-01/-02) in current-sharing groups unless you accept the resulting load imbalance.
コンプライアンス情報
RoHS-compliant and lead-free per Vicor product page. Not AEC-Q100 qualified; contact Vicor for automotive-grade ZVS buck variants. Halogen-free status not explicitly stated in the verified web data.
