RT8071AZQW - 3A 2MHz Synchronous Step-Down Converter | Richtek
部品番号: RT8071AZQW ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $0.69 | $0.69 |
| 10 | $0.62 | $6.20 |
| 100 | $0.48 | $48.00 |
| 500 | $0.36 | $180.00 |
| 1,000 | $0.28 | $280.00 |
| 3,000 | $0.23 | $690.00 |
RT8071AZQW 概要
A synchronous step-down (buck) converter is a type of DC-DC switching regulator that steps a higher DC input voltage down to a lower regulated DC output voltage. Buck converters belong to the broader family of switch-mode power supplies (SMPS), which sit above linear regulators in efficiency but require an inductor, output capacitor, and feedback compensation. Within the SMPS hierarchy, the RT8071AZQW is positioned as a small-footprint, high-frequency point-of-load converter that targets portable, handheld, and embedded designs where PCB real estate is at a premium.
Key features include a typical peak current limit of approximately 4 A for robust transient handling, internal soft-start to limit inrush current, power-good indication for sequencing, and a typical quiescent current on the order of tens of microamperes to maximize light-load efficiency. The exposed thermal pad on the DFN-10 package provides a low thermal resistance path, allowing the device to deliver 3 A continuously without an external heatsink when the PCB copper area is properly sized.
The RT8071AZQW uses voltage-mode PWM control with internal compensation, which simplifies the external BOM to an input capacitor, an inductor, an output capacitor, and two feedback resistors. The 2 MHz switching frequency keeps the converter above the AM broadcast band, avoiding audible interference in audio-adjacent designs. Internal synchronous rectification eliminates the external Schottky diode required by older buck topologies, improving efficiency at light loads.
Typical applications include portable media players, set-top boxes, blade servers, notebook computers, and distributed 5V POL rails in networking and storage equipment. The wide 2.7V-5.5V input range covers single-cell Li-ion, USB, and 3.3V/5V system bus rails, while the adjustable output supports DDR memory, FPGA core rails, and I/O supplies.
When designing with this part, keep the input ceramic capacitor within 2 mm of the VIN and GND pins, route the feedback trace away from the SW node, and provide at least four thermal vias under the exposed pad to keep junction temperature within ratings at full 3 A load.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical PCB layout notes that go beyond the manufacturer datasheet, enabling faster design-in and BOM decisions.
ドロップイン代替品: RT8071AZQW — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
RT8068AZQW
✅ ドロップイン📋 参考代替品（カタログ未掲載）
RT8070AZQW
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
RT8071AZQW-R
✅ ドロップイン📋 参考代替品（カタログ未掲載）
RT8071AZQW 最大定格＆電気的特性
| トポロジー | Synchronous Step-Down (Buck) |
| 入力電圧範囲 | 2.7 V to 5.5 V |
| 出力電圧範囲 | 0.6 V to VIN (adjustable) |
| 最大出力電流 | 3 A |
| スイッチング周波数 | 2 MHz (typical) |
| Switch Type | Internal P-channel high-side + N-channel low-side MOSFETs |
| Control Method | Voltage-mode PWM with internal compensation |
| ソフトスタート | Internal |
| Power Good Indicator | Yes |
| 動作温度範囲 | -40C to +85C |
| パッケージ | DFN-10-EP (3x3 mm) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
RT8071AZQW ピン構成
| ピン 1 | PGND — Power ground for internal low-side MOSFET |
| ピン 2 | VIN — Input supply voltage (2.7V to 5.5V) |
| ピン 3 | EN — Enable input (active high) |
| ピン 4 | FB — Feedback voltage sense input |
| ピン 5 | AGND — Analog ground |
| ピン 6 | PGOOD — Power good indicator output |
| ピン 7 | COMP — Compensation node (internal compensation, leave open) |
| ピン 8 | SW — Switch node (inductor connection) |
| ピン 9 | SW — Switch node (inductor connection) |
| ピン 10 | VIN — Input supply voltage (tie to pin 2) |
主な用途
RT8071AZQW の用途: 6 件s: Portable Media Players, Set-Top Box Point-of-Load, Blade Server POL Regulation, Notebook Computer Core Rails, DDR Memory Termination, FPGA Core Power Rail.
Portable Media Players
The RT8071AZQW's 3A output in a 3x3 mm DFN-10-EP package makes it ideal for portable media players that need a compact 3.3V to 1.xV core rail. Its 2.7V-5.5V input covers single-cell Li-ion (3.0V-4.2V) directly, eliminating an intermediate boost stage. The 2 MHz switching frequency keeps the inductor and output caps small (~1uH, 22uF), and synchronous rectification delivers >90% efficiency at typical 1-2A loads, extending battery life during playback.
おすすめ
Set-Top Box Point-of-Load
Set-top boxes require multiple low-voltage rails (1.0V core, 1.5V DDR, 3.3V I/O) generated from a 5V or 12V intermediate bus. The RT8071AZQW steps 5V down to sub-volt rails at 3A with >90% efficiency, eliminating the thermal challenge of a linear regulator at that power level. Its exposed-pad DFN-10 package dissipates heat through PCB copper, and the internal compensation network keeps the external BOM to just an inductor, input/output caps, and feedback resistors.
おすすめ
Blade Server POL Regulation
Blade servers pack high-current CPUs, ASICs, and DDR memory into confined chassis where 12V or 5V intermediate buses feed point-of-load (POL) converters at the load. The RT8071AZQW delivers 3A from a 5V bus to memory and support ASICs, where its 2 MHz switching frequency allows placement close to the load with minimal EMI concerns. The exposed thermal pad supports continuous 3A operation when stitched to internal power planes, and the PGOOD output enables sequencing with adjacent regulators.
おすすめ
Notebook Computer Core Rails
Notebook platforms generate CPU core, graphics, and chipset rails from the 5V or 3.3V system bus using compact synchronous buck converters. The RT8071AZQW's 3A capability covers many sub-system rails (chipset, audio codec, embedded controller), while its DFN-10-EP 3x3 footprint fits under BGA packages on dense motherboards. The 2 MHz switching frequency exceeds the AM band, preventing audible interference, and the internal soft-start minimizes inrush stress on upstream USB or battery sources.
おすすめ
DDR Memory Termination
DDR memory requires accurate low-voltage rails (typically 1.2V-1.35V for DDR4, 1.0V for LPDDR) with tight regulation and low noise. The RT8071AZQW generates these rails from the 3.3V or 5V memory bus at 3A, sufficient for 4-8 GB memory subsystems. Its voltage-mode PWM control with internal compensation simplifies design, while the PGOOD output signals the memory controller that the rail is stable before commencing write cycles.
おすすめ
FPGA Core Power Rail
Small-to-medium FPGAs (Cyclone 10 LP, Lattice ECP5, Artix-7 class) require 0.9V-1.2V core rails at 2-4 A from a 3.3V or 5V bus. The RT8071AZQW delivers this 3A point-of-load rail in a 3x3 mm footprint that fits beneath the FPGA or beside it on the same PCB layer. The exposed pad enables continuous 3A operation on standard 4-layer boards with adequate copper, and the 2 MHz switching rate avoids interference with sensitive PLL/VCO power supply inputs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: RT8071AZQW — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | RT8068AZQW | RT8070AZQW | RT8071AZQW-R |
|---|---|---|---|---|
| Brand | Richtek | Richtek - same | Richtek - same | Richtek - same |
| Package | DFN-10-EP (3x3) | DFN-10-EP (3x3) - same | DFN-10-EP (3x3) - same | DFN-10-EP (3x3) - same |
| Topology | Synchronous Buck | Synchronous Buck | Synchronous Buck | Synchronous Buck |
| Input Voltage Range | 2.7V to 5.5V | 2.7V to 5.5V | 2.7V to 5.5V | 2.7V to 5.5V |
| Switching Frequency | 2 MHz (typ) | 2 MHz (typ) | 2 MHz (typ) | 2 MHz (typ) |
| Output Voltage Range | 0.6V to VIN (adj.) | 0.6V to VIN (adj.) | 0.6V to VIN (adj.) | 0.6V to VIN (adj.) |
主な差別化要因
- 3A in a 3x3 mm DFN-10-EP footprint （vs RT8068AZQW)
- Same family, 100% drop-in identical-die option （vs RT8071AZQW-R)
- Synchronous rectification (no Schottky needed) （vs RT9297GQW)
設計ノート
Estimated: at VIN=5V, VOUT=1.8V, IOUT=3A, the RT8071AZQW dissipates approximately (5V-1.8V)*3A = 9.6W minus inductor/conduction losses. The DFN-10-EP package requires at least four thermal vias under the exposed pad (0.3mm drill, 1mm pitch) to a top-layer copper pour of ~1 square inch. Without this, junction temperature can exceed +125C at full 3A load. Place input ceramic capacitors (10uF X5R minimum) within 2 mm of the VIN and PGND pins.
Keep the SW node copper area minimal to reduce EMI radiation; this is a 2 MHz switching node so any copper pours connected to SW act as radiators. Route the FB trace away from the SW node and the inductor to avoid noise coupling. The AGND pin should connect to a quiet ground island that ties to PGND at a single point near the output capacitor return. The exposed thermal pad must be soldered to a copper pour that is stitched to the inner ground plane with multiple vias.
Do not exceed the absolute maximum VIN of 6V (per datasheet). Using low-ESR ceramic output capacitors (X5R/X7R, 22uF or larger) is mandatory; tantalum or electrolytic capacitors can cause instability with the internal compensation network. The EN pin has an internal pull-up; tie to VIN through a 100k resistor if not driven externally. The PGOOD output is open-drain and requires an external pull-up resistor (typically 100k to VIN).
Inductor selection: 1.0uH to 2.2uH with >= 4A saturation current rating and < 30 mΩ DCR for best efficiency. Lower inductance gives faster transient response but higher ripple; higher inductance gives lower ripple but slower transient response. Output capacitor: 22uF to 47uF X5R/X7R ceramic; derate ceramic capacitance for DC bias (a 22uF 6.3V cap may be only 12uF at 1.8V bias). Input capacitor: 10uF X5R ceramic minimum, plus a 0.1uF high-frequency bypass close to the IC.
コンプライアンス情報
RoHS and lead-free status confirmed per JLCPCB and LCSC product listings (C3034118). AEC-Q100 not qualified - for automotive applications, use an AEC-Q100 grade part. Halogen-free status not explicitly stated in the verified web data.
