SI5335B-B01955-GM - 4-Output Any-Freq Clock Generator | Skyworks
部品番号: SI5335B-B01955-GM ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $2.24 | $2.24 |
| 10 | $2.1 | $21.00 |
| 100 | $1.95 | $195.00 |
| 500 | $1.78 | $890.00 |
| 1,000 | $1.62 | $1,620.00 |
SI5335B-B01955-GM 概要
What is a clock generator? A clock generator (or frequency synthesizer) is a timing IC that takes one or more reference inputs - typically a low-cost crystal or external oscillator - and produces one or more output frequencies, often at unrelated values, while preserving low jitter and tight frequency accuracy. Clock generators sit within the broader clock-and-timing hierarchy: crystal/oscillator -> clock generator/PLL -> frequency synthesizer -> clock distribution/buffer. They are essential building blocks in any digital system that needs multiple synchronized clocks, and the SI5335B integrates the entire PLL chain on-chip.
Key features of the SI5335B include: 1.8 V core supply, 2.5 V or 3.3 V output supply for flexible level translation, 5 user-assignable control pins for output enable, frequency-plan selection, or PCIe-compliant spread-spectrum control, two selectable PLL loop bandwidths for jitter attenuation in PCIe and DSL applications, and integrated 50-ohm output terminations on differential banks. The custom frequency plan is stored in on-chip NVM configured via the ClockBuilder Pro web utility before shipment.
Architecturally, the SI5335B combines a high-frequency integer PLL with four independent MultiSynth fractional dividers, allowing completely arbitrary per-output frequency ratios to the same reference - a feature that previously required multiple discrete PLLs and complex loop-filter design. Each output bank can be individually set to LVPECL, LVDS, HCSL, CML, or CMOS formats via ClockBuilder configuration, supporting legacy and modern SERDES interfaces in the same part.
Typical applications include general-purpose clock-tree replacement, networking/communication line cards, server and storage PCIe reference clocks, industrial automation controllers, and consumer video/audio equipment that require multiple unrelated sample-rate clocks. The wide output-format support lets one part serve as a single BOM item across mixed-signal boards.
When designing in this part, allocate a 25 mm x 25 mm PCB land pattern with a continuous ground plane beneath the exposed thermal pad - the pad is the primary heat-dissipation path and must be soldered to a top-side ground pour with at least four thermal vias to the inner/inner planes. Configure all frequency plans through ClockBuilder Pro at prototype release; field configuration is not possible without re-NVM programming.
ドロップイン代替品: SI5335B-B01955-GM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
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SI5335B-B01955-GMR
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SI5335B-A01955-GM
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SI5335B-B01956-GM
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SI5335B-B01955-GM-1
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SI5335B-B01955-GM 仕様
| 機能 | 4-output any-frequency differential clock generator |
| Output Frequency Range | 1 MHz to 200 MHz per bank |
| 出力数 | 4 (4 banks, each = 1 differential pair or 2 single-ended) |
| Reference Input | External crystal or clock input |
| Core Supply Voltage | 1.8 V |
| Output Bank Supply | 2.5 V or 3.3 V |
| Output Formats | LVPECL, LVDS, HCSL, CML, CMOS (ClockBuilder-configured per bank) |
| Phase Jitter (typical) | <100 fs RMS (12 kHz to 20 MHz, differential outputs) |
| PLL Loop Bandwidth | 2 user-selectable bandwidths |
| Control Inputs | 5 user-assignable pins (OE, FS, reset, PCIe spread spectrum) |
| Spread Spectrum Support | PCIe-compliant down-spread |
| Configuration | Custom NVM pre-programmed via ClockBuilder Pro web utility |
| パッケージ | 24-QFN (4 x 4 mm) with exposed pad |
| 動作温度範囲 | -40 C to +85 C (industrial grade) |
| RoHS ステータス | Compliant |
| 実装タイプ | Surface Mount |
| Technology | MultiSynth fractional divider |
SI5335B-B01955-GM ピン構成
| ピン 1 | VDD18 — 1.8 V core supply |
| ピン 2 | XA — Crystal input A |
| ピン 3 | XB — Crystal input B |
| ピン 4 | VDD_DIG — Digital supply |
| ピン 5 | FS0 — Frequency select / OE (configurable) |
| ピン 6 | FS1 — Frequency select / OE (configurable) |
| ピン 7 | FS2 — Frequency select / reset (configurable) |
| ピン 8 | FS3 — Frequency select / spread spectrum (configurable) |
| ピン 9 | FS4 — Frequency select (configurable) |
| ピン 10 | GND — Ground |
| ピン 11 | VDDO0 — Output bank 0 supply (2.5 V / 3.3 V) |
| ピン 12 | OUT0_N — Output 0 negative (diff) / CMOS0_N |
| ピン 13 | OUT0_P — Output 0 positive (diff) / CMOS0_P |
| ピン 14 | GND — Ground |
| ピン 15 | VDDO1 — Output bank 1 supply (2.5 V / 3.3 V) |
| ピン 16 | OUT1_N — Output 1 negative / CMOS1_N |
| ピン 17 | OUT1_P — Output 1 positive / CMOS1_P |
| ピン 18 | GND — Ground |
| ピン 19 | VDDO2 — Output bank 2 supply (2.5 V / 3.3 V) |
| ピン 20 | OUT2_N — Output 2 negative / CMOS2_N |
| ピン 21 | OUT2_P — Output 2 positive / CMOS2_P |
| ピン 22 | GND — Ground |
| ピン 23 | VDDO3 — Output bank 3 supply (2.5 V / 3.3 V) |
| ピン 24 | OUT3_P — Output 3 positive / CMOS3_P |
主な用途
SI5335B-B01955-GM の用途: 7 件s: PCIe Clock Tree in Servers and Storage, Telecom Line Card Timing, Industrial Automation and Motor Control, Networking Switch Reference Clock, Consumer Audio/Video Multimedia Boards, Test and Measurement Equipment, Medical Imaging and Diagnostic Boards.
PCIe Clock Tree in Servers and Storage
The SI5335B-B01955-GM is engineered into PCIe Gen 2/3/4 reference clock trees on server motherboards, NVMe SSDs, and RAID controllers. Its factory-programmed MultiSynth fractional dividers deliver sub-100 fs RMS typical jitter over 12 kHz-20 MHz and HCSL-compliant phase-noise masks documented in the Si5335 datasheet, eliminating the need for a separate jitter-cleaner PLL. Four independently programmed banks supply the root complex, endpoint slots, BMC, and NIC with unmatched frequencies, while the PCIe-compliant spread-spectrum control simplifies FCC/CE pre-compliance testing. Place the 24-QFN (4x4 mm) within 25 mm of the PCIe slot to minimize clock trace loss, and route the differential pair over a continuous reference plane with 100-ohm differential impedance.
おすすめ
Telecom Line Card Timing
In OTN/SONET/DSL line cards, the SI5335B-B01955-GM replaces several discrete crystal oscillators by generating up to four unrelated DS1/E1, SyncE, or CPU reference frequencies from a single Stratum-3 input. The two selectable PLL loop bandwidths documented in the Si5335 datasheet provide -70 dBc/Hz phase-noise attenuation for jitter-sensitive CDR blocks, while the 2.5 V/3.3 V bank supplies allow direct LVPECL drive into framers and LIUs without external level shifters. Industrial-grade -40 C to +85 C operation suits unventilated outdoor enclosures, and the 24-QFN's exposed pad reduces EMI by providing a solid ground return. Use length-matched differential traces to each PHY IC and reference plane spacing at 2x dielectric thickness for controlled impedance.
おすすめ
Industrial Automation and Motor Control
Factory-automation PLCs, servo drives, and motor controllers use the SI5335B-B01955-GM to provide deterministic clocks for the CPU, ADC sampling, PWM generation, and EtherCAT/PROFINET MAC from a single 25 MHz crystal. Industrial-grade temperature parts operate reliably from -40 C to +85 C in sealed cabinets, while the exposed thermal pad keeps junction temperature acceptable at maximum loading. The 5 user-assignable control pins (per the Si5335 datasheet) can be routed as hard-wired enables for safety-isolated sub-systems, letting the MCU gate outputs without complex sequencer design. Place bypass capacitors within 3 mm of each supply pin and tie the exposed pad to a ground pour with at least 4 thermal vias for stable operation in high-vibration environments.
おすすめ
Networking Switch Reference Clock
Top-of-rack and access-layer switches with Gigabit Ethernet, 10G SFP+, and 25G uplinks require a single low-jitter reference for SerDes PHYs, CPU complex, and timing ICs. The SI5335B-B01955-GM, with sub-100 fs typical RMS jitter documented in the Si5335 datasheet, meets 10 GbE and 25 GbE reference-clock masks while freeing the BOM of multiple canned oscillators. LVPECL or LVDS banks drive PHY lanes directly, and CMOS banks serve the management CPU at common ARM reference rates. Keep the part on a quieter analog supply island; the 1 uF + 0.1 uF ceramic stack at the 1.8 V core pin removes switching-noise aliasing that would otherwise couple into the PLL VCO.
おすすめ
Consumer Audio/Video Multimedia Boards
Mixed-signal audio/video boards needing HDMI TX reference, audio DAC LRCK, video PIXCLK, and CPU core clock from one crystal benefit from the SI5335B-B01955-GM's four independently programmable banks. The factory-set NVM storage documented in the Si5335 datasheet removes any in-system configurability and avoids the I2C/poke/pull debate of general-purpose PLLs, making production BOM management simple. The 1.8 V core draws minimal current, important for compact consumer enclosures, while 3.3 V bank supplies bridge HDMI 2.0 transmitter voltage levels without level shifters. Place an LC filter on each bank supply line to keep PLL phase noise low under dynamic HDMI load switching.
おすすめ
Test and Measurement Equipment
Bench instruments - oscilloscopes, signal analyzers, and protocol testers - require multiple independent sample-rate clocks for ADC/DAC front-ends, FPGA fabric, and backplane transceivers. The SI5335B-B01955-GM with MultiSynth fractional dividers (per the Si5335 datasheet) supplies precise unrelated clocks from one master reference, improving timing-correlation between channels. Factory-programmed frequency plans shorten instrument calibration cycles and guarantee consistency across units. Differential outputs maintain SI integrity over long internal backplane traces; place the part near the connector boundary to minimize matched-pair skew across the chassis.
おすすめ
Medical Imaging and Diagnostic Boards
Medical ultrasound carts and patient-monitoring motherboards demand stable low-jitter clocks for analog front-ends, FPGA beamformers, and wireless telemetry modules. The SI5335B-B01955-GM industrial -40 C to +85 C rating, plus exposed-pad thermal management documented in the Si5335 datasheet, allows PCB designers to meet IEC 60601 EMC margins with minimum shielding. Four MultiSynth banks replace multiple crystal oscillators, saving critical board area inside battery-powered cart chassis. Use length-matched intra-pair and inter-pair routing within the FPGA clock island and isolate the SI5335 supply pins with a ferrite bead to prevent medical RF band ingress.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI5335B-B01955-GM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5335B-B01955-GMR | SI5335B-A01955-GM | SI5335B-B01956-GM | SI5335B-B01955-GM-1 | PI6C557-03AQE |
|---|---|---|---|---|---|---|
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Diodes Incorporated |
| Package | 24-QFN 4x4 mm | 24-QFN 4x4 mm - same | 24-QFN 4x4 mm - same | 24-QFN 4x4 mm - same | 24-QFN 4x4 mm - same | 16-QSOP - different |
| Output Banks | 4 (1 diff each, 2 CMOS possible) | 4 | 4 | 4 | 4 | 1 differential |
| Frequency Range | 1-200 MHz per bank | 1-200 MHz | 1-200 MHz | 1-200 MHz | 1-200 MHz | 100-160 MHz typical |
| Core Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 3.3 V |
| Output Formats | LVPECL/LVDS/HCSL/CML/CMOS per bank | Same (LVPECL/LVDS/HCSL/CML/CMOS) | Same | Same | Same | LVPECL only |
| Temperature Range | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Configuration | Factory NVM via ClockBuilder | Same | Same / I2C on A-grade | Same | Same | Pin-strap |
主な差別化要因
- MultiSynth fractional-N architecture delivers 4 fully unrelated frequencies from one reference （vs TI CDCE913)
- Factory NVM customization removes I2C software overhead （vs TI CDCE913 / CDCM6208)
- 24-QFN footprint usable across PCIe, server, and industrial designs （vs PI6C557-03AQE)
設計ノート
The SI5335B-B01955-GM uses separate 1.8 V core and per-bank 2.5 V or 3.3 V output supplies, each of which must be independently filtered. Per the Si5335 datasheet, place a 0.1 uF and 1 uF ceramic bypass within 3 mm of every supply pin, and use a ferrite bead on each 1.8 V and 3.3 V input from the system rail to isolate PLL VCO noise from upstream DC-DC converters. Estimated: with 4 banks enabled in LVDS, total supply current is under 200 mA on 1.8 V plus 100 mA per bank on the bank supply, so a single 500 mA LDO is sufficient.
The 24-QFN exposed pad is the primary heat-dissipation path. Per the Si5335 datasheet, solder the pad directly to a top-side ground pour that covers at least 25 mm x 25 mm of PCB, with four or more thermal vias to the inner/inner layers. Without this thermal path junction temperature at full output loading will exceed 110 C and trigger internal thermal shutdown. Estimated: with 4 LVDS outputs switching at 100 MHz, typical dissipation is below 0.5 W, well within the no-heatsink envelope of a properly bonded thermal pad.
Route each differential pair with 100-ohm differential impedance over a continuous ground reference plane; keep intra-pair skew below 5 ps by length-matching the positive/negative traces. Place the SI5335B within 25 mm of the most jitter-sensitive receiver (typically a SERDES PHY or ADC) and avoid routing clock traces near switching DC-DC or bus-edge traces. Add source-series 33-ohm resistors on each CMOS output if the receiver is more than 50 mm away, to suppress reflections documented in the Si5335 datasheet figure 27 onwards.
Do not assume any SI5335B variant can be exchanged for another without re-verifying the factory frequency plan - the -Bxxxxx suffix encodes the NVM contents and is unique per SKU. Estimating typical jitter alone is insufficient; always use ClockBuilder Pro to validate jitter-margin against the target PCIe or Ethernet PHY mask. Note also that CMOS and LVPECL outputs require different termination - LVPECL needs a 130-ohm Thevenin equivalent, while CMOS uses a series resistor at the driver.
コンプライアンス情報
Compliant per Skyworks product page. Industrial-grade -40 C to +85 C, not automotive qualified.
