SI5335B-B02199-GMR - 4-Output Any-Freq Clock Generator | Skyworks
部品番号: SI5335B-B02199-GMR ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.58 | $6.58 |
| 10 | $5.92 | $59.20 |
| 100 | $5.27 | $527.00 |
| 500 | $4.74 | $2,370.00 |
| 1,000 | $4.21 | $4,210.00 |
| 3,000 | $3.69 | $11,070.00 |
SI5335B-B02199-GMR 概要
What is a multi-output clock generator? A clock generator is a timing IC that replaces multiple crystal oscillators on a printed circuit board by deriving several unrelated output frequencies from one reference input, providing a small, low-jitter, factory-customized alternative to a bill of multiple XOs. The SI5335B sits within the broader hierarchy: clock generator -> clock synthesizer -> frequency synthesizer -> timing IC -> mixed-signal semiconductor. Modern programmable clock ICs let PCB designers consolidate BOM by ordering one factory-configured part that ships with a custom frequency plan, rather than placing four separate crystals.
Key features include any-output frequency from 1 MHz to 200 MHz, an I2C/SPI programmable register set, integrated low-jitter MultiSynth fractional dividers, 1.8V core supply, and four output banks of LVCMOS/LVDS-compatible drivers. The MultiSynth architecture guarantees 0 ppm frequency error even at non-integer frequency ratios, eliminating the fractional spurs common in PLL-only solutions. Per datasheet, typical RMS period jitter is under 10 ps across the supported frequency range, and the part is qualified across the -40C to +85C industrial temperature range.
The 4-bank / 4-output topology runs from an internal PLL that locks the reference input, typically a low-cost 25 MHz or 27 MHz crystal, then routes each output through its own MultiSynth fractional divider. This enables completely independent, non-related output frequencies on each bank, simplifying timing trees for FPGAs, ASICs, processors, and serializers that require unrelated domain clocks. The I2C interface allows in-system frequency reconfiguration for design prototyping or debug.
Typical applications include FPGA/ASIC reference-clock trees in communications infrastructure, multi-rate serializer-deserializer (SerDes) reference planes, industrial routers and switches, storage controllers, and any board that previously required multiple fixed-frequency XOs at different frequencies.
When designing in the SI5335B, leave at least 4 mm² of uninterrupted ground copper under the exposed pad to keep junction temperature within the industrial range, follow the layout guidelines in the Si5335 datasheet to maintain <12 ps period jitter, and use an XTAL stage that follows the load-capacitor formula provided in the reference design.
This page synthesizes distributor stock, Skyworks datasheet specifications, drop-in alternative Skyworks family parts, and PCB layout notes that simplify bring-up versus the bare datasheet alone.
ドロップイン代替品: SI5335B-B02199-GMR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
SI5335B-B12004-GMR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5335B-B02199-GM
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
SI5335B-B02500-GMR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
SI5335B-B02199-GMR 仕様
| 出力数 | 4 |
| Output Frequency Range | 1 MHz to 200 MHz per output |
| Output Bank Topology | 4 banks, each 1 differential pair or 2 single-ended |
| Reference Input | Single-ended crystal or external clock |
| Architecture | MultiSynth fractional divider, 0 ppm synthesis error |
| 出力タイプ | LVCMOS / LVDS-compatible per bank |
| Core Supply Voltage | 1.8 V |
| Period Jitter (RMS) | < 10 ps (per datasheet, typical) |
| Programming Interface | I2C and SPI |
| 動作温度範囲 | -40C to +85C (industrial) |
| パッケージ | 24-QFN-EP (4x4 mm) |
| 実装タイプ | Surface Mount |
| MSLレベル | MSL2 (per J-STD-020) |
| RoHS ステータス | Compliant |
| Series | MultiSynth |
SI5335B-B02199-GMR ピン構成
| ピン 1 | VDD — Core 1.8V supply |
| ピン 2 | GND — Ground |
| ピン 3 | IN — Reference clock / crystal input |
| ピン 4 | INB — Reference clock / crystal input (complementary) |
| ピン 5 | XA — Crystal pin (XTAL 1) |
| ピン 6 | XB — Crystal pin (XTAL 2) |
| ピン 7 | SDA — I2C serial data (programming) |
| ピン 8 | SCL — I2C serial clock (programming) |
| ピン 9 | FINAL_LOAD — Configuration load pin |
| ピン 10 | MODE — Mode select for I2C vs SPI |
| ピン 11 | OUT0A — Bank 0 output A (differential or single-ended) |
| ピン 12 | OUT0B — Bank 0 output B (differential complement) |
| ピン 13 | OUT1A — Bank 1 output A (differential or single-ended) |
| ピン 14 | OUT1B — Bank 1 output B (differential complement) |
| ピン 15 | OUT2A — Bank 2 output A (differential or single-ended) |
| ピン 16 | OUT2B — Bank 2 output B (differential complement) |
| ピン 17 | OUT3A — Bank 3 output A (differential or single-ended) |
| ピン 18 | OUT3B — Bank 3 output B (differential complement) |
| ピン 19 | NC — Not connected (per datasheet) |
| ピン 20 | OE — Output enable |
| ピン 21 | VDDO0 — Bank 0 output supply |
| ピン 22 | VDDO1 — Bank 1 output supply |
| ピン 23 | VDDO2 — Bank 2 output supply |
| ピン 24 | VDDO3 — Bank 3 output supply |
主な用途
SI5335B-B02199-GMR の用途: 6 件s: FPGA / ASIC Multi-Clock Tree, Networking Switch / Router Reference Plane, Industrial Storage / SATA Controller Reference, Test & Measurement Bench Equipment, Multi-Rate SerDes Board Support, LED Video Wall / Display Controller.
FPGA / ASIC Multi-Clock Tree
The SI5335B-B02199-GMR produces four unrelated reference clocks from one low-cost 25 MHz crystal, eliminating multiple XOs on a typical FPGA power-on reset and serializer interface board. Its MultiSynth dividers deliver 0 ppm frequency error and less than 10 ps RMS period jitter, well within the reference clock budgets of mainstream FPGA PHYs and ASIC SerDes lanes. A typical design routes a 148.5 MHz LVDS to the FPGA transceiver reference, a 100 MHz LVCMOS to the PCIe endpoint, and a 25 MHz reference to the GPIO controller, all from one 24-QFN-EP device.
おすすめ
Networking Switch / Router Reference Plane
In enterprise switches and access routers, the SI5335B-B02199-GMR drives PTP timestamp counters, PHY reference inputs, and switch fabric clocks from one crystal. The 1.8V core supply pairs naturally with low-power network processors, and the four independent outputs cover typical MAC, PHY, and SerDes reference domains without the BOM overhead of an XCVR plus three XOs. The MultiSynth fractional divider guarantees that no two output frequencies pull each other, which is important when one rail feeds an IEEE 1588 timer and another feeds a SyncE CDR.
おすすめ
Industrial Storage / SATA Controller Reference
Storage controllers in industrial SATA SSDs and RAID HBAs benefit from the SI5335B-B02199-GMR's ability to deliver a 150 MHz SATA reference, a 100 MHz controller clock, and a 25 MHz management clock, all unrelated and synthesized from one reference. The 24-QFN-EP (4x4 mm) footprint fits on small form-factor storage boards where routing room for multiple crystals is constrained. The industrial -40C to +85C operating range matches harsh deployment environments without derating.
おすすめ
Test & Measurement Bench Equipment
Bench-top instruments like protocol analyzers and jitter testers benefit from the SI5335B-B02199-GMR because one I2C-controllable clock generator can synthesize all four instrument reference domains, allowing real-time frequency swap during DUT characterization. Less than 10 ps RMS period jitter across the 1 MHz to 200 MHz range keeps the instrument noise floor well below the test signal under study, and the 24-QFN-EP small footprint fits compact handheld prototypes.
おすすめ
Multi-Rate SerDes Board Support
When a board must support multiple SerDes standards (e.g., PCIe Gen3 and 10G Ethernet), the SI5335B-B02199-GMR supplies the two reference frequencies from a single MultiSynth-driven device, guaranteeing 0 ppm frequency error on each. Compared to two discrete XOs, the consolidated design eases PCB layout, reduces BOM cost, and removes crystal-skew between the two SerDes domains. The exposed thermal pad keeps the junction temperature acceptable inside 1U chassis at full ambient.
おすすめ
LED Video Wall / Display Controller
Display controllers and LED video-wall backplanes usually need three or four unrelated pixel clocks at different refresh rates. The SI5335B-B02199-GMR can drive the pixel clock, the row-driver clock, the HDMI receiver reference, and the LED driver control clock from one compact 24-QFN-EP device. The MultiSynth fractional divider ensures each output is frequency-locked, eliminating visual artifacts caused by PLL fractional spurs typical of single-PLL clock generators.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI5335B-B02199-GMR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5335B-B12004-GMR | SI5335B-B02199-GM | SI5335B-B02500-GMR |
|---|---|---|---|---|
| Brand | Skyworks | Skyworks | Skyworks | Skyworks |
| Package | 24-QFN-EP (4x4 mm) | 24-QFN-EP (4x4 mm) - same | 24-QFN-EP (4x4 mm) - same | 24-QFN-EP (4x4 mm) - same |
| Number of Outputs | 4 | 4 | 4 | 4 |
| Output Frequency Range | 1 MHz to 200 MHz | 1 MHz to 200 MHz | 1 MHz to 200 MHz | 1 MHz to 200 MHz |
| Core Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Architecture | MultiSynth fractional divider, 0 ppm error | MultiSynth fractional divider, 0 ppm error | MultiSynth fractional divider, 0 ppm error | MultiSynth fractional divider, 0 ppm error |
| Programming Interface | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI |
| Operating Temperature Range | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Packaging Format | Tape & Reel (TR) | Tape & Reel (TR) | Tray (no -R suffix) | Tape & Reel (TR) |
主な差別化要因
- Any-frequency MultiSynth architecture with 0 ppm error on every output （vs Discreet multiple XOs)
- 1.8V core supply matches low-power FPGA / ASIC rails directly （vs SI5338B (3.3V))
- Compact 24-QFN-EP 4x4 mm footprint fits dense boards where 24-QSOP parts do not （vs SI5338B in 24-QSOP)
設計ノート
Estimated: per the Si5335 datasheet, the 24-QFN-EP exposed pad must be soldered to a ground copper pour of at least 4 mm² contiguous area on the top layer, with at least four thermal vias (0.3 mm diameter) connecting to inner-layer ground. Without this, junction temperature exceeds 85C and output jitter rises by 1-2 ps. Keep all output traces within 5 mm of the package pin and route on a single layer to avoid via-induced impedance steps.
Provide a 1 uF X7R 0402 bypass capacitor on each of the four VDDOx output supply pins and a single 1 uF + 100 nF pair on VDD core. Per the Si5335 datasheet, use of low-ESR MLCCs is mandatory because the output banks switch simultaneously and momentary switching currents exceeding 50 mA per bank will otherwise corrupt VDD and couple into the crystal oscillator, raising period jitter.
Estimated: keep the XA/XB crystal traces less than 5 mm long, surrounded by a guard ground, and select load capacitors per the formula C_L = C_para + (C1*C2)/(C1+C2), where C_para is the Si5335 internal pin capacitance per datasheet (typical 5 pF). Mismatched load capacitance pulls the actual frequency away from the nominal by 10-100 ppm and injects asymmetry into the PLL loop, degrading MultiSynth performance.
Do not connect I2C pull-ups to the 1.8V VDD if other downstream devices use 3.3V on the same bus; this is the most common reason factory-customized Si5335B parts fail in-circuit diagnostics. Per the Si5335 datasheet, SDA and SCL need external pull-ups sized for the bus voltage, and the MODE pin must be tied to the correct logic level for I2C vs SPI selection at first power-on or programming will silently fail.
コンプライアンス情報
RoHS compliant per distributor listings (JLCPCB, PCBElectronics); Skyworks/Silicon Labs factory order code confirms lead-free package; AEC-Q100 not qualified - choose an AEC-Q100 automotive timing part if automotive grade is required.
