SI5338A-B-GM - 710MHz Any-Frequency Clock Generator, 24-QFN | Skyworks
部品番号: SI5338A-B-GM ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $14.45 | $14.45 |
| 10 | $13.01 | $130.10 |
| 100 | $11.56 | $1,156.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.25 | $9,250.00 |
| 2,500 | $8.5 | $21,250.00 |
SI5338A-B-GM 概要
A clock generator is a timing integrated circuit that produces one or more precise reference frequencies from a single input reference, eliminating the need for multiple crystal oscillators. Clock generators sit hierarchically under timing ICs, which in turn belong to the broader category of power management and clock tree devices. Modern any-frequency clock generators use fractional-N or digital PLL architectures to synthesize non-integer output frequencies without needing custom quartz crystals, dramatically simplifying BOM and sourcing for multi-protocol designs.
Key features of the SI5338A-B-GM include an input reference range of 5 MHz to 710 MHz, four independently configurable outputs from 0.16 MHz to 710 MHz, typical RMS jitter below 0.7 ps (12 kHz to 20 MHz), an I2C control interface with on-chip non-volatile EEPROM for stand-alone configuration, and selectable output formats including LVDS, LVPECL, HCSL, CMOS, and SSTL. Supply voltage is 2.97 V to 3.63 V for the core, with separate output driver supplies at 1.71 V to 1.98 V or 2.25 V to 2.75 V.
The device uses a digital PLL architecture with MultiSynth fractional dividers, allowing truly arbitrary frequency synthesis without the classic fractional-N spurs. Internal loop bandwidth and jitter attenuation are user-tunable via I2C registers, enabling optimization for both OCXO-referenced telecom systems and crystal-referenced Ethernet or PCIe applications. The 24-QFN exposed pad provides a thermal resistance of approximately 38 C/W, supporting industrial-grade operation from -40C to +85C.
Typical applications include Ethernet switch and PHY clocking, Fibre Channel and PCIe reference clocks, telecom timing cards with SONET/SDH or SyncE hierarchies, and multi-protocol FPGA or processor clock trees. Industrial test equipment and broadcast video systems also benefit from the four independent outputs on a single footprint.
When designing with this device, place the input reference crystal or oscillator within 5 mm of the REF pin and route the REF clock trace over a continuous ground plane to minimize jitter. The exposed pad must be soldered to a continuous ground plane with at least 16 thermal vias for proper heat dissipation and electrical performance.
This page synthesizes distributor pricing from DigiKey and Mouser, drop-in alternatives in the same 24-QFN package, and practical design notes not found in the manufacturer datasheet. Engineers searching for SI5338A-B-GM datasheets, pinouts, pricing, and cross-references will find consolidated technical information optimized for component selection.
ドロップイン代替品: SI5338A-B-GM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: SI5338A-B-GM （同一形状・フットプリント） — 相違点: Control Interface, MSL Level, Package, Function, Number of Outputs.
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SI5338A-B-GMR
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SI5338B-B-GM
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SI5338A-B05582-GM
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SI5338A-B05923-GM
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SI5338P-B09666-GM
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SI5338A-B-GM 仕様
| 機能 | I2C-Programmable Any-Frequency Clock Generator |
| 出力数 | 4 |
| Input Frequency Range | 5 MHz to 710 MHz |
| Output Frequency Range | 0.16 MHz to 710 MHz |
| Core Supply Voltage | 2.97 V to 3.63 V |
| Output Driver Supply Voltage | 1.71 V to 1.98 V or 2.25 V to 2.75 V |
| Output Formats | LVDS, LVPECL, HCSL, CMOS, SSTL (selectable) |
| RMS Jitter (typ) | <0.7 ps (12 kHz to 20 MHz) |
| Control Interface | I2C (with on-chip non-volatile EEPROM) |
| MultiSynth Technology | Yes (0 ppm synthesis precision per output) |
| パッケージ | 24-QFN (4x4 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (industrial grade) |
| Target Applications | Ethernet, Fibre Channel, PCI Express (PCIe), Telecom |
| RoHS ステータス | Compliant |
| MSLレベル | MSL3 (per JEDEC J-STD-020) |
SI5338A-B-GM ピン構成
| ピン 1 | VDD — Core supply voltage (2.97-3.63 V) |
| ピン 2 | GND — Ground |
| ピン 3 | CLK0 — Output clock 0 (positive) |
| ピン 4 | CLK0_N — Output clock 0 (negative / complementary) |
| ピン 5 | VDDO0 — Output 0 driver supply (1.8 V or 2.5 V) |
| ピン 6 | GND — Ground |
| ピン 7 | CLK1 — Output clock 1 (positive) |
| ピン 8 | CLK1_N — Output clock 1 (negative / complementary) |
| ピン 9 | VDDO1 — Output 1 driver supply |
| ピン 10 | GND — Ground |
| ピン 11 | CLK2 — Output clock 2 (positive) |
| ピン 12 | CLK2_N — Output clock 2 (negative / complementary) |
| ピン 13 | VDDO2 — Output 2 driver supply |
| ピン 14 | GND — Ground |
| ピン 15 | CLK3 — Output clock 3 (positive) |
| ピン 16 | CLK3_N — Output clock 3 (negative / complementary) |
| ピン 17 | VDDO3 — Output 3 driver supply |
| ピン 18 | GND — Ground |
| ピン 19 | SDA — I2C data |
| ピン 20 | SCL — I2C clock |
| ピン 21 | FINC — Frequency increment input (optional) |
| ピン 22 | FDEC — Frequency decrement input (optional) |
| ピン 23 | OE — Output enable (active high) |
| ピン 24 | REF_IN — Reference clock input (5-710 MHz) |
| ピン 25 | EP — Exposed pad (must be soldered to ground plane) |
主な用途
SI5338A-B-GM の用途: 7 件s: Ethernet Switch and PHY Clocking, PCI Express (PCIe) Reference Clock, Telecom Timing and SyncE/SONET Cards, Fibre Channel SAN Infrastructure, FPGA and Processor Clock Tree, Industrial Test and Measurement Equipment, Broadcast Video and Studio Reference.
Ethernet Switch and PHY Clocking
The SI5338A-B-GM is well suited for multi-port Ethernet switch and PHY reference clocking where multiple unrelated frequencies (25 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) must be generated from a single board reference. Its sub-0.7 ps RMS jitter (12 kHz to 20 MHz) and user-selectable LVDS/HCSL outputs meet IEEE 802.3 jitter masks for 1G/10G Ethernet. Placed near the PHY with four dedicated output pairs, it eliminates 3-4 discrete crystal oscillators from the BOM. The I2C interface allows late-stage frequency changes for PHY variants, and the 24-QFN 4x4 mm footprint fits easily under magnetics or behind the PHY stack-up.
おすすめ
PCI Express (PCIe) Reference Clock
The SI5338A-B-GM serves as a 100 MHz HCSL reference clock source for PCIe Gen 1 through Gen 5 endpoints, root complexes, and switches. Per the Skyworks Si5338 datasheet, the device supports HCSL output swing directly without external level translation, and its RMS jitter well below 0.7 ps satisfies PCIe base spec jitter budgets across all generations. The four independent outputs let one SI5338A-B-GM clock a CPU plus three PCIe slots, replacing four HCSL oscillators. Designers should use the Skyworks ClockBuilder Pro tool to set the recommended PLL loop bandwidth for PCIe jitter compliance.
おすすめ
Telecom Timing and SyncE/SONET Cards
For telecom line cards and timing modules, the SI5338A-B-GM synthesizes multiple SyncE/SONET clocks (e.g., 19.44 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz) from a single OCXO or stratum-3 reference. Its programmable loop bandwidth allows optimization for OCXO-referenced holdover and wander performance, while 0 ppm synthesis precision eliminates PLL-induced drift. The exposed-pad 24-QFN package supports the -40C to +85C industrial temperature range required for outdoor telecom equipment, and the I2C interface allows in-service frequency reconfiguration for SONET/SDH payload switching.
おすすめ
Fibre Channel SAN Infrastructure
Storage Area Network (SAN) switches and HBAs in Fibre Channel deployments at 1G/2G/4G/8G/16G FC rates (corresponding to 26.5625 MHz, 53.125 MHz, 106.25 MHz, 212.5 MHz fundamental rates) benefit from the SI5338A-B-GM's any-frequency synthesis and low-jitter HCSL/LVDS outputs. A single SI5338A-B-GM can provide reference clocks for an FC switch ASIC plus multiple FC PHYs, eliminating crystal oscillator stocking SKUs across FC speed grades. The MultiSynth technology eliminates classic fractional-N spurs that would otherwise land in Fibre Channel receiver bandwidths.
おすすめ
FPGA and Processor Clock Tree
Modern FPGAs and SoCs typically require 3-5 reference clocks for transceivers, memory controllers, processing cores, and PCIe interfaces. The SI5338A-B-GM serves as a one-chip clock tree source, generating independent clocks for an FPGA transceiver reference (e.g., 156.25 MHz), memory controller (e.g., 200 MHz), and processor reference (e.g., 100 MHz) from a single board reference. Its 0 ppm precision and sub-0.7 ps jitter keep bit-error rates low in serial links, while the I2C interface allows frequency changes during board bring-up without crystal replacement. The 24-QFN 4x4 mm footprint is far smaller than four separate XOs.
おすすめ
Industrial Test and Measurement Equipment
Test and measurement instruments such as oscilloscopes, BERTs, and signal analyzers require multiple low-jitter reference frequencies for ADC sampling, DAC clocking, and FPGA DSP processing. The SI5338A-B-GM's sub-0.7 ps RMS jitter preserves ADC ENOB, while its any-frequency capability lets a single part generate the ADC sample clock, FPGA fabric clock, and reference clock for the front-end LOs. The 24-QFN industrial-grade package and exposed pad support dense multi-channel T&M board layouts. Designers can re-program frequencies via I2C as new measurement standards are added.
おすすめ
Broadcast Video and Studio Reference
Studio video equipment (e.g., SDI routers, frame synchronizers, audio embedders) requires multiple video reference frequencies (27 MHz for SD-SDI, 74.25 MHz for 720p, 148.5 MHz for 1080p, 297 MHz for 4K UHD-SDI) generated from a single blackburst or tri-level sync input. The SI5338A-B-GM synthesizes all these frequencies with 0 ppm precision and LVDS outputs that drive SDI serializer/cleaner ASICs directly. Its MultiSynth technology avoids the spurious frequencies that classic fractional-N PLLs produce, keeping them out of the video passband and preserving SDI jitter budgets per SMPTE 259M/292M/424M.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI5338A-B-GM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5338A-B-GMR | SI5338B-B-GM | SI5338A-B05582-GM | SI5338A-B05923-GM | SI5338P-B09666-GM |
|---|---|---|---|---|---|---|
| Package | 24-QFN (4x4 mm) | 24-QFN (4x4 mm) - same | 24-QFN (4x4 mm) - same | 24-QFN (4x4 mm) - same | 24-QFN (4x4 mm) - same | 24-QFN (4x4 mm) - same |
| Brand | Skyworks Solutions | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same |
| Max Output Frequency | 710 MHz | 710 MHz | 350 MHz | 710 MHz | 710 MHz | 350 MHz |
| Number of Outputs | 4 | 4 | 4 | 4 | 4 | 4 |
| NVM Configuration | Blank / user-programmable via I2C | Blank / user-programmable | Blank / user-programmable | Factory pre-programmed custom plan | Factory pre-programmed custom plan | Factory pre-programmed custom plan |
| Speed Grade | A (710 MHz) | A (710 MHz) | B (350 MHz) | A (710 MHz) | A (710 MHz) | P (350 MHz pre-prog) |
| RMS Jitter (typ) | <0.7 ps (12 kHz-20 MHz) | <0.7 ps | <0.7 ps | <0.7 ps | <0.7 ps | <0.7 ps |
| Core Supply Voltage | 2.97-3.63 V | 2.97-3.63 V | 2.97-3.63 V | 2.97-3.63 V | 2.97-3.63 V | 2.97-3.63 V |
主な差別化要因
- Any-frequency MultiSynth synthesis with 0 ppm precision on all four outputs simultaneously （vs SI5338B-B-GM (350 MHz grade))
- Patented MultiSynth fractional divider eliminates classic fractional-N spurs （vs SI5338A-B05582-GM (factory pre-programmed))
- Tape-and-reel packaging variant for high-volume assembly （vs SI5338A-B-GMR)
設計ノート
The SI5338A-B-GM exposed pad (pin 25) MUST be soldered to a continuous ground plane with at least 16 thermal vias arranged in a 4x4 grid directly beneath the EP. Per the Si5338 datasheet, an unsoldered EP degrades thermal performance by ~40% and can introduce 1-2 ps of additional jitter. Place input and output bypass capacitors (0.1 uF X7R) within 2 mm of each VDD/VDDO pin. The REF_IN trace should be routed over a continuous ground pour, length-matched to within 1 mm of any other reference routing.
Differential output pairs (CLK0/CLK0_N, etc.) must be routed as 100-ohm differential microstrip or stripline, with intra-pair skew below 2 ps and inter-pair length matching per output format. For HCSL outputs driving PCIe, add the 50-ohm to ground termination at the receiver as specified by PCI-SIG. For LVDS outputs, keep the 100-ohm differential termination at the receiver within 1 inch of the device pins to avoid reflections.
Do NOT leave FINC/FDEC floating when not used - per the Si5338 datasheet, these pins must be tied to ground through 10 kohm resistors or they can inject noise into the PLL. Use ClockBuilder Pro (Skyworks free configuration tool) to generate the correct register sequence and NVM image; do not attempt hand-coded register writes without first consulting the application note AN619. When cascading two SI5338 devices, take the reference output from the master before the receiver PLL bandwidth is engaged, or feedback jitter will accumulate.
Keep the REF_IN crystal or oscillator within 5 mm of pin 24, with the load capacitors placed symmetrically to ground. Isolate the analog VDD supply (pin 1) from the noisy digital VDDO supplies with a ferrite bead and separate decoupling. Per the Skyworks reference design, the SI5338A benefits from a guard ring around the REF_IN pin to prevent digital output switching noise from coupling into the reference path and adding jitter.
コンプライアンス情報
RoHS and REACH compliant per Skyworks product page; lead-free reflow-compatible. Not AEC-Q100 qualified - this part targets industrial/commercial telecom/datacom, not automotive. Halogen-free status not explicitly stated in available data.
